VIA Technologies Apollo Pro133A Guide

Design Guide
VT82C694X
Apollo Pro133A
with VT82C686A
South Bridge
Preliminary Revision 0.5
November 19, 1999
VIA TECHNOLOGIES, INC.

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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 iRevision History
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REVISION HISTORY
Document
Release Date Revision Initials
0.5 11/19/99 Initial Release (Modified from DG694X&596BR070 and DG693A&686AR060) VL, JY,
VH, RC,
SS

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 iTable of Contents
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TABLE OF CONTENTS
Revision History............................................................................................................................................i
Table of Contents..........................................................................................................................................i
List of Figures...............................................................................................................................................i
List of Tables.................................................................................................................................................i
Introduction .................................................................................................................................................1
1.1 About This Design Guide ................................................................................................................................1
1.2 Apollo Pro133A Chipset Overview .................................................................................................................2
1.2.1 VT82C694X Apollo Pro133A North Bridge Features ..................................................................................................2
1.2.2 Super South (VT82C686A) Chipset Features...............................................................................................................3
1.2.3 System Block Diagram................................................................................................................................................4
1.3 System Design Recommendations...................................................................................................................5
Motherboard Design Guidelines ..................................................................................................................7
2.1 Ballout Assignment..........................................................................................................................................7
2.1.1 Apollo Pro133A North Bridge Ballout Assignment......................................................................................................7
2.1.2 "Super South" South Bridge Ballout Assignment.........................................................................................................8
2.2 Motherboard Description................................................................................................................................9
2.2.1 Slot-1 Motherboard Placement and Routing.................................................................................................................9
2.2.1.1 ATX Form Factor for Slot-1 System...................................................................................................................10
2.2.1.2 Micro ATX Form Factor for Slot-1 System.........................................................................................................11
2.2.2 Socket-370 Motherboard Placement and Routing....................................................................................................... 12
2.2.2.1 ATX Form Factor for Socket-370 System........................................................................................................... 13
2.2.2.2 Micro ATX Form Factor for Socket-370 System.................................................................................................14
2.2.3 Printed Circuit Board Description.............................................................................................................................. 15
2.2.3.1 Four-Layer Board...............................................................................................................................................15
2.2.3.2 Six-Layer Board.................................................................................................................................................16
2.2.4 On Board Power Regulation......................................................................................................................................17
2.2.5 Capacitive Decoupling..............................................................................................................................................17
2.2.5.1 Single Slot-1 Processor Capacitive Decoupling...................................................................................................18
2.2.5.2 Single Socket-370 Processor Capacitive Decoupling...........................................................................................19
2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling................................................................................................. 20
2.2.5.4 DRAM Module Capacitive Decoupling .............................................................................................................. 20
2.2.6 Power Plane Partitions ..............................................................................................................................................21
2.2.6.1 Power Plane Partitions for Slot-1 Motherboard ...................................................................................................21
2.2.6.2 Power Plane Partitions for Socket-370 Motherboard ...........................................................................................23
2.2.7 Chipset Power and Ground Layout Recommendations............................................................................................... 25
2.2.8 Power Up Configuration ...........................................................................................................................................27
2.2.8.1 VT82C694X Power Up Strappings.....................................................................................................................28
2.2.8.2 VT82C686A Power Up Strappings.....................................................................................................................28
2.3 General Layout and Routing Guidelines ......................................................................................................29
2.3.1 Trace Attribute Recommendations.............................................................................................................................29
2.3.2 Apollo Pro133A Clock Layout Recommendations..................................................................................................... 30
2.3.2.1 Clock Requirements ...........................................................................................................................................30
2.3.2.2 Clocking Scheme ...............................................................................................................................................31
2.3.2.3 Clock Routing Considerations ............................................................................................................................ 32
2.3.2.4 System Clock Combinations...............................................................................................................................33
2.3.2.5 Host CPU Clock and SDRAM Clock Signals......................................................................................................34

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2.3.2.6 AGP Clock Signals.............................................................................................................................................36
2.3.2.7 PCI Clock Signals..............................................................................................................................................37
2.3.2.8 Miscellaneous Clock Signals ..............................................................................................................................37
2.3.2.9 Clock Trace Length Calculation..........................................................................................................................38
2.3.3 Routing Styles and Topology.....................................................................................................................................40
2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines....................................................................41
2.4.1 Host CPU Interface Layout and Routing Guidelines ..................................................................................................41
2.4.1.1 Slot-1 Host Interface to North Bridge..................................................................................................................41
2.4.1.2 Socket-370 Host Interface to North Bridge.......................................................................................................... 42
2.4.1.3 CPU Host Interface to South Bridge ...................................................................................................................44
2.4.2 Memory Subsystem Layout and Routing Guidelines..................................................................................................46
2.4.2.1 DRAM Routing Guidelines ................................................................................................................................46
2.4.2.2 DRAM Reference Layout................................................................................................................................... 50
2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines ........................................................................................52
2.4.3.1 General Layout and Routing Recommendations..................................................................................................52
2.4.3.2 Vref Characteristics for AGP 4X Mode...............................................................................................................53
2.4.3.3 AGP VDDQ Power Delivery..............................................................................................................................53
2.4.3.4 AGP VDDQ Power Plane Partition..................................................................................................................... 55
2.4.3.5 Optimized Layout and Routing Recommendations..............................................................................................56
2.4.4 PCI Interface Layout and Routing Guidelines............................................................................................................58
2.5 Super South (VT82C686A) Layout and Routing Guidelines .......................................................................59
2.5.1 USB controller..........................................................................................................................................................59
2.5.2 AC’97 Link and Game/MIDI Ports............................................................................................................................61
2.5.2.1 AC'97 Link ........................................................................................................................................................61
2.5.2.2 Game/MIDI ports...............................................................................................................................................62
2.5.3 Hardware Monitoring................................................................................................................................................63
2.5.4 Integrated Super IO Controller ..................................................................................................................................64
2.5.5 System Management Bus Interface............................................................................................................................65
2.5.6 IDE...........................................................................................................................................................................66
2.5.7 Suspend to DRM.......................................................................................................................................................70
2.5.7.1 Suspend DRAM Refresh .................................................................................................................................... 70
2.5.7.2 STR Power Plane Control................................................................................................................................... 71
Timing Analysis and Simulation................................................................................................................73
3.1 SDRAM Timing.............................................................................................................................................73
Electrical Specifications.............................................................................................................................75
4.1 Absolute Maximum Ratings..........................................................................................................................75
4.2 Recommended Operating Ranges.................................................................................................................75
4.3 DC Characteristics ........................................................................................................................................76
4.4 Power Dissipation..........................................................................................................................................76
Signal Connectivity and Design Checklist..................................................................................................77
5.1 Overview........................................................................................................................................................77
5.2 VT82C694X Apollo Pro133A North Bridge .................................................................................................78
5.3 "Super South" South Bridge Controller.......................................................................................................81
5.4 Apollo Pro-133A Design Checklist................................................................................................................90
5.4.1 General Layout Considerations Checklist ..................................................................................................................90
5.4.2 Major Components Checklist ....................................................................................................................................90
5.4.3 Decoupling Recommendations Checklist................................................................................................................... 91
5.4.4 Clock Trace Checklist............................................................................................................................................... 92
5.4.5 Clock Trace Length Calculation................................................................................................................................92

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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5.4.6 Signal Trace Attribute Checklist................................................................................................................................94
Appendices .................................................................................................................................................95
Appendix A - SPKR Strapping Application Circuits..........................................................................................97
Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines ...............................................................99
B.1 Introduction ................................................................................................................................................................99
B.2 Layout Recommendations ......................................................................................................................................... 100
B.2.1 Component Placement........................................................................................................................................ 100
B.2.2 Ground and Power Planes:.................................................................................................................................. 103
B.2.3 Routing Guidelines............................................................................................................................................. 105
Appendix C - Apollo Pro133A Reference Design Schematics...........................................................................109

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 iList of Figures
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LIST OF FIGURES
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge ............................................................4
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View)............................................................7
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)................................................8
Figure 2-3. ATX Placement and Routing Example for Slot-1 System...........................................................................................10
Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System................................................................................ 11
Figure 2-5. ATX Placement and Routing Example for Socket-370 System...................................................................................13
Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System ........................................................................14
Figure 2-7. Four-Layer Stack-up with 2 Signal Layers and 2 Power Planes...............................................................................15
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes.................................................................................. 16
Figure 2-9. Example of Via Location......................................................................................................................................... 17
Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor................................................................................18
Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor........................................................................ 19
Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A.....................................................................20
Figure 2-13. Decoupling Capacitor Placements for DRAM Modules..........................................................................................20
Figure 2-14. ATX Power Plane Partitions for Slot-1 System....................................................................................................... 21
Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System............................................................................................22
Figure 2-16. ATX Power Plane Partitions for Socket-370 System............................................................................................... 23
Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System ....................................................................................24
Figure 2-18. VT82C694X Power and Ground Layout ................................................................................................................25
Figure 2-19. VT82C686A Power and Ground Layout ................................................................................................................26
Figure 2-20. A Typical Example of a 3-pin Jumper Strapping Circuit.........................................................................................27
Figure 2-21. System Clock Connections.....................................................................................................................................30
Figure 2-22. Apollo Pro133A Chip Clocking Scheme.................................................................................................................31
Figure 2-23. Clock Trace Spacing Guidelines............................................................................................................................32
Figure 2-24. Effect of Ground Plane to a Clock Signal ..............................................................................................................32
Figure 2-25. Series Termination for Multiple Clock Loads......................................................................................................... 32
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System...........................................................34
Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems..................................................35
Figure 2-28. AGP Clock Layout Recommendations....................................................................................................................36
Figure 2-29. PCI Clock Layout Recommendations.....................................................................................................................37
Figure 2-30. Daisy Chain Routing Example...............................................................................................................................40
Figure 2-31. Point-to-Point and Multi-Drop Topology Examples...............................................................................................40
Figure 2-32. Alternate Multi-Drop Topology Example...............................................................................................................40
Figure 2-33. Slot-1 Host Interface Topology Example................................................................................................................ 41
Figure 2-34. Socket-370 Host Interface Topology Example........................................................................................................42
Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X....................................................................43
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing....................................................... 44
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU......................................................................45
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU..............................................................45
Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots................................................................................................ 47
Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots ..............................................................................................48
Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots.......................................................................................................49
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots.................................................................................................50
Figure 2-43. DRAM Placement for 133MHz Timing Consideration............................................................................................50
Figure 2-44. Layout Example of Three-DRAM DIMM Slots....................................................................................................... 51
Figure 2-45. General Layout Recommendations of AGP 4X Interface ........................................................................................52
Figure 2-46. AGP 2X and 4X Mode Sharing Circuit ..................................................................................................................53
Figure 2-47. VDDQ Voltage-Switching Application Circuit.......................................................................................................54
Figure 2-48. VDDQ Voltage-Switching Application Circuit (II).................................................................................................54
Figure 2-49. AGP VDDQ Power Plane Partition Example......................................................................................................... 55
Figure 2-50. AGP 4X Interface Layout Example......................................................................................................................... 57
Figure 2-51. Topology Example of AGP and PCI Interface......................................................................................................... 58
Figure 2-52. USB Over-Current Scan Logic ..............................................................................................................................59
Figure 2-53. USB Differential Signal Routing Example ..............................................................................................................60

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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Figure 2-54. AC'97 Link Example..............................................................................................................................................62
Figure 2-55. MIDI/Game Port Application Circuit ....................................................................................................................62
Figure 2-56. Hardware Monitoring Application Circuit............................................................................................................. 63
Figure 2-57. System Management Bus Interface ........................................................................................................................65
Figure 2-58. ISA Bus SA[15:0] / SDD[15:0] Sharing Circuitry..................................................................................................66
Figure 2-59. IDE Interfaces Layout Guidelines.......................................................................................................................... 67
Figure 2-60. Ultra DMA/66 Placement and Routing Example....................................................................................................68
Figure 2-61. Ultra DMA/66 Application Circuit ......................................................................................................................... 69
Figure 2-62. Suspend DRAM Refresh Application Circuit.......................................................................................................... 70
Figure 2-63. STR State Power Plane Control Application Circuit ..............................................................................................71
Figure 3-1. CPU Read from SDRAM (SL=2) .............................................................................................................................73
Figure 3-2. CPU Post Write to SDRAM (SL=2).........................................................................................................................74
Figure A-1. VT82C686A SPKR Pin Transistor Driver Solution (I) .............................................................................................97
Figure A-2. VT82C686A SPKR Pin Inverter Driver Solution (II)................................................................................................97
Figure B-1. AC’97 Audio Codec and Game/MIDI Port Block Diagram......................................................................................99
Figure B-2. AC’97 Audio Codec and GAME/MIDI Port Placement Example ........................................................................... 100
Figure B-3. Ground Layer Layout Example............................................................................................................................. 103
Figure B-4. Power Layer Layout Example............................................................................................................................... 104
Figure B-5. Component Layer Layout Example ....................................................................................................................... 106
Figure B-6. Solder Layer Layout Example............................................................................................................................... 106
Figure C-1. Apollo Pro133A Reference Component Placement................................................................................................ 110

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 iList of Tables
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LIST OF TABLES
Table 2-1. Different Board Size Lists for Slot-1 System ................................................................................................................9
Table 2-2. Different Board Size Lists for Socket-370 System....................................................................................................... 12
Table 2-3. High Frequency and Bulk Decoupling Capacitor Distribution around Socket-370.....................................................19
Table 2-4. Power-Up Configuration for VT82C694X.................................................................................................................28
Table 2-5. Power-Up Configuration for VT82C686A.................................................................................................................28
Table 2-6. Recommended Trace Width and Spacing................................................................................................................... 29
Table 2-7. Apollo Pro133A Clock Synthesizer Requirements...................................................................................................... 30
Table 2-8. Apollo Pro133A System Clock Combinations ............................................................................................................33
Table 2-9. Host Control Signals to South Bridge........................................................................................................................44
Table 2-10. Memory Subsystem Signals.....................................................................................................................................46
Table 2-11. VT82C694X AGP 4X Signal Groups .......................................................................................................................52
Table 2-12 Universal Serial Bus (USB) Signals .........................................................................................................................59
Table 2-13. Signal Description of AC'97 Link and Game/MIDI Ports.........................................................................................61
Table 2-14. Resume Events Supported in Different Power States................................................................................................71
Table 4-1. Absolute Maximum Ratings....................................................................................................................................... 75
Table 4-2. Recommended Operating Ranges..............................................................................................................................75
Table 4-3. DC Characteristics...................................................................................................................................................76
Table 4-4. Maximum Power Dissipation....................................................................................................................................76
Table 5-1. VT82C694X North Bridge Connectivity.....................................................................................................................78
Table 5-2. VT82C686A South Bridge Connectivity..................................................................................................................... 81
Table 5-3. Recommended Trace Width and Spacing................................................................................................................... 90
Table 5-4. Maximum Accumulated Trace Length .......................................................................................................................94
Table B-1. Decoupling Capacitor List ..................................................................................................................................... 101
Table B-2. AC-Coupling Capacitors for Audio Input Signals.................................................................................................... 101
Table B-3. AC-Coupling Capacitors for Audio Input Signals.................................................................................................... 102
Table B-4. Signal Groups Associated with Their Audio Ground Plane...................................................................................... 104
Table B-5. Routing Guidelines for Signal Nets......................................................................................................................... 107
Table B-6. Routing Guidelines for Power and Ground Nets ..................................................................................................... 107

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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 1Introduction
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INTRODUCTION
This document provides design guidelines for motherboard manufacturers on developing single Slot-1 or Socket-370 processor
and Apollo Pro133A (VT82C694X) based systems. All the major underlying subsystems, especially Host Interface and Memory
subsystems, related to the motherboard design are described in detail. General layouts, routing guidelines and power requirements
of each subsystem are presented.
1.1 About This Design Guide
A brief description of each chapter is given below:
Chapter 1: Introduction.
An overview of Apollo Pro133A reference design features is given in this chapter along with general recommendations on
Pro133A system design.
Chapter 2: Motherboard Design Guidelines.
General design schemes and recommended layout rules are shown in chapter 2. It begins with the 510-pin BGA ballout
assignment. The following sections contain placement and routing of a motherboard, PCB stack-up information and power
requirements for a desktop or a mobile system. Detailed placement, layout, and routing guidelines for each bus or subsystem
(Host bus, Memory subsystem, AGP bus and PCI bus) are described in section 2.4.
Chapter 3: Timing Diagram Analysis.
133 MHz timing analyses for memory read/write cycles are discussed in Chapter 3.
Chapter 4: Electrical Specifications.
The electrical specifications for the VT82C694X North Bridge are listed in this chapter.
Chapter 5: Signal Connectivity and Design Checklist.
The final chapter provides signal connection tables as a brief reference for hardware design engineers who are experienced in PC
motherboard design. Also design checklists are included that can be used for reviewing Pro133A system designs.
Appendices: Reference Design Schematics.
Appendix A shows two power-up strapping circuits for the VT82C686A SPKR pin which determines the function of the
Secondary IDE disk data bus pins (SDD[15..0]) to be either SDD[15..0] (SPKR strapped low) or Audio/Game port functions
(SPKR strapped high).
Appendix B describes the Printed Circuit Board (PCB) layout recommendations for VIA VT1611A (AC’97 audio codec) and
Game/MIDI port in a motherboard design.
Reference schematics for an Apollo Pro133A system design with VT82C686A South Bridge are shown in Appendix C.

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1.2 Apollo Pro133A Chipset Overview
The Apollo Pro133A chip set consists of the VT82C694X system controller (510-pin BGA) and the VT82C686A PCI to ISA
bridge (352-pin BGA). The features for both chips are listed below and a typical system block diagram is shown in this section.
1.2.1 VT82C694X Apollo Pro133A North Bridge Features
Apollo Pro133A (VT82C694X) is a Slot-1 and Socket-370 system logic north bridge with the addition of 133 MHz capability for
both the CPU and SDRAM interfaces. Apollo Pro133A may be used to implement both desktop and notebook personal computer
systems from 66MHz to 133MHz based on 64-bit Slot-1 (Intel Pentium-II) and Socket-370 (Intel and Celeron) processors. The
primary features of the Apollo Pro133A-North Bridge are:
•Slot-1 or Socket-370 CPU (Front Side Bus) Interface (66 / 100 / 133MHz)
•DRAM Memory Interface (66 / 100 / 133MHz)
•AGP Bus Interface (66MHz)
•PCI Bus Interface (33MHz)
•Mobile Power Management
•510-pin BGA Package
The DRAM interface supports eight banks of DRAMs (4 DIMM sockets) although VIA recommends implementation of three
DIMMs maximum for operation of the memory interface at 133 MHz. Total memory supported is 1.5 GB independent of the
number of DIMMs implemented. The DRAM controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous
DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability separately selectable
on a bank-by-bank basis. The DRAM controller can run synchronous with the host CPU bus (66 /100 /133 MHz) or synchronous /
pseudo-synchronous with the AGP bus (66 / 133 MHz) with built-in PLL timing control. The DRAM interface can also run either
slower or faster than the CPU interface (both combinations of 66 / 100 MHz or both combinations of 100 / 133 MHz).
The AGP controller supports full AGP v2.0 capability for maximum bus utilization including 2x and 4X mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-write
request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep pipelined
and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI remapping
control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and Windows-98 /
NT5 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia accelerators.
The VT82C694X supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five
levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are
also implemented for further improvement of overall system performance.
For sophisticated power management, the Apollo Pro133A provides independent clock stop control for the CPU / SDRAM, PCI,
and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for
the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C686A south bridge chip, a complete
power conscious PC main board can be implemented with no external TTLs.

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1.2.2 Super South (VT82C686A) Chipset Features
The VT82C686A Super-IO PCI Integrated Peripheral Controller (PSIPC) is a high integration, high performance, power efficient
and high compatibility device that supports Intel and non-Intel based processors plus PCI bus bridge functionality to make a
complete Microsoft PC98-compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C686A
includes the following standard intelligent peripheral controllers:
•Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands
•4-Port Universal Serial Bus (USB) controller that is USB v1.1 and Universal HCI v1.1 compliant
•Keyboard controller with PS2 mouse support
•Real Time Clock (RTC) with 256 bytes extended CMOS
•Power management (PM) functionality compliant with ACPI and legacy APM requirements
•Hardware monitoring subsystem for managing system/motherboard voltage levels, temperatures, and fan speed
•Full System Management Bus (SMBus) interface
•Two 16550-compatible serial I/O ports with infrared communication port option
•Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system.
•Two game ports and one MIDI port
•ECP/EPP-capable parallel port
•Standard Floppy Disk Drive (FDD) interface
•Distributed DMA capability for support of ISA legacy DMA over the PCI bus. Serial IRQ is also supported for docking
and non-docking applications
•Plug and play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to
any interrupt channel

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1.2.3 System Block Diagram
A block diagram of a typical Apollo Pro133A based system with a VT82C686A South Bridge is shown in Figure 1-1. The Apollo
Pro133A supports a single processor including 64-bit Slot-1 (Intel Pentium II TM) or Socket-370 (Intel Celeron TM) CPUs at 66
MHz, 100 MHz or the maximum 133MHz system bus frequency.
PCI BUS
Hardware
Monitoring
AC'97
Codec
USB x4
ISA BUS
DRAM Interface
HOST BUS
BOOT
ROM
Keyboard
& Mouse
IDE x2
PM Control,
GPIO, Reset
Super IO
Serial Port x2
Infrared Port x1
Parallel Port x1
FDD x2
VT82C694X
VT82C686A
Main
Memory
(DRAM)
Single Slot-1 CPU
PCI4 PCI2 PCI3 PCI1
ISA2
ISA1
Single
Socket-370
CPU
or
AGP(4X) BUS
AGP Slot or
3D Graphics
Controller
PCI5
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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1.3 System Design Recommendations
The VT82C694X Apollo Pro133A north bridge and VT82C686A south bridge form one of VIA's most optimized chipset
combinations for single Slot-1or Socket-370 based PC systems. On an ATX form factor, for example, the optimized system
specification for such a combination is listed below:
•Single Slot-1 or Socket-370 CPU (66 / 100 / 133MHz)
•Apollo Pro133A single chip clock synthesizer
•Apollo Pro133A North Bridge (Host/PCI) Controller
•VT82C686A South Bridge (PCI/ISA) Controller
•Four DIMM Slots (maximum 2 GB and 133MHz memory frequency)
•One AGP Slot (66MHz)
•Two PCI Slots (33MHz)
•One ISA Slots (8/16MHz)
•One AMR Slot (24.576MHz)
•One 2MB Flash ROM for system BIOS
•One AC’97 Codec Chip (VT1611) to cooperate with an AC’97 Link Controller
•Four Universal Serial Bus Ports
•PS2 Keyboard/Mouse Support
•Two Enhanced IDE Interfaces supporting both ATA-33 and ATA-66
•One Floppy Drive Interface
•One Infrared Interface
•Various Hardware Monitoring functions supporting 5 positive voltages, 3 temperatures, and 2 fan-speed inputs
•One Parallel Port and Two Serial Ports
•Three Audio Jacks including Audio In, Audio Out and Mic In
•One MIDI Port
•One Game Port
For the rest of this document, the specification above will be used as a reference example for component placement and PCB
layout.

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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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MOTHERBOARD DESIGN GUIDELINES
This chapter describes general design schemes and recommended layout rules. It begins with the 510-pin BGA (Pro133A north
bridge) and 352-pin BGA (south bridge) ballout assignments. The following section contains the placement and routing of a
motherboard, PCB stack-up information and power requirements for a desktop system. Detailed placement, layout, and routing
guidelines for each bus or subsystem (Host bus, Memory subsystem, AGP bus and PCI bus) are described in section 2.4.
2.1 Ballout Assignment
Basically, the chipset ballout plays an important role in motherboard designs. It can determine the quality of the Printed Circuit
Board (PCB) layout. The reliability of a motherboard partially depends on the ballout of both the North Bridge and the South
Bridge. To achieve a cost effective and compact 4-layer motherboard, the ballouts should be well defined because they have an
inseparable relationship with component placement and PCB layout.
2.1.1 Apollo Pro133A North Bridge Ballout Assignment
Ballout of the Apollo Pro133A North Bridge is designed to minimize the number of crossover signals. Figure 2-1 shows the four
major signal group quadrants of the Apollo Pro133A Ballout. They are Host, Memory, AGP and PCI interfaces. Please refer to
the VT82C694X datasheet for more details on ball assignments.
1
A
Apollo Pro-133A
VT82C694X
510-PIN BGA Memory
Host
AGP
PCI
(Top View)
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View)

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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2.1.2 "Super South" South Bridge Ballout Assignment
Ballout of the VIA "Super South" South Bridge is designed to minimize the number of crossover signals. Similarly to Figure 2-1,
the major signal group quadrants are shown in Figure 2-2. They are PCI, ISA, Hardware Monitoring, IDE1, IDE2 (shared with
Audio/Game), Super IO (including FDC, COM, LPT, and Infrared interface (not shown) ), USB, Keyboard & Mouse, and a group
of Power Control, GPIO & Reset. Please refer to the VT82C686A datasheet for more details on these ball assignments.
ISA
352-PIN BGA
SUPER SOUTH
VT82C686A
USB Keyboard
& Mouse FDC COM LPT
PCI
IDE1
IDE2
(Audio/Game)
Hardware
Monitoring
Power Control,
GPIO & Reset
1
A
(Top View)
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)
Package Information:
•The VIA VT82C694X Apollo Pro133A North Bridge is a 510-pin Ball Grid Array (BGA) package. The package size is
35mm x 35mm and the grid matrix is 26x26.
•The VIA "Super South" South Bridge (VT82C686A) is a 352-pin BGA package. The package size is 27mm x 27mm and
the grid matrix is 20x20.

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2.2 Motherboard Description
This section illustrates proposed component placements for an Apollo Pro133A based motherboard with different system
configurations to achieve maximum optimization. The description of the Printed Circuit Board (PCB) for a motherboard is also
given.
2.2.1 Slot-1 Motherboard Placement and Routing
For Slot-1 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the two
most popular form factors (ATX and micro-ATX) are shown in figures 2-3 and 2-4 respectively. Detailed layout guidelines and
signal routings for the Pro133 chipset will be addressed later in section 2.4.
Each figure shows a full size of its respective form factor. The empty area at the bottom of each placement diagram can be
eliminated to reduce the board size. Table 2-1 shows the full size and the suggested compact size for each form factor
implementation.
Table 2-1. Different Board Size Lists for Slot-1 System
Form Factor Type Full size Compact Size Specification
ATX 12" x 9.6" (30.5cm x 24.5cm) 12" x 7.9" (30.5cm x 20cm) 1 AGP, 5 PCI, 1 ISA, 1 AMR, 3 DIMM
Micro-ATX 9.6" x 9.6" (24.5cm x 24.5cm) 9.6" x 7.9" (24.5cm x 20cm) 1 AGP, 2 PCI, 1 ISA, 1 AMR, 2 DIMM

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2.2.1.1 ATX Form Factor for Slot-1 System
A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in
Figure 2-3. The major components on the board are single Slot-1 CPU, five PCI slots, one AMR, one ISA slot and three DIMM
slots. This figure shows an ATX motherboard placement as a reference only. The placement should be re-evaluated if a different
combination of AGP, PCI and ISA slots and other motherboard peripherals is desired.
Back Panel Area
VT82C
686A
IDE1
IDE2 FDC
CLK
GEN.
Host
AGP
PCI
DRAM
IDEISA
VT82C
694X
0"
6"
5"
4"
3"
2"
1"
9"
8"
7"
9.6"
Figure 2-3. ATX Placement and Routing Example for Slot-1 System