Advantech DSPC-8682 User manual

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DSPC-8682
Octal-TMS320C6678 DSP PCI-E FLCard
H/W Manual
Author:
Status:
Version
1.0
Document ID:
Location:

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Cont nt
1. GENERAL ............................................................................................................. 6
1.1 G ENERAL I NTRODUCTION ..............................................................................................................................................6
1.2 P RODUCT S PECIFICATIONS .............................................................................................................................................6
1.3 DSPC-8682 B LOCK D IAGRAMS .....................................................................................................................................9
1.4 DSPC-8682 PCI-E CARD P LACEMENT ..........................................................................................................................10
2. HARDWARE SPECIFICATION ............................................................................... 11
2.1 P OWER F EED ............................................................................................................................................................ 11
2.2 P OWER D ISTRIBUTION ...............................................................................................................................................11
2.3 P OWER B UDGET .......................................................................................................................................................14
2.4 P OWER S EQUENCE ....................................................................................................................................................15
2.5 P LATFORM C LOCK ......................................................................................................................................................17
2.6 R ESET B LOCK D IAGRAM ..............................................................................................................................................22
2.7 R ESET S EQUENCE .......................................................................................................................................................23
2.8 DSP (TI TMS320C6678) B LOCK D IAGRAM .................................................................................................................24
2.9 M EMORY (DDR3) ....................................................................................................................................................24
2.10 SRIO INTERFACE .......................................................................................................................................................24
2.11 PCI-E INTERFACE .......................................................................................................................................................25
2.12 E THERNET MAC .......................................................................................................................................................26
2.13 H YPER L INK INTERFACE ................................................................................................................................................27
2.14 FGPA XC3S200AN..................................................................................................................................................28
2.15 LED S ......................................................................................................................................................................30
3. IO CONNECTOR .................................................................................................. 32
3.1 C ONNECTOR O VERVIEW ..............................................................................................................................................32
3.2 T HE PEX8748, BCM5482S AND CPS1616 BOUNDARY SCAN CONNECTOR ........................................................................33
3.3 TMS320C6678 B OUNDARY S CAN C ONNECTOR ............................................................................................................34
3.4 60 PINS DSP EMULATOR CONNECTOR ...........................................................................................................................34
3.5 RJ45 LAN CONNECTOR ..............................................................................................................................................37
3.6 XILINX XC3S200AN JTAG INTERFACE ........................................................................................................................38
3.7 DC 12V ATX POWER CONNECTOR ...............................................................................................................................39
3.8 FAN CONNECTOR ......................................................................................................................................................40
3.9 FAN CONNECTOR ......................................................................................................................................................41
4. JUMPER AND SWITCH SETTING .......................................................................... 42
5. MECHANICAL DRAWING .................................................................................... 46

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Figur
FIGURE 1: DSPC-8682 SYSTEM BLOCK DIAGRAM .............................................................................. 9
FIGURE 2: DSPC-8682 PCI-E CARD PLACEMENT ............................................................................... 10
FIGURE 3: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP0, DSP1, DSP6 AND DSP7 .................... 11
FIGURE 4: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP2, DSP3, DSP4 AND DSP5 .................... 12
FIGURE 5: POWER DISTRIBUTION BLOCK DIAGRAM ....................................................................... 13
FIGURE 6: DSPC-8682 OVERALL POWER SEQUENCE ........................................................................ 15
FIGURE 7: POWER DISTRIBUTION ON DSPC-8682 PCI-E CARD ......................................................... 16
FIGURE8: DSPC-8682 CARRIER CLOCK FEEDING DIAGRAM .............................................................. 21
FIGURE9: DSPC-8682 RESET BLOCK DIAGRAM ................................................................................ 22
FIGURE10: THE DSP RESET SEQUENCE ON DSPC-8682 ..................................................................... 23
FIGURE11: TI TMS320C6678 BLOCK DIAGRAM................................................................................ 24
FIGURE12: SERIAL RAPIDIO RING ................................................................................................... 25
FIGURE13: PCIE INTERCONNECTION ............................................................................................... 26
FIGURE14: LAN INTERCONNECTION ............................................................................................... 27
FIGURE15: HYPERLINK CONNECTION ............................................................................................. 28
FIGURE16: FPGA CONNECTION ...................................................................................................... 29
FIGURE17: TOP SIDE LED LOCATION ............................................................................................... 30
FIGURE18: CONNECTOR OVERVIEW ............................................................................................... 32
FIGURE19:CN1, BOUNDARY SCAN FOR PEX748, BCM5482S AND CPS1616 ...................................... 33
FIGURE20: CN2, THE BOUNDARY SCAN FOR THE DSP FARM............................................................ 34
FIGURE21: CN3, TI 60-PIN EMULATION CONNECTOR....................................................................... 35
FIGURE22: CONNECTION THE XDS560V2 STM EMULATOR .............................................................. 35
FIGURE23: 60-PIN HEADER ORIENTATION ...................................................................................... 35
FIGURE24: THE CONNECTION WITH TI XDS560V2 STM EMULATOR ................................................. 36
FIGURE25: CN5, RJ45 LAN PORT ..................................................................................................... 37
FIGURE26: CN5, THE FPGA JTAG FOR FIRMWARE UPDATE .............................................................. 38
FIGURE27: CN6, 12V CONNECTOR .................................................................................................. 39
FIGURE28: CN7, FAN CONNECTOR .................................................................................................. 40
FIGURE29: CN8, FAN CONNECTOR .................................................................................................. 41
FIGURE30: THE SW1 ON DSPC-8682 PCIE CARD .............................................................................. 42

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FIGURE31: THE SW1 SCHEMATIC .................................................................................................... 42
FIGURE32: THE SW2 SCHEMATIC .................................................................................................... 44
FIGURE33: DSPC-8682 TOP SIDE ..................................................................................................... 46
FIGURE34: DSPC-8682 FRONT SIDE ................................................................................................ 46
FIGURE 35: DSPC-8682 BOTTOM SIDE ............................................................................................ 47

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Tabl
TABLE 1: DSPC-8682 POWER BUDGET ............................................................................................ 14
TABLE 2: SYSTEM POWER SEQUENCE PARAMETER ......................................................................... 16
TABLE 3: CLOCK DOMAINS ............................................................................................................. 20
TABLE 4: PCI-E PORT MAPPING ON PEX8748 .................................................................................. 25
TABLE5: PCI-E SWITCH LED ............................................................................................................. 30
TABLE6: FPGA LED ......................................................................................................................... 30
TABLE7: CN1 PIN ASSIGNMENT ...................................................................................................... 33
TABLE 8: CN2 PIN ASSIGNMENT ..................................................................................................... 34
TABLE 9: CN3 DSP EMULATOR PIN ASSIGNMENTS .......................................................................... 36
TABLE10: CN4 PIN ASSIGNMENT .................................................................................................... 38
TABLE11: CN5 PIN ASSIGNMENT .................................................................................................... 38
TABLE12: CN6 PIN ASSIGNMENT .................................................................................................... 39
TABLE13: CN7 PIN ASSIGNMENT .................................................................................................... 40
TABLE14: CN8 PIN ASSIGNMENT .................................................................................................... 41
TABLE15: THE SW1 SETTING TABLE ................................................................................................ 43
TABLE16: THE SW2 SETTING TABLE ................................................................................................ 45

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1. G n ral
1.1 G n ral Introduction
This document is the H/W user manual of DSPC-8682, the PCI-E x8 Full-Length add-on card with
octal-TMS320C6678 DSPs. DSPC-8682 is composed of eight TI TMS320C6678 DSPs, one PCI-E GEN3
switch PEX8748, one SRIO GEN2 switch CPS1616 and two RJ4 LAN ports.
1.2 Product Sp cifications
Below information describes the components designed on DSPC8682E PCI-E card.
DSP
TI TMS320C6678 Multi-core Fixed and Floating-Point Digital Signal Processor.
DSP Memory
1024MB or 2048MB memory size on each DSP composed of 64-bit data width with four 2G
or 4G bits DDR3-1333 x16 memory chips. Refer below list for detail.
Revision PCB SN PCB Rev Memory
X 19C2868200 A101-1 Samsung 2G bits
X 19C2868201-01
A102-1 Micron 4G bits
Rev.0 19C2868201-01
A102-1 Samsung 4G bits
Refer to blow picture to see the PCB SN
Octal-TMS320C6678 DSP PCI-E FL Card contains very delicate integrated circuit chips.
In order to protect Octal-TMS320C6678 DSP PCI-E FL Card from static electricity, you should
follow some precautions whenever you work on your computer.
1. Turn off your computer and unplug power supply.
2. Use a grounded wrist strap before handling computer components. If you do not have one,
touch both of your hands to a safely grounded object or to a metal object, such as the power
supply case.
3. Plug in ATX power connector (CN6) first before turn on your computer. Some volt ge’s
power source of oct l c rd comes from 6-pin ATX power connector.

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FPGA
 XILINX XC3S200AN
Handle the DSPs’ interrupt events, booting configurations, power sequences, reset sequences
and PHY LED control, programming clock generator of CDCE6200 and the LVDS clock buffers.
PCI-express Switch
 PEX8748 (48 lanes / PCI-E GEN3)
Upstream port: PCI-E x8 GEN3 to HOST, Downstream port: PCI-E GEN2x2 4-port to eight DSPs.
Ethernet PHY
 BCM 482S
Support 10/100/1000 Mb/s with 1000BASE-T interface.
I/O Expansion
 Standard PCI-E x8 golden finger
I/O connector
 CN1: The PEX8748, BCM 482S and CPS1616 boundary scan connector.
 CN2: The DSP Boundary Scan connector.
 CN3: TI 60 pins DSP emulator connector.
 CN4: RJ4 connectors for LANs.
 CN : FPGA JTAG connector.
 CN6: DC 12V ATX power connector.
 CN7: FAN connector for the heat sink.
 CN8: FAN connector for the heat sink.
 COM1: 3 pins UART connector.

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 PMBUS1: UCD9244 PMBUS connector.
 60V2_PWR1: XDS 60v2 power connector.
Indicator
 Four LEDs, FPGA LED1 to FPGA LED4, are used for the FPGA XC3S200AN debugging.
 LED D1 indicates the error event of CPS1616.
 LED D3 indicates the error event of PEX8748.
 LED D4 indicates the interrupt event of PEX8748.
 LED SYSPG_D1 indicates that all power rails are stable.
EEPROM
 Eight pieces of 1M bits I2C EEPROM are attached to eight DSPs respectively. The EEPROM is
contained of the DSP boot code and the initializations for the first boot while the card
power-on and then branch to PCI-E interface for the second boot by the HOST computer.
 One piece of 128kbit SPI EEPROM is attached to PCI-E switch (PEX8748) for specific port
configurations.
 One piece of 64kbit I2C EEPROM is attached to SRIO switch (CPS1616) for port’s routing
table configurations.
Power Requirement
 12V and 3.3V from PCI-E golden finger.
 12V from ATX power connector.
OS Verification
 Booting image (TBD).
 Application Program (TBD).
Environments
 Operating temperatures: - ° C to 4 ° C (TBD)
 Storage temperatures: -20 ° C to 70 ° C
 Relative humidity: % to 9 % (Non-condensing)
Certification
 CE/ FCC Class A
 Compliant with RoHS

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1.3 DSPC-8682 Block Diagrams
The internal connections on DSPC-8682 PCI-E card are described and shown as below figures. The
whole system interface block diagram for the DSPC-8682 board is shown as Figure 1 Each
TMS320C6678 DSP contains several interfaces such as DDR, HyperLink, Serial RapidIO, PCI-E, and
SGMII for Ethernet connection.
Figure 1: DSPC-8682 System Block Diagram
PCIEx2
PCIEx2
PCIEx2
PCIEx2
PCIEx2
PCIEx8
PCIEx2
PCIEx2
PCIEx2
DSP5 Block DSP4 Block
DSP3 BlockDSP2 BlockDSP1 Block
DSP7 Block DSP6 Block
Hyperlink
Hyperlink
Hyperlink
Hyperlink
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
SGMII
SRIOx1
SGMII
SRIOx1SRIOx1
SGMII SGMII
SRIOx1
Switch
21x21mm
CPS-1616
IDT
SRIOx1
SGMII*1
SRIO Gen2)
12Ports/48Lanes
PEX8748
PLX
TMS320C6678
DSP0 Block
PCIEx8 Gen3)
SGMII
SRIOx1
SGMII
SRIOx1
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
PCIEx8 Gen3)
BCM5482S
Broadcom
RJ45
W/ Xfmr
RJ45
W/ Xfmr
SGMII&MDIO
&MDC(5482S input)
SGMII&MDIO&MDC(5482S input)
4Gb
x16b
DDR3
24x24mm
TI
SGMII[1]x1
DDR3-1333
4Gb*4
15W
DSP0~7
SRIO[1]x1
SGMII[0]x1
SRIO[0]x1
PCIE[0:1]x2
SRIO[2:3] x2
Hyperlink
I2C
EEPROM
128k-byte
DSP Block
TMS320C6678

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1.4 DSPC-8682 PCI-E card Plac m nt
Below figure shows main components on DSPC-8682. It’s only for reference if user needs to learn
specific DSP or want to find a key chip on the card during developing.
Figure 2: DSPC-8682 PCI-E card Placement

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2. Hardwar Sp cification
2.1 Pow r F d
The power source of DSPC-8682 is provided by two power rails, 12V and 3.3V from host, via PCI-E x8
golden finger and 12V from ATX power connector.
2.2 Pow r Distribution
The major power on DSPC-8682 is illustrated as below Figure3, Figure4 and Figure . User could refer
to DSPC-8682 schematics for more details regarding the power supplies on DSPC-8682.
Figure 3: Power Distribution Block Diagram for DSP0, DSP1, DSP6 and DSP7
VCC1P5
DVDD1P8
VCC1P0
DSP7
VID
1.8V/0.416A
1.5V/1.3A
0.75V
Adjus table Core
(0.9V – 1.1V) 10A VCC0P75
1.0V/8A
DSP6
VID
VCC0P75
VID
Adjus table Core
(0.9V – 1.1V) 10A
DSP1
1.5V/1.3A
1.8V/0.416A
1.0V/8A
Adjus table Core
(0.9V – 1.1V) 10A
0.75V
DVDD1P8
VCC1P0
VCC1P5
UCD74110
DDR3
#1
UCD9244
SmartReflex
PMbus
V4
V2
V3
V1
4
4
DSP6_VartibleCore_1.0V
DSP1_VartibleCore_1.0V
DSP0_VartibleCore_1.0V
4
4
DSP7_VartibleCore_1.0V
PWM
PWM
DSP0
TMS320C6678
PWM
PWM
PMbus_CLK
PMbus_Alert
PMbus_Cntrl
GPIO_power_good
PMbus_DATA
0.75V
VCC1P0
1.5V/1.3A
1.8V/0.416A
1.0V/8A Adjustable Core
(0.9V – 1.1V) 10A
DVDD1P8
VCC1P5
VCC0P75
1.0V/8A
1.8V/0.416A
1.5V/1.3A
0.75V
15A Max 15A Max
15A Max
15A Max
TMS320C6678 TMS320C6678
TMS320C6678
UCD74110
UCD74110 UCD74110
VCC1P5
DVDD1P8
VCC1P0
VCC0P75
VID
DDR3 DDR3
DDR3

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Figure 4: Power Distribution Block Diagram for DSP2, DSP3, DSP4 and DSP
UCD74110
UCD74110
UCD74110
15A Max 15A Max
15A Max
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
VID
DSP2
0.75V
1.5V/1.3A
1.8V/0.416A
15A Max
Adjustable Core
(0.9V – 1.1V) 10A
VID
DSP5
1.0V/8A
VID
DSP3
Adjustable Core
(0.9V – 1.1V) 10A
Adjustable Core
(0.9V – 1.1V) 10A
1.0V/8A
1.8V/0.416A
1.5V/1.3A
0.75V
DDR4
PMbus
SmartReflex
UCD9244 #2
V3
V2
V4
4
4
V1
DSP4_VartibleCore_1.0VDSP2_VartibleCore_1.0V
DSP5_VartibleCore_1.0V
4
4
DSP3_VartibleCore_1.0V
PWM PWM
DSP4
PMbus_Cntrl
PMbus_Alert
PMbus_CLK
PWM PWM
GPIO_power_good
1.8V/0.416A
1.5V/1.3A
0.75V
PMbus_DATA
Adjus table Core
(0.9V – 1.1V) 10A
1.0V/8A
1.8V/0.416A
1.0V/8A
0.75V
1.5V/1.3A
UCD74110
VID
DDR4 DDR4
DDR4
DVDD1P8
VCC1P0
DVDD1P8
VCC1P0
VCC0P75 VCC0P75
VCC1P5
VCC1P0
VCC0P75
VCC1P5
DVDD1P8
VCC1P0
VCC1P5
VCC0P75
VCC1P5
DVDD1P8

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Figure : Power Distribution Block Diagram
Max. Delivery Current : 45A
VT239
1.0V@20A
EN_VCC1P0_1
0.75V@1A
VCC0P75
RT9173D
Max. Delivery Current : 3A
Max. Delivery Current : 45A
VT239
EN
EN_VCC1P0_2
1.0V@20A
3VSB@From PCIE
PG
PG
PG
PG
PG
PG
PG_VCC2P5
PG_VCC1P8_FPGA
PG_VCC1P0_1
PG_VCC1P0_2
PG_VCC0P09
PG_VCC1P2
VCC0P9
VCC1P0_2
VCC1P0_1
VCC1P8_FPGA
VCC2P5
VCC1P2
VCC1P5
VCC0P75
VCC5
5V@1A
EN_VCC5 EN PG
Max. Delivery Current : 3A
MP28253EL
PG_VCC5
VCC3
MOSFET
PG PG_VCC3
VCC12 EN
PG_VCC1P2SB
PG
VCC1P2SB
Max. Delivery Current : 1A
EN
APL5912KAC
1.2VSB@0.2A
PG PG_DVDD1P8
EN_DVDD1P8
MP28253EL
1.8V@2A
DVDD1P8
EN
Max. Delivery Current : 3A
APL5912KAC
3VSB
3VSB
Max. Delivery Current : 34A
EN_VCC0P9
0.9V@15A
VT237
EN
MP28253EL
EN
EN_VCC1V2
1.2V@1.1A
MP28253EL
2.5V@1A
Max. Delivery Current : 3A
EN
EN_VCC2P5 Max. Delivery Current : 3A
3V@1.5A
Max. Delivery Current : 45A
VT239
1.8V@1A
EN
Max. Delivery Current : 1A
1.5V@22A
EN
0.75V@1A
RT9173D
Max. Delivery Current : 3A
EN_VCC1P5
EN

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2.3 Pow r Budg t
The estimated operational power budget of DSPC-8682 is about 1 2.06W. This value is estimated
based on the assumption of the power dissipations and utilizations of the key components. For
detailed number, it is summarized in the following table (Table1.DSPC-8682 Power Budget).
 VCC12 load= 12.3 A.
 VCC3.3 load=1.3 1 A
 Total power consumption (for EE Design) ~ 1 2.06W.
 Total power consumption (for Thermal Design) ~ 106.639W.
 Power budget table please refer to below.
Table 1: DSPC-8682 Power Budget

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2.4 Pow r S qu nc
DSPC-8682 consists of many devices on it, including DSP, PCIe switch, SRIO switch, PHY & FPGA etc.
Hence, the power sequence is designed to meet all devices’ power-on requirements. And the timing
parameters are shown in below table (Table 2.System Power Sequence Parameter) while the power
sequence is shown in below figure.( Figure 6.DSPC-8682 overall power sequence).
Figure 6: DSPC-8682 overall power sequence
t<1ms
Host re se t fr om PC
DVDD1P2_EN
5ms < t <200ms
VCC1P2
IDT1616
5ms < t <200ms
IDT1616
VCC0P9
EN_VCC0P9
CPS1432_SRIO_RST#
PEX8748 BCM5482S
PEX8748
t<1ms
PEX8748_PCIE_RST#
POWER_GOOD
Delay 100ms
3.3V standby
pow er
3VSB
FPGA
VCC1P5
EN_VCC1P5
VCC0P75
VCC2P5
EN_VCC2P5
5ms < t <200ms
5ms < t <200ms
5ms < t <200ms
CVDD_DSP
UCD9244_EN
VCC1P0_1
EN_VCC1P0_1
DVDD1P8
EN_DVDD1P8
1V2SB
1.2VSB
TMS320C6678
TMS320C6678
TMS320C6678
VCC3
EN_VCC3
BCM5482S
BCM5482S
IDT1616
T>1m s
POR#
CLOCK_PLL_LOCK
RESETSTAT#
T>1m s
REFCLKP&N
DDRCLKP&N
RESET#
RESETFULL#
T>1ms
PCIE_GF_RST#
5482S_PHY_RST#
t<1ms
VCC3_1616
EN_VCC3_1616
EN_VCC1P0_2
VCC1P0_2
VCC3_PCIE_CLK
EN_VCC3_PCIE_CLK
VCC1V8_FPGA
FPGA
FPGA
TMS320C6678
VCC12
5VSB

Page 16 of 47
Sym Parameter Timing Note
T0
VCC1P0_EN is ramped up after
UCD9244_EN
.
ms<t<200
ms
T1 VCC1P8_EN is ramped up after VCC1P0_EN. ms<t<200ms
T2
VCC1P V_EN is ramped up after VCC1P8_EN
.
ms<t<200ms
T3
POWER_GOOD is asserted after the last power rail(VCC
1P V)
t>100ms
Table 2: System Power Sequence Parameter
For the power sequence on each main component are designed based on the specifications of each
chipset and shown in below figure (Figure7.Power distribution on DSPC-8682 PCIe card).
Figure 7: Power Distribution on DSPC-8682 PCI-E Card
3.3V/0.021A
1.2V/0.069A
FPGA
XC3S200AN
1.8V/0.021A
1V/0.84A
(VDDS,Analog pow er for SerDes and Rx)
3.3V/0.015A (VCC3_1616)
1.2V/0.46A
(VDDT,Analog pow er for TX pairs)
CPS1616
PEX8748
1.8V/0.98A
0.9V/14.03A
1.2V/0.29A
BCM5482S
1.8V/0.189A
VDD3->VDDS->VDDT
2.5V/0.082A
DVDD1P8
(VCCINT, VCCAUX, and VCCO supplies to the FPGA can
be applied in any order)
(The rising time of VCCINT,VCCAUX,and VCCO is 0.2ms to
100ms)
When power on
TMS320C6678
(DSP 0~7)
CVDD
1.8V
1.0V(core)
1.0V Fix
VCC1P0
1.5V / 0.75V
1.8V2.5VBCM5482S
There is no specific power-up nor power-down
sequence
1.2V
VCC1P5
5ms < t <200ms

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2.5 Platform Clock
The DSPC-8682 clocks are generated by the clock synthesizers, crystals and oscillators. Introductions
for each clock are described as below.
CDCE62005 : It’s a Low-Jitter clock generator with 2 .0MHz crystal. It’s programmed to provide
166.66MHZ, 2 0MHZ and 100MHz with LVDS level for the DSP reference clocks.
ICS853S12I : It’s a PCI-E GEN3 clock buffer and provides nine reference clocks to the PCI-E switch and
support PCI-E clock for DSP.
IDT_83PN156DKI: It’s a programmable LVPECL oscillator generator with 2 .0MHz crystal. It offer
1 6.2 MHz by LVPECL level and transfer to CML level for SRIO switch by divider resistor.
CDCLVD110A : It’s a 1:10 LVDS clock buffer. There are four clock buffers which fan out 166.66MHZ,
2 0MHZ and 100MHz to each DSP for the reference clocks of core, DDR3, HyperLink and SRIO/SGMII
interfaces.

Page 18 of 47
The platform clock distribution scheme is illustrated as the below Figure (Figure8.DSPC-8682 Carrier
Clock Feeding Diagram).
Signal Frequency Source Device
DSP0_DDR_CLKP
DSP0_DDR_CLKN
166.67MHz TI_CDCLVD110ARHBR
U1
9
DSP0
DSP1_DDR_CLKP
DSP1_DDR_CLKN 166.67MHz TI_CDCLVD110ARHBR U19
DSP1
DSP2_DDR_CLKP
DSP2_DDR_CLKN
166.67MHz TI_CDCLVD110ARHBR
U1
9
DSP2
DSP3_DDR_CLKP
DSP3_DDR_CLKN
166.67MHz TI_CDCLVD110ARHBR
U1
9
DSP3
DSP4_DDR_CLKP
DSP4_DDR_CLKN 166.67MHz TI_CDCLVD110ARHBR U19
DSP4
DSP _DDR_CLKP
DSP
_DDR_CLKN
166.67MHz TI_CDCLVD110ARHBR
U1
9
DSP5
DSP6_DDR_CLKP
DSP6_DDR_CLKN 166.67MHz TI_CDCLVD110ARHBR U19
DSP6
DSP7_DDR_CLKP
DSP
7
_DDR_CLKN
166.67MHz TI_CDCLVD110ARHBR
U1
9
DSP7
DSP0_CORE_CLKP
DSP0_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP0
DSP1_CORE_CLKP
DSP1_CORE_CLKN 100.00MHz TI_CDCLVD110ARHBR U23
DSP1
DSP2_CORE_CLKP
DSP2_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP2
DSP3_CORE_CLKP
DSP3_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP3
DSP4_CORE_CLKP
DSP
4
_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP4
DSP _CORE_CLKP
DSP
_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP5
DSP6_CORE_CLKP
DSP6_CORE_CLKN 100.00MHz TI_CDCLVD110ARHBR U23
DSP6
DSP7_CORE_CLKP
DSP
7
_CORE_CLKN
100.00MHz TI_CDCLVD110ARHBR
U
2
3
DSP7
DSP0_SRIOSGMII_CLKP
DSP0_SRIOSGMII_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP0
DSP1_SRIOSGMII_CLKP
DSP1_SRIOSGMII_CLKN 2 0.00MHz TI_CDCLVD110ARHBR U28
DSP1
DSP2_SRIOSGMII_CLKP
DSP2_SRIOSGMII_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP2

Page 19 of 47
Signal Frequency Source Device
DSP3_SRIOSGMII_CLKP
DSP3_SRIOSGMII_
CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP3
DSP4_SRIOSGMII_CLKP
DSP
4
_SRIOSGMII_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP4
DSP _SRIOSGMII_CLKP
DSP
_SRIOSGMII_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP5
DSP6_SRIOSGMII_CLKP
DSP
6
_SRIOSGMII_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
28
DSP6
DSP7_SRIOSGMII_CLKP
DSP7_SRIOSGMII_CLKN 2 0.00MHz TI_CDCLVD110ARHBR U28 DSP7
DSP0_MCM_CLKP
DSP0_MCM_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
33
DSP0
DSP1_MCM_CLKP
DSP1_MCM_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
33
DSP1
DSP2_MCM_CLKP
DSP2_MCM_CLKN 2 0.00MHz TI_CDCLVD110ARHBR U33
DSP2
DSP3_MCM_CLKP
DSP3_MCM_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
33
DSP3
DSP4_MCM_CLKP
DSP4_MCM_CLKN 2 0.00MHz TI_CDCLVD110ARHBR U33
DSP4
DSP _MCM_CLKP
DSP
_MCM_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
33
DSP5
DSP6_MCM_CLKP
DSP
6
_MCM_CLKN
2 0.00MHz TI_CDCLVD110ARHBR
U
33
DSP6
DSP7_MCM_CLKP
DSP7_MCM_CLKN 2 0.00MHz TI_CDCLVD110ARHBR U33 DSP7
ICS 83_PCIE_REF_CLKP0
ICS 83
_PCIE_REF_CLKN
0
100.00MHz IDT_ICS8 3S12AKI
U3
4
DSP0
ICS 83_PCIE_REF_CLKP1
ICS 83_PCIE_REF_CLKN1
100.00MHz IDT _ICS8 3S12AKI
U3
4
DSP1
ICS 83_PCIE_REF_CLKP2
ICS 83_PCIE_REF_CLKN2 100.00MHz IDT _ICS8 3S12AKI U34
DSP2
ICS 83_PCIE_REF_CLKP3
ICS 83_PCIE_REF_CLKN
3
100.00MHz IDT_ ICS8 3S12AKI
U3
4
DSP3
ICS 83_PCIE_REF_CLKP4
ICS 83_PCIE_REF_CLKN4 100.00MHz IDT_ ICS8 3S12AKI U34
DSP4
ICS 83_PCIE_REF_CLKP
ICS 83_PCIE_REF_CLKN
100.00MHz IDT_ICS8 3S12AKI
U3
4
DSP5
ICS 83_PCIE_REF_CLKP6
ICS 83
_PCIE_REF_CLKN
6
100.00MHz IDT_ ICS8 3S12AKI
U3
4
DSP6

Page 20 of 47
Signal Frequency Source Device
ICS 83_PCIE_REF_CLKP7
ICS 83_PCIE_REF_CLKN
7
100.00MHz IDT_ ICS8 3S12AKI
U3
4
DSP7
ICS 83_PCIE_REF_CLKP8
ICS 83
_PCIE_REF_CLKN
8
100.00MHz IDT_ ICS8 3S12AKI
U3
4
PEX8748
U40
482S_XTALO
482S_XTALI
2 .00MHz Crystal BCM 482SHA1KFBG
U
20
MAIN_48MHZ_CLK_R 48.00MHz Oscillator XILINX XC3S200AN
FPGA1
PCIE_REF_CLK_P
PCIE_REF_CLK_N 100MHz PCI-E Gold Finger GF1
IDT_ICS8 3S12AKI
U34
83PN1 6_XTAL_OUT
83PN1 6_XTAL_IN
2 .00MHz Crystal ICS83PN1 6I
U
9
83PN1 6_SRIO_QN
83PN1 6_SRIO_QP
1 6.2 MHz Oscillator 80HCPS1616RMI
U10
Table 3: Clock Domains
250Mhz Diff
62005_CLK_SSP_CS0
62005_CLK_SSP_CLK
62005_CLK_SSP_MOSI
62005_CLK_SSP_MISO
Control
X'TAL
25Mhz
100Mhz Diff
SRIO_SGMI_CLKP/N
TMS320C6678
DSP 0 ~ 7
MCM_CLKP/N
CORE_CLKP/N
DSPn_SRIOSGM II_CLKP/N
250M hz Diff
250M hz Diff
100Mhz Diff
166.67Mhz Diff
Clock Diagram
250Mhz Diff
U0
CDCE62005
U4
U3
U2
U1
EN3
TI
CDCLVD110A
1:10 LVDS
Clock Buffer
n 0~7
EN4
DSPn_CORE_CLKP/N
Control
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
n 0~7
Control
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
EN2
Control
n 0~7
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
EN0
DSPn_MCM_CLKP/N
Control
n 0~7
DDR_CLKP/N
166.67Mhz Diff
DSPn_DDR_CLKP/N