Alinx ACU2CG User manual

ZYNQ UltraScale+ MPSoC
FPGA SOM Core Board
ACU2CG
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2022-09-08

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Table of Contents
Version Record .............................................................................................2
Part 1: ACU2CG core board ........................................................................ 4
Part 1.1: ACU2CG core board Introduction ......................................... 4
Part 1.2: ZYNQ Chip .............................................................................5
Part 1.3: DDR4 DRAM ..........................................................................7
Part 1.4: QSPI Flash ...........................................................................12
Part 1.5: eMMC Flash .........................................................................13
Part 1.6: Clock configuration .............................................................. 15
Part 1.7: LED ...................................................................................... 17
Part 1.8: Power Supply .......................................................................18
Part 1.9: ACU2CG Core Board Form Factor ..................................... 19
Part 1.10: Board to Board Connectors pin assignment .....................19

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Part 1: ACU2CG core board
Part 1.1: ACU2CG core board Introduction
ACU2CG (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU2CG-1SFVC784E of XILINX company Zynq UltraScale+
MPSoCs CG series.
This core board uses 4 Micron DDR4 chips MT40A512M16GE on the PS
side, to form a 64-bit data bus bandwidth and 2GB capacity. The highest
operating speed of DDR4 SDRAM on the PS side can reach 1200MHz (data
rate 2400Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC
FLASH chip are also integrated on the core board to start storage configuration
and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO
ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the
XCZU2CG chip and the interface has been processed with equal length and
differential, and the core board size is only 3.15*2.36 (inch), which is very
suitable for secondary development.

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Figure 2-1-1: ACU2CG Core Board (Front View)
Part 1.2: ZYNQ Chip
The FPGA core board ACU2CG uses Xilinx's Zynq UltraScale+ MPSoCs
CG series chip, module XCZU2CG-1SFVC784E. The PS system of the
ZU2CG chip integrates 2 ARM Cortex™-A53 processors with a speed of up to
1.2Ghz and supports Level 2 Cache; it also contains 2 Cortex-R5 processors
with a speed of up to 500Mhz
The ZU2CG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU2CG Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.2GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface

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Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Supports the division of four parts of power
supply Full/Low/PL/Battery.
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 103K
Flip-flops: 94K
Look-up-tables (LUTs): 47K
 Block RAM : 5.3MB
Clock Management Units (CMTs): 3
18x25MACCs: 240
XCZU2CG-1SFVC784E chip speed grade is -1, industrial grade, package
is SFVC784
Part 1.3: DDR4 DRAM
The ACU2CG core board is equipped with 4 Micron (Micron) 512MB
DDR4 chips, model is PANGO CXDQ2BFAM-CG (Compatible with
MT40A256M16GE-083E), to form a 64-bit data bus bandwidth and 2GB
capacity. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems

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are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1066MHz (data rate 2133Mbps), and four DDR4 storage systems are directly
connected to the memory interface of PS's BANK504. The specific
configuration of DDR4 SDRAM is shown in Table 2-3-1 below:
Bit Number
Chip Model
Capacity
Factory
U12,U14,U15,U16
CXDQ2BFAM-CG
256M x 16bit
PANGO
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR4 DRAM schematic diagram on the PS Side

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PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AF21
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AG21
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AF23
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AG23
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AF25
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AF26
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AE27
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AF27
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
N23
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
M23
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
L23
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
K23
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
N26
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
N27
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
J26
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
J27
PS_DDR4_DQ0
PS_DDR_DQ0_504
AD21
PS_DDR4_DQ1
PS_DDR_DQ1_504
AE20
PS_DDR4_DQ2
PS_DDR_DQ2_504
AD20
PS_DDR4_DQ3
PS_DDR_DQ3_504
AF20
PS_DDR4_DQ4
PS_DDR_DQ4_504
AH21
PS_DDR4_DQ5
PS_DDR_DQ5_504
AH20
PS_DDR4_DQ6
PS_DDR_DQ6_504
AH19
PS_DDR4_DQ7
PS_DDR_DQ7_504
AG19
PS_DDR4_DQ8
PS_DDR_DQ8_504
AF22
PS_DDR4_DQ9
PS_DDR_DQ9_504
AH22
PS_DDR4_DQ10
PS_DDR_DQ10_504
AE22
PS_DDR4_DQ11
PS_DDR_DQ11_504
AD22
PS_DDR4_DQ12
PS_DDR_DQ12_504
AH23
PS_DDR4_DQ13
PS_DDR_DQ13_504
AH24
PS_DDR4_DQ14
PS_DDR_DQ14_504
AE24
PS_DDR4_DQ15
PS_DDR_DQ15_504
AG24

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PS_DDR4_DQ16
PS_DDR_DQ16_504
AC26
PS_DDR4_DQ17
PS_DDR_DQ17_504
AD26
PS_DDR4_DQ18
PS_DDR_DQ18_504
AD25
PS_DDR4_DQ19
PS_DDR_DQ19_504
AD24
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG26
PS_DDR4_DQ21
PS_DDR_DQ21_504
AH25
PS_DDR4_DQ22
PS_DDR_DQ22_504
AH26
PS_DDR4_DQ23
PS_DDR_DQ23_504
AG25
PS_DDR4_DQ24
PS_DDR_DQ24_504
AH27
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH28
PS_DDR4_DQ26
PS_DDR_DQ26_504
AF28
PS_DDR4_DQ27
PS_DDR_DQ27_504
AG28
PS_DDR4_DQ28
PS_DDR_DQ28_504
AC27
PS_DDR4_DQ29
PS_DDR_DQ29_504
AD27
PS_DDR4_DQ30
PS_DDR_DQ30_504
AD28
PS_DDR4_DQ31
PS_DDR_DQ31_504
AC28
PS_DDR4_DQ32
PS_DDR_DQ32_504
T22
PS_DDR4_DQ33
PS_DDR_DQ33_504
R22
PS_DDR4_DQ34
PS_DDR_DQ34_504
P22
PS_DDR4_DQ35
PS_DDR_DQ35_504
N22
PS_DDR4_DQ36
PS_DDR_DQ36_504
T23
PS_DDR4_DQ37
PS_DDR_DQ37_504
P24
PS_DDR4_DQ38
PS_DDR_DQ38_504
R24
PS_DDR4_DQ39
PS_DDR_DQ39_504
N24
PS_DDR4_DQ40
PS_DDR_DQ40_504
H24
PS_DDR4_DQ41
PS_DDR_DQ41_504
J24
PS_DDR4_DQ42
PS_DDR_DQ42_504
M24
PS_DDR4_DQ43
PS_DDR_DQ43_504
K24
PS_DDR4_DQ44
PS_DDR_DQ44_504
J22
PS_DDR4_DQ45
PS_DDR_DQ45_504
H22
PS_DDR4_DQ46
PS_DDR_DQ46_504
K22
PS_DDR4_DQ47
PS_DDR_DQ47_504
L22
PS_DDR4_DQ48
PS_DDR_DQ48_504
M25
PS_DDR4_DQ49
PS_DDR_DQ49_504
M26
PS_DDR4_DQ50
PS_DDR_DQ50_504
L25

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PS_DDR4_DQ51
PS_DDR_DQ51_504
L26
PS_DDR4_DQ52
PS_DDR_DQ52_504
K28
PS_DDR4_DQ53
PS_DDR_DQ53_504
L28
PS_DDR4_DQ54
PS_DDR_DQ54_504
M28
PS_DDR4_DQ55
PS_DDR_DQ55_504
N28
PS_DDR4_DQ56
PS_DDR_DQ56_504
J28
PS_DDR4_DQ57
PS_DDR_DQ57_504
K27
PS_DDR4_DQ58
PS_DDR_DQ58_504
H28
PS_DDR4_DQ59
PS_DDR_DQ59_504
H27
PS_DDR4_DQ60
PS_DDR_DQ60_504
G26
PS_DDR4_DQ61
PS_DDR_DQ61_504
G25
PS_DDR4_DQ62
PS_DDR_DQ62_504
K25
PS_DDR4_DQ63
PS_DDR_DQ63_504
J25
PS_DDR4_DM0
PS_DDR_DM0_504
AG20
PS_DDR4_DM1
PS_DDR_DM1_504
AE23
PS_DDR4_DM2
PS_DDR_DM2_504
AE25
PS_DDR4_DM3
PS_DDR_DM3_504
AE28
PS_DDR4_DM4
PS_DDR_DM4_504
R23
PS_DDR4_DM5
PS_DDR_DM5_504
H23
PS_DDR4_DM6
PS_DDR_DM6_504
L27
PS_DDR4_DM7
PS_DDR_DM7_504
H26
PS_DDR4_A0
PS_DDR_A0_504
W28
PS_DDR4_A1
PS_DDR_A1_504
Y28
PS_DDR4_A2
PS_DDR_A2_504
AB28
PS_DDR4_A3
PS_DDR_A3_504
AA28
PS_DDR4_A4
PS_DDR_A4_504
Y27
PS_DDR4_A5
PS_DDR_A5_504
AA27
PS_DDR4_A6
PS_DDR_A6_504
Y22
PS_DDR4_A7
PS_DDR_A7_504
AA23
PS_DDR4_A8
PS_DDR_A8_504
AA22
PS_DDR4_A9
PS_DDR_A9_504
AB23
PS_DDR4_A10
PS_DDR_A10_504
AA25
PS_DDR4_A11
PS_DDR_A11_504
AA26
PS_DDR4_A12
PS_DDR_A12_504
AB25
PS_DDR4_A13
PS_DDR_A13_504
AB26

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PS_DDR4_WE_B
PS_DDR_A14_504
AB24
PS_DDR4_CAS_B
PS_DDR_A15_504
AC24
PS_DDR4_RAS_B
PS_DDR_A16_504
AC23
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
Y23
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
U25
PS_DDR4_BA0
PS_DDR_BA0_504
V23
PS_DDR4_BA1
PS_DDR_BA1_504
W22
PS_DDR4_BG0
PS_DDR_BG0_504
W24
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
W27
PS_DDR4_ODT0
PS_DDR_ODT0_504
U28
PS_DDR4_PARITY
PS_DDR_PARITY_504
V24
PS_DDR4_RESET_B
PS_DDR_RST_N_504
U23
PS_DDR4_CLK0_P
PS_DDR_CK0_P_504
W25
PS_DDR4_CLK0_N
PS_DDR_CK0_N_504
W26
PS_DDR4_CKE0
PS_DDR_CKE0_504
V28
Part 1.4: QSPI Flash
The FPGA core board ACU2CG is equipped with one 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U5
MT25QU256ABA1EW9
256Mbit
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure

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2-4-1 shows the QSPI Flash in the schematic.
Figure 2-4-1: QSPI Flash in the schematic
Configure chip pin assignments:
Signal Name
Pin Name
Pin Number
MIO0_QSPI0_SCLK
PS_MIO0_500
AG15
MIO1_QSPI0_IO1
PS_MIO1_500
AG16
MIO2_QSPI0_IO2
PS_MIO2_500
AF15
MIO3_QSPI0_IO3
PS_MIO3_500
AH15
MIO4_QSPI0_IO0
PS_MIO4_500
AH16
MIO5_QSPI0_SS_B
PS_MIO5_500
AD16
Part 1.5: eMMC Flash
The ACU2CG core board is equipped with a large-capacity 8GB eMMC
FLASH chip, the model is FEMDRM008G-58A39 (Compatible with
MTFC8GAKAJCN-4M ), it supports the HS-MMC interface of the JEDEC
e-MMC V5.0 standard, and the level supports 1.8V or 3.3V. The data width of
eMMC FLASH and ZYNQ connection is 8bit. Due to the large-capacity and
non-volatile characteristics of eMMC FLASH, it can be used as a large-capacity
storage device in the ZYNQ system, such as storing ARM applications, system
files and other user data files The specific models and related parameters of
eMMC FLASH are shown in Table 2-5-1.

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Position
Model
Capacity
Factory
U19
FEMDRM008G-58A39
8G Byte
FORESEE
Table 2-5-1: eMMC FLASH Specification
The eMMC FLASH is connected to the GPIO port of the BANK500 of the
PS part of the ZYNQ UltraScale+. In the system design, it is necessary to
configure the GPIO port function of the PS side as an EMMC interface. Figure
2-5-1 shows the part of eMMC Flash in the schematic diagram.
Figure 2-5-1: QSPI Flash in the schematic
Configuration Chip pin assignment:
Signal Name
Pin Name
Pin Number
MMC_DAT0
PS_MIO13_500
AH18
MMC_DAT1
PS_MIO14_500
AG18
MMC_DAT2
PS_MIO15_500
AE18
MMC_DAT3
PS_MIO16_500
AF18
MMC_DAT4
PS_MIO17_500
AC18
MMC_DAT5
PS_MIO18_500
AC19
MMC_DAT6
PS_MIO19_500
AE19
MMC_DAT7
PS_MIO20_500
AD19
MMC_CMD
PS_MIO21_500
AC21

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MMC_CCLK
PS_MIO22_500
AB20
MMC_RSTN
PS_MIO23_500
AB18
Part 1.6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:
Figure 2-6-1: Core Board Clock Source
PS System RTC Real Time Clock
The passive crystal Y2 on the core board provides a 32.768KHz real-time
clock source for the PS system. The crystal is connected to the PS_PADI_503
and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic
diagram is shown in Figure 2-6-2:
Figure 2-6-2: Passive Crystal Oscillator for RTC

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Clock pin assignment:
Signal Name
Pin
PS_PADI_503
N17
PS_PADO_503
N18
PS System Clock Source
The X1 crystal on the core board provides a 33.333MHz clock input for the
PS part. The clock input is connected to the PS_REF_CLK_503 pin of
BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-3:
Figure 2-6-3: Active Crystal in PS part
Clock pin assignment:
Signal Name
Pin
PS_CLK
R16
PL System Clock Source
The core board provides a differential 200MHz PL system clock source for
the reference clock of the DDR4 controller. The crystal oscillator output is
connected to the global clock (MRCC) of PL BANK64. This global clock can be
used to drive the DDR4 controller and user logic circuits in the FPGA. The
schematic diagram of this clock source is shown in Figure 2-6-4

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Figure 2-6-4: PL system clock source
Clock pin assignment:
Signal Name
Pin
PL_CLK0_P
AE5
PL_CLK0_N
AF5
Part 1.7: LED
There is a red power indicator (PWR) and a configuration LED (DONE) on
the ACU2CG core board. When the core board is powered on, the power
indicator will light up; after the FPGA configuration program, the configuration
LED light will light up. The LED Schematic in the Core Board is shown in Figure
2-7-1:
Figure 2-7-1: LED Schematic in the Core Board

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Part 1.8: Power Supply
The power supply voltage of the ACU2CG core board is DC12V, which is
supplied by connecting the carrier board. The core board uses a PMIC chip
TPS6508641 to generate all the power required by the XCZU2CG chip. For the
TPS6508641 power supply design, please refer to the power supply chip
manual. The design block diagram is as follows:

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In addition, the VCCIO power supply of BANK65 and BANK66 of
XCZU2CG chip is provided by the carrier board, which is convenient for users
to modify, but the maximum power supply cannot exceed 1.8V.
Part 1.9: ACU2CG Core Board Form Factor
Figure 2-9-1: ACU2CG Core Board Form Factor
Part 1.10: Board to Board Connectors pin assignment
The core board has a total of four high-speed expansion ports. It uses four
120-pin inter-board connectors (J29/J30/J31/J32) to connect to the carrier
board.
The connectors used is Panasonic AXK5A2137YG, and the corresponding
connector model in the carrier board is Panasonic AXK6A2337YG. Among

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them, J29 is connected to the IO of BANK65 and BANK66, J30 is connected to
the IO of BANK25, BANK26, BANK66 and the transceiver signal of BANK505
MGT, J31 is connected to the IO of BANK24 and BANK44, J32 is connected to
the MIO, VCCO_65, VCCO_66 and +12V power supply of PS.
Among them, the IO level standard of BANK43~46 is 3.3V, and the
level standard of BANK65 and BANK66 is determined by the VCCO_65
and VCCO_66 power supply of the carrier board, but cannot exceed +1.8V;
the level standard of MIO is also 1.8V.
Pin assignment of board to board connector J29
J29 Pin
Signal Name
Pin Number
J29 Pin
Signal Name
Pin Number
1
B65_L2_N
V9
2
B65_L22_P
K8
3
B65_L2_P
U9
4
B65_L22_N
K7
5
GND
-
6
GND
-
7
B65_L4_N
T8
8
B65_L20_P
J6
9
B65_L4_P
R8
10
B65_L20_N
H6
11
GND
-
12
GND
-
13
B65_L1_N
Y8
14
B65_L6_N
T6
15
B65_L1_P
W8
16
B65_L6_P
R6
17
GND
-
18
GND
-
19
B65_L7_P
L1
20
B65_L17_P
N9
21
B65_L7_N
K1
22
B65_L17_N
N8
23
GND
-
24
GND
-
25
B65_L15_P
N7
26
B65_L9_P
K2
27
B65_L15_N
N6
28
B65_L9_N
J2
29
GND
-
30
GND
-
31
B65_L16_P
P7
32
B65_L3_N
V8
33
B65_L16_N
P6
34
B65_L3_P
U8
35
GND
-
36
GND
-
37
B65_L14_P
M6
38
B65_L19_P
J5