Alinx ZYNQUltraScale+ AXU5EVB-E User manual

ZYNQ UltraScale+ MPSoC
FPGA Development Board
AXU5EVB-E
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2021-06-17
Rachel Zhou
First Release

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Table of Contents
Version Record .............................................................................................2
Part 1: FPGA Development Board Introduction .......................................... 6
Part 2: ACU5EV core board .......................................................................10
Part 2.1: ACU5EV core board Introduction ........................................ 10
Part 2.2: ZYNQ Chip ...........................................................................11
Part 2.3: DDR4 DRAM ........................................................................13
Part 2.4: QSPI Flash ...........................................................................20
Part 2.5: eMMC Flash .........................................................................21
Part 2.6: Clock configuration .............................................................. 23
Part 2.7: LED ...................................................................................... 25
Part 2.8: Power Supply .......................................................................26
Part 2.9: ACU5EV Core Board Size Dimension ................................ 27
Part 2.10: Board to Board Connectors pin assignment .....................27
Part 3: Carrier Board ..................................................................................36
Part 3.1: Carrier Board Introduction ................................................... 36
Part 3.2: M.2 Interface ........................................................................37
Part 3.3: DP Interface ......................................................................... 38
Part 3.4: USB3.0 interface ..................................................................40
Part 3.5: Gigabit Ethernet Interface ................................................... 41
Part 3.6: USB to Serial Port ................................................................43
Part 3.7: SD Card Slot Interface .........................................................44
Part 3.8: Expansion Header ............................................................... 45
Part 3.9: CAN communication interface .............................................47
Part 3.10: 485 communication interface ............................................ 48
Part 3.11: MIPI camera interface ........................................................49
Part 3.12: JTAG Debug Port ...............................................................51
Part 3.13: Real-time clock .................................................................. 51

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Part 3.14: EEPROM and Temperature sensor ...................................52
Part 3.15: User LEDs ..........................................................................53
Part 3.16: Keys ................................................................................... 54
Part 3.17: DIP Switch Configuration ...................................................55
Part 3.18: Power Supply .....................................................................56
Part 3.19: ALINX Customized Fan ..................................................... 57
Part 3.20: Carrier Board Size Dimension ...........................................58

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This MPSoCs FPGA development platform adopts the core board + carrier
board mode, which is convenient for users to use the core board for secondary
development. The core board uses XILINX Zynq UltraScale+ EV chip ZU5EV
solution, uses Processing System(PS)+Programmable Logic(PL) technology to
integrate dual-core ARM ARM Cortex-A53 and FPGA programmable logic on a
single chip. In addition, the PS side of the core board has 4 pieces of 1GB
high-speed DDR4 SDRAM chips, 1 piece of 8GB eMMC memory chip and 1
piece of 256Mb QSPI FLASH chip; the PL side of the core board has 1 piece of
1GB DDR4 SDRAM chip
In the design of carrier board, we have extended a wealth of interfaces for
users, such as 1 SATA M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2
Gigabit Ethernet interfaces, 1 SD card slot,2-Channel 40-pin expansion header,
2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI
Camera Interface. It meets users' requirements for high-speed data exchange,
data storage, Video transmission processing, deep learning, artificial
intelligence and industrial control. It is a "professional" ZYNQ development
platform. For high-speed data transmission and exchange, pre-verification and
post-application of data processing is possible. This product is very suitable for
students, engineers and other groups engaged in MPSoCs development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AXU5EVB-E FPGA development board is
inherited from our consistent core board + carrier board model. A high-speed
inter-board connector is used between the core board and the carrier board.
The core board is mainly composed of the smallest system of ACU5EV +
5 DDR4 + eMMC + QSPI FLASH, ACU5EV uses Xilinx's Zynq UltraScale+
MPSoCs EV chip, the model number is XCZU5EV-2SFVC784I. ZU5EV chip
can be divided into processor system part Processor System (PS) and
programmable logic part Programmable Logic (PL). On the PS side and PL
side of the ZU5EV chip, there are 4 DDR4 and 1 DDR4 respectively, each with
a capacity of up to 1GB, which enables the ARM system and FPGA system to
independently process and store data. The 8GB eMMC FLASH memory chip
and a 256Mb QSPI FLASH which are on the PS side, used to statically store
the operating system, file system and user data of MPSoCs.
The AXU5EVB-E carrier board expands its rich peripheral interface,
including 1 M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2 Gigabit
Ethernet interfaces, 1 SD card slot, 2-Channel 40-pin expansion header,
2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI
Camera Interface and some keys and LEDs.
The following figure shows the structure of the entire development system:

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Figure 1-1-1: The Schematic Diagram of the AXU5EVB-E
Through this diagram, you can see the interfaces and functions that the
AXU5EVB-E FPGA Development Board contains:
ACU5EV core board
It consists of ZU5EV +4GB DDR4（PS）+1GB DDR4（PL）+8GB eMMC
FLASH + 256Mb QSPI FLASH, and there are 2 crystal oscillators to
provide the clock, a single-ended 33.3333MHz crystal oscillator for the
PS system, and a differential 200MHz crystal oscillator for the PL logic
DDR reference clock.
M.2 Interface
1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state
drives, with a communication speed of up to 6Gbps.
DP Output Interface
1 standard Display Port output display interface, used for video image
display. Supports up to 4K@30Hz or 1080P@60Hz output

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USB 3.0 Interface
4-channel USB3.0 HOST interface, USB interface type is TYPE A. Used
to connect external USB peripherals, such as connecting a mouse,
keyboard, U disk, etc.
Gigabit Ethernet Interface
2-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses JLSemi JL2121-N040I industrial grade GPHY chip.
USB Uart Interface
2-Channel Uart to USB interfaces for communication with the computer,
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
SD Card Slot Interface
1 Micro SD card holder, used to store operating system image and file
system.
40-pin expansion port
2 40-pin 0.1-inch pitch expansion port can be connected to various
ALINX modules (binocular camera, TFT LCD screen, high-speed AD
module, etc.). The expansion port contains 1-channel 5V power supply,
2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
CAN Communication Interface
Two-way CAN bus interface, using TI's SN65HVD232 chip, the
interface uses 4Pin green terminal blocks.
485 Communication Interface
Two-way 485 communication interface, using MAX3485 chip of MAXIM
company. The interface uses 6Pin green terminal blocks.
MIPI Interface
MIPI camera input interfaces, used to connect MIPI camera module

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(AN5641).
JTAG debug port
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download the ZU4EV system
through the XILINX downloader.
Temperature and humidity sensor chip LM75
On-board temperature and humidity sensor chip LM75, used to detect
the temperature and humidity of the surrounding environment around
the FPGA development board
EEPROM
One EEPROM 24LC04 with I2C interface
Real Time Clock (RTC)
1 built-in RTC real-time clock
LED Lights
5 LEDs, include 2 LEDs on the core board, 3 LED on the carrier board.
There are 1 power indicator and 1 DONE Configuration indicator on the
core board, 1 power indicator on the carrier board. There are 1 power
indicator and 2 user indicators on the carrier board.
KEYs
3 KEYs, include 1 Rest KEY and 2 User KEYs.

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Part 2: ACU5EV core board
Part 2.1: ACU5EV core board Introduction
ACU5EV (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU5EV-2SFVC784I of XILINX company Zynq UltraScale+
MPSoCs EV Family.
This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit
data bus width and a capacity of 1GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz
(data rate 2132Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC
FLASH chip are also integrated on the core board to start storage configuration
and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO
ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the
XCZU5EV chip and the interface has been processed with equal length and
differential, and the core board size is only 3.15*2.36 (inch), which is very
suitable for secondary development.

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Figure 2-1-1: ACU5EV Core Board (Front View)
Part 2.2: ZYNQ Chip
The FPGA core board ACU5EV uses Xilinx's Zynq UltraScale+ MPSoCs
EV family chip, module XCZU5EV-2SFVC784I. The PS system of the ZU5EV
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.2Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 500Mhz
The ZU5EV chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-2-1 detailed the Overall Block Diagram of the ZU5EV Chip.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU5EV Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.5GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 600MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
Image Video Processor Mali-400 MP2, speed up to 677MHz, 64KB level
2 cache
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,

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Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/ Low/ PL/ Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
System Logic Cells: 256.2K
CLB Flip-flops: 234.24K
Look-up-tables (LUTs): 117.12K
 Block RAM : 5.1 Mb
Clock Management Units (CMTs): 4
 DSP Slices: 1248
Video Codec Unit (VCU): 1
 PCIE3.0: 2
GTH 12.5Gb/s Transceiver: 4
XCZU5EV-2SFVC784I chip speed grade is -2, industrial grade, package is
SFVC784
Part 2.3: DDR4 DRAM
The ACU5EV core board is equipped with 5 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4
chip is mounted on the PL end, which is a 16-bit data bus width and a capacity

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of 1GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1066MHz (data rate 2133Mbps), and a piece of DDR4 is connected to the
BANK64 interface of the FPGA. The specific configuration of DDR4 SDRAM is
shown in Table 2-3-1 below:
Bit Number
Chip Model
Capacity
Factory
U12,U14,U15,U16
MT40A512M16LY-062E
512M x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: PS DDR4 DRAM schematic diagram

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The hardware connection of DDR4 SDRAM on the PL Side is shown in
Figure 2-3-2:
Figure 2-3-2: PL DDR4 DRAM schematic diagram
PS Side DDR4 SDRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AF21
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AG21
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AF23
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AG23
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AF25
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AF26
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AE27
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AF27
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
N23
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
M23
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
L23
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
K23
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
N26
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
N27

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PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
J26
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
J27
PS_DDR4_DQ0
PS_DDR_DQ0_504
AD21
PS_DDR4_DQ1
PS_DDR_DQ1_504
AE20
PS_DDR4_DQ2
PS_DDR_DQ2_504
AD20
PS_DDR4_DQ3
PS_DDR_DQ3_504
AF20
PS_DDR4_DQ4
PS_DDR_DQ4_504
AH21
PS_DDR4_DQ5
PS_DDR_DQ5_504
AH20
PS_DDR4_DQ6
PS_DDR_DQ6_504
AH19
PS_DDR4_DQ7
PS_DDR_DQ7_504
AG19
PS_DDR4_DQ8
PS_DDR_DQ8_504
AF22
PS_DDR4_DQ9
PS_DDR_DQ9_504
AH22
PS_DDR4_DQ10
PS_DDR_DQ10_504
AE22
PS_DDR4_DQ11
PS_DDR_DQ11_504
AD22
PS_DDR4_DQ12
PS_DDR_DQ12_504
AH23
PS_DDR4_DQ13
PS_DDR_DQ13_504
AH24
PS_DDR4_DQ14
PS_DDR_DQ14_504
AE24
PS_DDR4_DQ15
PS_DDR_DQ15_504
AG24
PS_DDR4_DQ16
PS_DDR_DQ16_504
AC26
PS_DDR4_DQ17
PS_DDR_DQ17_504
AD26
PS_DDR4_DQ18
PS_DDR_DQ18_504
AD25
PS_DDR4_DQ19
PS_DDR_DQ19_504
AD24
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG26
PS_DDR4_DQ21
PS_DDR_DQ21_504
AH25
PS_DDR4_DQ22
PS_DDR_DQ22_504
AH26
PS_DDR4_DQ23
PS_DDR_DQ23_504
AG25
PS_DDR4_DQ24
PS_DDR_DQ24_504
AH27
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH28
PS_DDR4_DQ26
PS_DDR_DQ26_504
AF28
PS_DDR4_DQ27
PS_DDR_DQ27_504
AG28
PS_DDR4_DQ28
PS_DDR_DQ28_504
AC27
PS_DDR4_DQ29
PS_DDR_DQ29_504
AD27
PS_DDR4_DQ30
PS_DDR_DQ30_504
AD28
PS_DDR4_DQ31
PS_DDR_DQ31_504
AC28

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PS_DDR4_DQ32
PS_DDR_DQ32_504
T22
PS_DDR4_DQ33
PS_DDR_DQ33_504
R22
PS_DDR4_DQ34
PS_DDR_DQ34_504
P22
PS_DDR4_DQ35
PS_DDR_DQ35_504
N22
PS_DDR4_DQ36
PS_DDR_DQ36_504
T23
PS_DDR4_DQ37
PS_DDR_DQ37_504
P24
PS_DDR4_DQ38
PS_DDR_DQ38_504
R24
PS_DDR4_DQ39
PS_DDR_DQ39_504
N24
PS_DDR4_DQ40
PS_DDR_DQ40_504
H24
PS_DDR4_DQ41
PS_DDR_DQ41_504
J24
PS_DDR4_DQ42
PS_DDR_DQ42_504
M24
PS_DDR4_DQ43
PS_DDR_DQ43_504
K24
PS_DDR4_DQ44
PS_DDR_DQ44_504
J22
PS_DDR4_DQ45
PS_DDR_DQ45_504
H22
PS_DDR4_DQ46
PS_DDR_DQ46_504
K22
PS_DDR4_DQ47
PS_DDR_DQ47_504
L22
PS_DDR4_DQ48
PS_DDR_DQ48_504
M25
PS_DDR4_DQ49
PS_DDR_DQ49_504
M26
PS_DDR4_DQ50
PS_DDR_DQ50_504
L25
PS_DDR4_DQ51
PS_DDR_DQ51_504
L26
PS_DDR4_DQ52
PS_DDR_DQ52_504
K28
PS_DDR4_DQ53
PS_DDR_DQ53_504
L28
PS_DDR4_DQ54
PS_DDR_DQ54_504
M28
PS_DDR4_DQ55
PS_DDR_DQ55_504
N28
PS_DDR4_DQ56
PS_DDR_DQ56_504
J28
PS_DDR4_DQ57
PS_DDR_DQ57_504
K27
PS_DDR4_DQ58
PS_DDR_DQ58_504
H28
PS_DDR4_DQ59
PS_DDR_DQ59_504
H27
PS_DDR4_DQ60
PS_DDR_DQ60_504
G26
PS_DDR4_DQ61
PS_DDR_DQ61_504
G25
PS_DDR4_DQ62
PS_DDR_DQ62_504
K25
PS_DDR4_DQ63
PS_DDR_DQ63_504
J25
PS_DDR4_DM0
PS_DDR_DM0_504
AG20
PS_DDR4_DM1
PS_DDR_DM1_504
AE23

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PS_DDR4_DM2
PS_DDR_DM2_504
AE25
PS_DDR4_DM3
PS_DDR_DM3_504
AE28
PS_DDR4_DM4
PS_DDR_DM4_504
R23
PS_DDR4_DM5
PS_DDR_DM5_504
H23
PS_DDR4_DM6
PS_DDR_DM6_504
L27
PS_DDR4_DM7
PS_DDR_DM7_504
H26
PS_DDR4_A0
PS_DDR_A0_504
W28
PS_DDR4_A1
PS_DDR_A1_504
Y28
PS_DDR4_A2
PS_DDR_A2_504
AB28
PS_DDR4_A3
PS_DDR_A3_504
AA28
PS_DDR4_A4
PS_DDR_A4_504
Y27
PS_DDR4_A5
PS_DDR_A5_504
AA27
PS_DDR4_A6
PS_DDR_A6_504
Y22
PS_DDR4_A7
PS_DDR_A7_504
AA23
PS_DDR4_A8
PS_DDR_A8_504
AA22
PS_DDR4_A9
PS_DDR_A9_504
AB23
PS_DDR4_A10
PS_DDR_A10_504
AA25
PS_DDR4_A11
PS_DDR_A11_504
AA26
PS_DDR4_A12
PS_DDR_A12_504
AB25
PS_DDR4_A13
PS_DDR_A13_504
AB26
PS_DDR4_WE_B
PS_DDR_A14_504
AB24
PS_DDR4_CAS_B
PS_DDR_A15_504
AC24
PS_DDR4_RAS_B
PS_DDR_A16_504
AC23
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
Y23
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
U25
PS_DDR4_BA0
PS_DDR_BA0_504
V23
PS_DDR4_BA1
PS_DDR_BA1_504
W22
PS_DDR4_BG0
PS_DDR_BG0_504
W24
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
W27
PS_DDR4_ODT0
PS_DDR_ODT0_504
U28
PS_DDR4_PARITY
PS_DDR_PARITY_504
V24
PS_DDR4_RESET_B
PS_DDR_RST_N_504
U23
PS_DDR4_CLK0_P
PS_DDR_CK0_P_504
W25
PS_DDR4_CLK0_N
PS_DDR_CK0_N_504
W26

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PS_DDR4_CKE0
PS_DDR_CKE0_504
V28
PL Side DDR4 SDRAM pin assignment:
Signal Name
Pin Name
Pin Number
PL_DDR4_DQS0_P
IO_L22P_T3U_N6_DBC_AD0P_64
AE2
PL_DDR4_DQS0_N
IO_L22N_T3U_N7_DBC_AD0N_64
AF2
PL_DDR4_DQS1_P
IO_L16P_T2U_N6_QBC_AD3P_64
AD2
PL_DDR4_DQS1_N
IO_L16N_T2U_N7_QBC_AD3N_64
AD1
PL_DDR4_DQ0
IO_L24N_T3U_N11_64
AG1
PL_DDR4_DQ1
IO_L24P_T3U_N10_64
AF1
PL_DDR4_DQ2
IO_L23N_T3U_N9_64
AH1
PL_DDR4_DQ3
IO_L23P_T3U_N8_64
AH2
PL_DDR4_DQ4
IO_L21N_T3L_N5_AD8N_64
AF3
PL_DDR4_DQ5
IO_L21P_T3L_N4_AD8P_64
AE3
PL_DDR4_DQ6
IO_L20N_T3L_N3_AD1N_64
AH3
PL_DDR4_DQ7
IO_L20P_T3L_N2_AD1P_64
AG3
PL_DDR4_DQ8
IO_L18N_T2U_N11_AD2N_64
AC1
PL_DDR4_DQ9
IO_L18P_T2U_N10_AD2P_64
AB1
PL_DDR4_DQ10
IO_L17N_T2U_N9_AD10N_64
AC2
PL_DDR4_DQ11
IO_L17P_T2U_N8_AD10P_64
AB2
PL_DDR4_DQ12
IO_L15N_T2L_N5_AD11N_64
AB3
PL_DDR4_DQ13
IO_L15P_T2L_N4_AD11P_64
AB4
PL_DDR4_DQ14
IO_L14N_T2L_N3_GC_64
AC3
PL_DDR4_DQ15
IO_L14P_T2L_N2_GC_64
AC4
PL_DDR4_DM0
IO_L19P_T3L_N0_DBC_AD9P_64
AG4
PL_DDR4_DM1
IO_L13P_T2L_N0_GC_QBC_64
AD5
PL_DDR4_A0
IO_L8N_T1L_N3_AD5N_64
AG8
PL_DDR4_A1
IO_L3P_T0L_N4_AD15P_64
AB8
PL_DDR4_A2
IO_L8P_T1L_N2_AD5P_64
AF8
PL_DDR4_A3
IO_L3N_T0L_N5_AD15N_64
AC8
PL_DDR4_A4
IO_L11P_T1U_N8_GC_64
AF7
PL_DDR4_A5
IO_L4P_T0U_N6_DBC_AD7P_64
AD7
PL_DDR4_A6
IO_L9N_T1L_N5_AD12N_64
AH7
PL_DDR4_A7
IO_L2P_T0L_N2_64
AE9

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PL_DDR4_A8
IO_L9P_T1L_N4_AD12P_64
AH8
PL_DDR4_A9
IO_L1P_T0L_N0_DBC_64
AC9
PL_DDR4_A10
IO_L4N_T0U_N7_DBC_AD7N_64
AE7
PL_DDR4_A11
IO_L7N_T1L_N1_QBC_AD13N_64
AH9
PL_DDR4_A12
IO_L6N_T0U_N11_AD6N_64
AC6
PL_DDR4_A13
IO_L1N_T0L_N1_DBC_64
AD9
PL_DDR4_BA0
IO_T1U_N12_64
AH6
PL_DDR4_BA1
IO_L5N_T0U_N9_AD14N_64
AC7
PL_DDR4_RAS_B
IO_T2U_N12_64
AB5
PL_DDR4_CAS_B
IO_L5P_T0U_N8_AD14P_64
AB7
PL_DDR4_WE_B
IO_L11N_T1U_N9_GC_64
AF6
PL_DDR4_ACT_B
IO_L13N_T2L_N1_GC_QBC_64
AD4
PL_DDR4_CS_B
IO_L6P_T0U_N10_AD6P_64
AB6
PL_DDR4_BG0
IO_L2N_T0L_N3_64
AE8
PL_DDR4_RST
IO_L7P_T1L_N0_QBC_AD13P_64
AG9
PL_DDR4_CLK_N
IO_L10N_T1U_N7_QBC_AD4N_64
AG5
PL_DDR4_CLK_P
IO_L10P_T1U_N6_QBC_AD4P_64
AG6
PL_DDR4_CKE
IO_T3U_N12_64
AE4
PL_DDR4_OTD
IO_L19N_T3L_N1_DBC_AD9N_64
AH4
Part 2.4: QSPI Flash
The FPGA core board ACU5EV is equipped with one 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U5
MT25QU256ABA1EW9
256Mbit
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS