Alinx KINTEX UltraScale AXKU062 User manual

KINTEX UltraScale
Development Board
AXKU062
User Manual

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
2 / 51
www.alinx.com
Version Record
Version
Modify Record
REV1.0
Create Documents

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
3/51
http://www.alinx.com.cn
3/51
Table of Contents
Version Record.................................................................................................................................2
Table of Contents............................................................................................................................3
Part 1 AXKU062 Development Board......................................................................................7
Part 1.1: FPGA Development Board Introduction.......................................................7
Part 1.2: FPGA Chip................................................................................................................8
Part 1.3: DDR4 DRAM ........................................................................................................... 9
Part 1.4: QSPI Flash..............................................................................................................13
Part 1.5: Clock configuration........................................................................................... 15
Part 1.6: LED Light................................................................................................................15
Part 1.7: Power Supply....................................................................................................... 16
Part 1.8: Size Dimension....................................................................................................18
Part 1.9: Board to Board Connectors pin assignment............................................18
Part 2: Carrier Board....................................................................................................................28
Part 2.1: Introduction..........................................................................................................28
Part 2.2: PCIE X8 interface................................................................................................ 29
Part 2.3: SFP+ Optical fiber interface ........................................................................... 30
Part 2.4: Gigabit Ethernet Interface ...............................................................................32
Part 2.5: USB to Serial Port............................................................................................... 33
Part 2.6: FMC Expansion Port.......................................................................................... 34
Part 2.7: SD Card Slot......................................................................................................... 44
Part 2.8: SMA Interface...................................................................................................... 45
Part 2.9: Temperature Sensor and EEPROM...............................................................45
Part 2.10: LED Light............................................................................................................. 46
Part 2.11: Keys.......................................................................................................................48
Part 2.12: JTAG Interface................................................................................................... 49
Part 2.13: Power Supply.....................................................................................................49
Part 2.14: Fan......................................................................................................................... 50
Part 2.15:Size Dimension...................................................................................................51

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
4 / 51
www.alinx.com
Alinx Electronic Technology (Shanghai) Co., Ltd, based on KINTEX UltraSacale
development platform for the architecture (model: AXKU062) has been officially
released. In order to let you quickly understand this development platform, we have
compiled this user manual.
AXKU062 adopt the mode of core board and expansion board, it is convenient for
the client to do the secondary development and utilization of the core board. The
core board mounts four 1GB high-speed DDR4 SDRAM chips and two 128Mb QSPI
FLASH. The AXKU062 FPGA development board expands the rich peripheral interface,
including two 10G optical SFP interfaces, three FMC expansion interfaces (one HPC，
two LPC), one gigabit network interface, one UART serial interface, one SD card
interface and LED keys etc.
The following figure shows the structure of the entire development system:

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
5/51
http://www.alinx.com.cn
5/51
Through this diagram, you can see the interfaces and functions that the AXKU062
FPGA Development Board contains:
FPGA Core Board
1) FPGA Chip：Xilinx KINTEX UltraSacaleCHIP XCKU060。
2) DDR4：With four large-capacity 1GB (4 GB total) high-speed DDR4 SDRAM,
used as FPGA data storage, image analysis cache, data processing.
3) QSPI FLASH：Two 128Mbit QSPI NOR FLASH memory chip can be used as a
storage for FPGA chip configuration files and user data;
4) one differential crystal vibration of 200 Mhz.
5) 2 diode LEDs, 1 power indicator, 1 DONE configuration indicator.
Development Board
1) Two SFP and optical fiber communication interfaces，each fiber optical data
communication receives and transmits at speeds of up to 16.3 Gb/s.
2) One PCIE3.0 X8 interfaces ， endpoint mode ， use to communicate datas

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
6 / 51
www.alinx.com
between PC and PCIE.
3) USB Uart interface，used for communication with the computer for user
debugging. The serial port chip adopts the USB-UAR chip of Silicon Labs
CP2102GM, and the USB interface adopts the MINI USB interface.
4) 1 channel 10/100M/1000MEthernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network interface
chip uses Micrel's KSZ9031 industrial grade GPHY chip.
5) 3 standard FMC expansion port, including 2 LPC FMC expansion ports and
1 HPC FMC expansion port, which can be connected to various FMC
modules of Xilinx or Alinx(HDMI input and output modules, binocular
camera modules,high-speed AD modules, etc. )
6) 1 Micro SD card holder, used to store operating system image and file system.
7) 2 SMA external interfaces，the pins are connected to the transceiver for
external high-speed input and output signals.
8) Onboard a temperature and humidity sensor chip LM75 for detecting
the temperature and humidity of the environment around the board.
9) One EEPROM, used for IIC bus communication and storage of some
customer-defined information.
10) A 10-pin 2.54mm spacing standard JTAG ports for FPGA program
download and debugging. Users can debug and download FPGAs through
XILINX downloader.
11) 2 156.25Mhz differential crystal onboard provides reference clock for
transceiver.
12) 7 LEDs, 1 power indicator, 4 user indicators,1 pair of panel indicator.
13) 2 user keys, 1 reset key, connect to the normal IO of the FPGA.

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
7/51
http://www.alinx.com.cn
7/51
Part 1 AXKU062 Development Board
Part 1.1: FPGA Development Board Introduction
ACKU060(core board model, the same below) FPGA core board,FPGA chip is
based on XCKU060-2FFVA1156I of XILINX company Kintex Ultrascale series.This core
board uses four Micron's MT40A512M16LY-062EIT, each of which has a capacity of
1GB, total capacity is 4 GB. In addition, FPGA chip configuration uses 2128MBit QSPI
FLASH,used as FPGA data storage and system files.
The six board-to-board connectors of the core board AXKU062 expand 359 IOs,
Of which 104 IO levels of BANK64 and BANK65 is 3.3V, while other IOs levels of bank
is 1.8V; In addition,the core board also extended 20 pairs of high-speed Transceiver
GTH interfaces. For users who need a lot of IO, this core board will be a good choice.
And IO connection part, the line between the chip and the interface have been done
the equal length and differential processing, and the core board size is only 80 * 60
(mm), very suitable for secondary development.

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
8 / 51
www.alinx.com
ACKU060 Core Board (Front View)
Part 1.2: FPGA Chip
The FPGA development board uses Xilinx's KINTEX UltraScale chip, model number
XCKU060-2FFVA1156I. The speed class is 2 and the temperature class is industrial.
This model is a FFVA1156 package with 1156 pins and a 1.0mm pitch. The chip
naming rules for Xilinx KINTEX UltraScale FPGA are shown in Figure 1-2-1 below:
Figure 1-2-1: The Chip Model Definition of KINTEX UltraScale Series
The main parameters of AXKU062 are as follows：
Name
Specific parameters
Logic Cells
725,550
CLB LUTs
331,680
CLB flip-flops
663,360
Block RAM（Mb）
38.0
DSP Slices
2,760
PCIe Gen3 x8
3
GTH Transceiver
20 个，16.3Gb/s max
Speed Grade
-2
Temperature Grade
Industrial

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
9/51
http://www.alinx.com.cn
9/51
Part 1.3: DDR4 DRAM
The AXKU062 FPGA development board is equipped with four Micron 1GB DDR4
chips, model MT40A512M16LY-062EIT. Four DDR4 SDRAMs form a 64-bit bus width.
Because four DDR4 chips are connected to the FPGA, the DDR4 SDRAM can run at
speeds up to 1200MHz, and four DDR4 memory systems are directly connected to
the BANK44, BANK45, and BANK46 interfaces of the FPGA. The specific configuration
of DDR4 SDRAM is shown in Table 3-1.
Table 3-1 DDR4 SDRAM Configuration
Bit Number
Chip Model
Capacity
Factory
U45,U47,U48,U49
MT40A512M16LY-062EIT
512M x 16bit
Micron
The hardware design of DDR4 requires strict consideration of signal integrity. We
have fully considered the matching resistor/terminal resistance, trace impedance
control, and trace length control in circuit design and PCB design to ensure
high-speed and stable operation of DDR3.
The hardware connection mode of FPGA and DDR4 DRAM is shown in Figure
1-3-1:

KINTEX UltraScale+ FPGA Board AXKU062 User Manual
10 / 51
www.alinx.com
Figure1-3-1 DDR4 DRAM schematic diagram
4 DDR4 DRAM pin assignments:
Signal Name
FPGA Pin Name
FPGA Pin
PL_DDR4_DQ0
IO_L3N_T0L_N5_AD15N_44
AE20
PL_DDR4_DQ1
IO_L2N_T0L_N3_44
AG20
PL_DDR4_DQ2
IO_L2P_T0L_N2_44
AF20
PL_DDR4_DQ3
IO_L5P_T0U_N8_AD14P_44
AE22
PL_DDR4_DQ4
IO_L3P_T0L_N4_AD15P_44
AD20
PL_DDR4_DQ5
IO_L6N_T0U_N11_AD6N_44
AG22
PL_DDR4_DQ6
IO_L6P_T0U_N10_AD6P_44
AF22
PL_DDR4_DQ7
IO_L5N_T0U_N9_AD14N_44
AE23
PL_DDR4_DQ8
IO_L8N_T1L_N3_AD5N_44
AF24
PL_DDR4_DQ9
IO_L11P_T1U_N8_GC_44
AJ23
PL_DDR4_DQ10
IO_L8P_T1L_N2_AD5P_44
AF23
PL_DDR4_DQ11
IO_L12N_T1U_N11_GC_44
AH23
PL_DDR4_DQ12
IO_L9N_T1L_N5_AD12N_44
AG25
PL_DDR4_DQ13
IO_L11N_T1U_N9_GC_44
AJ24
PL_DDR4_DQ14
IO_L9P_T1L_N4_AD12P_44
AG24
PL_DDR4_DQ15
IO_L12P_T1U_N10_GC_44
AH22