Alinx AV6045 User manual

FPGA Video Processing
Development Platform
AV6045
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-05-01
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................... 2
Part 1: FPGA Development Board Introduction......................................... 6
Part 2: Function realization........................................................................ 8
Part 2.1: Video Input............................................................................8
Part 2.2: Video Output.......................................................................11
Part 3: AC6045 core board...................................................................... 12
Part 3.1: AC6045 Core Board Introduction........................................13
Part 3.2: DDR3 DRAM ......................................................................13
Part 3.3: SPI Flash ............................................................................15
Part 3.4: AV6045 Power Supply ........................................................17
Part 3.5: Expansion Ports..................................................................19
Part 3.6: Powe interface on Core Board............................................22
Part 3.7: Crystal oscillator on Core Board .........................................23
Part 3.8: LED Light on Core Board....................................................25
Part 3.9: Structure Diagram...............................................................27
Part 4: Carrier board.................................................................................28
Part 4.1: Carrier board Introduction...................................................28
Part 4.2: VGA Display Interface.........................................................29
Part 4.3: HDMI Output Interface........................................................31
Part 4.4: HDMI Input Interface...........................................................34
Part 4.5: Video input interface...........................................................36
Part 4.6: Gigabit Ethernet Interface...................................................38
Part 4.7: ARM Controller ...................................................................41
Part 4.8: Camera Module Interface ...................................................47
Part 4.9: Expansion Header ..............................................................48
Part 4.10: JTAG Interface..................................................................50

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Part 4.11: Buttons..............................................................................51
Part 4.12: Power Supply....................................................................52

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This XILINX FPGA Video Processing development platform (module:
AV6045) adopts the core board + carrier board mode, which is convenient for
users to use the core board for secondary development.
This FPGA video image processing development platform is derived from
the improvement of our company's ALTERA video development board. In terms
of hardware design, we added HDMI input, DVI output, Gigabit Ethernet,
CMOS Camera interface and Micro in the original design. Peripherals such as
SD card slot. This greatly enriches the functions of the video image processing
board, not only satisfies the functions of FPGA video image processing, but
also provides network communication for video image storage and video
images. Therefore, this development platform can be called "professional" and
"all-round". Such a product is very suitable for students, engineers and other
groups engaged in FPGA video image processing or video image
communication and storage.

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Part 1: FPGA Development Board Introduction
The entire structure of the AV6045 FPGA development board is inherited
from our consistent core board + carrier board mode. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of FPGA+ DDR3+ FLASH. It
undertakes the core algorithm of video image processing, fully utilizes the
parallel processing capability of FPGA, and the high-speed data reading and
writing between FPGA and DDR3. The bandwidth of the whole system is up to
10Gb/s (666M*). 16bit); In addition, DDR3 capacity is up to 2Gbit, which meets
the need for high buffers during video processing. The selected FPGA is the
high-speed FPGA chip of XC6SLX45-2FG484 of XILINX SPARTAN6 series.
The FPGA is packaged in BGA 484. SPARTAN6 FPGA integrated DDR
controller hard core, and DDR3 communication clock frequency reached
333Mhz, DDR3 internal 666Mhz, fully meet the needs of four 1080p video
processing.

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XILINX
XC6SLX45 ARM
DDR3
TW2867
视频
输入
接口
视频
输入
接口
视频
输入
接口
视频
输入
接口
ADV7123
VGA输出
SiI9134
HDMI输出
SiI9013
HDMI输入
RTL8211E
以太网网
口CMOS接口
CP2102
USB UART SD Card
40PIN Connector
Figure 1-1-1: The Schematic Diagram of the AV6045
Through this diagram, you can see the interfaces and functions that the
AV6045 FPGA Development Board contains:
4-channel video input
Select Techwell TW2867, can input 4 composite video signals,
PAL/NTSC/SECAM automatic identification, output BT656,
multiplexable bus, FPGA-side demultiplexing, saving IO
1-channel VGA Output
The ADV7123, a three-channel, 10-bit DAC converter from Analog
Devices, supports RGB digital input and VGA output. Supports
conversion rates up to 240MSPS, up to 1080p@60Hz video image

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output
1-channel HDMI Output
Select Silion Image SIL9134 HDMI encoding chip, support up to
1080P@60Hz output, support 3D output.
1-channel HDMI Input
Select Silion Image SIL9013 HDMI decoder chip, support up to
1080P@60Hz input, support different formats of data output
1-channel 10/100M/1000M Ethernet with RJ-45 interface
The Gigabit Ethernet interface chip uses Realtek's RTL8211EG
Ethernet PHY chip to provide network communication services to users.
The RTL8211EG chip supports 10/100/1000 Mbps network
transmission rate;
1-channel CMOS Input
CMOS camera interface, can be connected to ALINX's 300,000-pixel
OV7670 camera module or 5 megapixel OV5640 camera module
On the FPGA carrier board, an ARM chip (STM32F103) is mounted on the
board, and each interface chip and FPGA on the board are configured through
I2C.
Part 2: Function realization
Part 2.1: Video Input
The video development board can input 4 composite video signals through
TW2867, PAL/NTSC/SECAM automatically recognizes and output BT656; or
through SIL9013, can input HDMI video signals; or through CMOS interface,
can input image signals acquired by CMOS camera. Therefore, there are many

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video sources available for development boards, such as:
1)Surveillance cameras
Through the FPGA development board, it is possible to realize
four-channel surveillance camera through the display (VGA/DVI/HDMI
interface, which can realize 1080p) for split-screen display. Our development
board is equivalent to the digital video host in the Figure below.
Figure 2-1-1: Split Screen Display Surveillance cameras
2)Set top box
The video source obtained by connecting the HDMI output of the set-top
box can be used to implement picture-in-picture (PIP) function through FPGA
development platform.

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Figure 2-1-2: Set top box
3)Camera Module
CMOS camera interface, plug in ALINX 30 megapixel camera module or 5
megapixel camera module, real-time display 1080P video image on VGA
display or HDMI display.
Figure 2-1-3: Camera Module

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Part 2.2: Video Output
There are two kinds of video output on the FPGA development board: you
can connect a VGA monitor to display VGA images; you can also connect
HMDI monitors or TV to display HDMI video signals. The video display for VGA
and HDMI output is up to 1080P@60Hz.
Current computer monitors basically support one of VGA or HDMI inputs.
As long as one of the VGA/HDMI interfaces of the display is connected to the
FPGA development board, the effect demonstration of the video image can be
realized. The picture below shows a computer monitor with VGA and HDMI
display connectors.
Figure 2-2-1: VGA/HDMI interfaces of the computer monitor

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Part 3: AC6045 core board

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Part 3.1: AC6045 Core Board Introduction
FPGA+ DDR3 core board is based on XILINX's SPARTAN6 series
XC6SLX45-2FG484I. This chip develops a high-performance core board with
high speed, high bandwidth and high capacity. It is suitable for video image
processing and high-speed data acquisition.
This core board uses MICRON's MT41J128M16LA-187E DDR3 chip with
a capacity of 2Gbit; 16bit bus mode, read and write data bandwidth between
FPGA and DDR3 is up to 10Gb; this configuration can meet the needs of 4
channels of 1080p video processing.
This core board expands 172 IO ports, which is a good choice for users
who need a lot of IO. Moreover, the FPGA chip to the interface is treated with
the same length, and the core board size is only 60*60 (mm), which is very
suitable for secondary development.
Part 3.2: DDR3 DRAM
Figure 3-2-1 detailed part of the DDR3 schematic (For details, please refer
to the schematic provided by us.)
Figure 3-2-1: DDR3 schematic

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In addition, the normal operation of DDR3 requires DDR3 address line and
control line to provide termination voltage VTT and DDR3 chip reference
voltage VREF, VTT and VREF voltage are both 1.5V, the following Figure 3-2-1
is the power part schematic.
Figure 3-2-2: DDR3 Power for VTT/VREF
Figure 3-2-3: DDR3 Power Circuit on the FPGA Board

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DDR3 is connected to the BANK3 of the FPGA.
DDR3 Pin Assignment
Pin Name
FPGA Pin
Pin Name
FPGA Pin
DDR3_A[0]
H2
DDR3_A[11]
C1
DDR3_A[1]
H1
DDR3_A[12]
D1
DDR3_A[2]
H5
DDR3_A[13]
G6
DDR3_A[3]
K6
DDR3_A[14]
F5
DDR3_A[4]
F3
DDR3_BA[0]
G3
DDR3_A[5]
K3
DDR3_BA[1]
G1
DDR3_A[6]
J4
DDR3_BA[2]
F1
DDR3_A[7]
H6
DDR3_nCAS
K4
DDR3_A[8]
E3
DDR3_CKE
D2
DDR3_A[9]
E1
DDR3_CLK_P
H4
DDR3_A[10]
G4
DDR3_CLK_N
H3
DDR3_nRAS
K5
DDR3_DQ[8]
P2
DDR3_nWE
F2
DDR3_DQ[9]
P1
DDR3_ODT
J6
DDR3_DQ[10]
R3
DDR3_RESET
C3
DDR3_DQ[11]
R1
DDR3_LDM
L4
DDR3_DQ[12]
U3
DDR3_UDM
M3
DDR3_DQ[13]
U1
DDR3_DQ[0]
N3
DDR3_DQ[14]
V2
DDR3_DQ[1]
N1
DDR3_DQ[15]
V1
DDR3_DQ[2]
M2
DDR3_LDQS_P
L3
DDR3_DQ[3]
M1
DDR3_LDQS_N
L1
DDR3_DQ[4]
J3
DDR3_UDQS_P
T2
DDR3_DQ[5]
J1
DDR3_UDQS_N
T1
DDR3_DQ[6]
K2
DDR3_DQ[7]
K1
Part 3.3: SPI Flash
The FPGA core board AC6045 is equipped with one 64MBit SPI FLASH,
and the model is W25Q64BV, which uses the 3.3V CMOS voltage standard.

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Due to the non-volatile nature of SPI FLASH, it can be used as a boot device
for the system to store the boot image of the system. These images mainly
include FPGA bit files, core application code and other user data files. The
specific models and related parameters of SPI FLASH are shown in Table
3-3-1.
Position
Model
Capacity
Factory
U8
W25Q64BV
64M Bit
Winbond
Table 3-3-1: SPI FLASH Specification
Figure 3-3-1: SPI Flash schematic
Figure 3-3-2: W25Q64BV chip on the FPGA Board

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SPI Flash pin assignments:
Pin Name
FPGA Pin
SPI_CLK
Y21
SPI_CSn
T5
SPI_DIN
AB20
SPI_DOUT
AA20
Part 3.4: AV6045 Power Supply
In order for FGPA to work properly, it is necessary to provide three power
supplies for P3V3, P1V2 and VCCIO for the FPGA. P3V3 is for the VCCAUX of
the FPGA, the voltage is 3.3V; P1V2 is for the VCCINT of the FPGA, the
voltage is 1.2V; VCCIO is for the VCCO of the BANK0, BANK1, BANK2 of the
FPGA. In addition, DDR3 on the core board requires P1V5 and a voltage of
1.5V (used to generate VTT and VREF), as mentioned above, and will not be
repeated here.
The VCCO of the FPGA is separated from the VCCAUX power supply. The
purpose is to enable the BANK IO voltage of the FPGA to be flexibly adjusted.
Different output voltages are obtained by adjusting the resistance value of the
VCCIO power supply section, so that the IO level of the FPGA core board can
be applied to different voltages.
The three-way power supply (P1V2, VCCIO, P1V5) adopts the
TLV62130RGT DCDC chip imported from American TI Company. It has high
efficiency, small size, no heat, and can provide large current and small ripple. It
is an excellent power solution for FPGA. A large number of high-grade
imported capacitors and inductors are used to ensure that the power supply of
the system is stable and reliable. The other circuit (P3V3) uses a smaller ripple
LDO chip SPX3819M5-L-3-3 because of the small current required.

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Figure 3-4-1：Power Supply on core board schematic

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Figure 3-4-2: Power Supply Circuit on the AC6045 FPGA Core Board
Part 3.5: Expansion Ports
The core board has a total of two high-speed expansion ports, which is
connected with the FPGA carrier board by two 100-pin inter-board connectors.
The inter-board connector uses AMP Tyco board-to-board connector
5177984-4, with a PIN pitch of 0.8mm, and a male connector with a height of
5mm. It is connected with the female AMP connector 5177983-4 of the FPGA
carrier board, which is configured for high speed data communication.

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Figure 3-5-1: Expansion Ports P1