Intel Agilex User manual

Intel® Agilex™ Logic Array Blocks
and Adaptive Logic Modules User
Guide
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Contents
1. Intel® Agilex™ LAB and ALM Overview............................................................................ 3
2. Intel Hyperflex™ Register................................................................................................4
3. Intel Agilex LAB and ALM Architecture and Features...................................................... 5
3.1. LAB..................................................................................................................... 5
3.1.1. MLAB....................................................................................................... 6
3.1.2. Local and Direct Link Interconnects.............................................................. 6
3.1.3. Carry Chain Interconnects.......................................................................... 7
3.1.4. LAB Control Signals....................................................................................8
3.2. ALM.....................................................................................................................9
3.2.1. ALM Resources.......................................................................................... 9
3.2.2. ALM Output.............................................................................................10
3.2.3. ALM Operating Modes............................................................................... 11
4. Document Revision History for the Intel Agilex Logic Array Blocks and Adaptive
Logic Modules User Guide........................................................................................ 20
Contents
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1. Intel® Agilex™ LAB and ALM Overview
The logic array block (LAB) is composed of basic building blocks known as adaptive
logic modules (ALMs). You can configure the LABs to implement logic functions,
arithmetic functions, and register functions.
You can use half of the available LABs in the Intel® Agilex™ devices as memory LABs
(MLABs). Certain devices may have a higher MLAB ratio.
The Intel Quartus® Prime software and other supported third-party synthesis tools
automatically choose the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions.
Related Information
Intel Hyperflex™ Core Architecture, Intel Agilex Device Overview
Provides more information about Hyper-Registers and the Intel Hyperflex™ core
architecture. Hyper-Registers are additional registers available in every
interconnect routing segment throughout the core fabric, including the routing
segments connected to the LAB inputs and outputs.
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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2. Intel Hyperflex™ Register
The Intel Agilex device family is based on the Intel Hyperflex™ core architecture.
The Intel Agilex LAB contains Intel Hyperflex registers and other features designed to
facilitate retiming. Intel Hyperflex registers are available in ALMs and carry chains. As
shown in the Intel Agilex ALM Connection Details figure, the Intel Hyperflex registers
are located on the synchronous clear and clock enable inputs to increase or reduce
path delay. All the Intel Hyperflex registers can be enabled and are controlled by the
Intel Quartus Prime software during retiming.
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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3. Intel Agilex LAB and ALM Architecture and Features
The following sections describe the LAB and ALM for Intel Agilex devices.
3.1. LAB
The LABs are configurable logic blocks that consist of a group of logic resources. Each
LAB contains dedicated logic for driving control signals to its ALMs. The MLAB is a
superset of the LAB and includes all the LAB features. There are a total of 10 ALMs in
each LAB, as shown in the Intel Agilex LAB and MLAB Structure figure.
Figure 1. Intel Agilex LAB Structure and Interconnects Overview
This figure shows an overview of the Intel Agilex LAB and MLAB structure with the LAB interconnects.
Row Interconnects of
Variable Speed and Length
Local
Interconnect
C8 C1/C4
R12
R0/R1/R2/R4/R6
C1/C4 C8
Column Interconnects of
Variable Speed and Length
ALMs
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Related Information
MLAB on page 6
3.1.1. MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can
configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in
a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.
Figure 2. Intel Agilex LAB and MLAB Structure
MLAB LAB
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
LAB Control Block
LAB Control Block
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
3.1.2. Local and Direct Link Interconnects
Each LAB can drive out 60 ALM outputs. A subset of these can directly drive LAB
inputs, but any connection to a different row or column must use at least one general-
purpose routing wire.
The local interconnect drives the ALM inputs. ALM outputs, as well as column and row
interconnects drive the local interconnect.
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Figure 3. Intel Agilex LAB Local and Direct Link Interconnects
R1
R0/R2/R4/R6
C1 C4
Fast LUT
Outputs
3.1.3. Carry Chain Interconnects
There is a dedicated carry chain path between the ALMs. Intel Agilex devices include
an enhanced interconnect structure in LABs for routing carry chains for efficient
arithmetic functions. These ALM-to-ALM connections bypass the local interconnect.
The Intel Hyperflex registers are added to the carry chain to enable flexible retiming
across a chain of LABs and the Intel Quartus Prime Compiler automatically takes
advantage of these resources to improve utilization and performance.
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Figure 4. Carry Chain Interconnects
Carry Chain
Routing to Adjacent ALM
Local Interconnect
Routing among ALMs
in the LAB
Local
Interconnect
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
ALM 10
3.1.4. LAB Control Signals
There are two clock sources in each LAB control block, which generate two LAB clocks
(LABCLK[1:0]) and two delayed LAB clocks (LABCLK_Phi1[1:0]) to drive the ALM
registers and Hyper-Registers in the LAB. The delayed clock source is used for time-
borrowing feature. The LAB supports two unique clock enable signals, as well as
additional clear signals, for the ALM registers.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. A low skew clock network distributes global signals to the row clocks [5..0].
The MultiTrack interconnect consists of continuous, performance-optimized routing
lines of different lengths and speeds used for routing efficiency. The Intel Quartus
Prime Compiler automatically routes critical design paths on faster interconnects to
improve design performance and optimizes the device resources.
3.1.4.1. Clear Logic Control
LAB-wide signals control the logic for the ALM register's clear signal. The ALM register
directly supports both a synchronous and an asynchronous clear. Each LAB supports
up to two synchronous clear signals and two asynchronous clear signals, provided that
the total number of clear signals is no greater than three.
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Intel Agilex devices provide a device-wide reset pin (DEV_CLRn) that resets all the
registers in the device. You can enable the DEV_CLRn pin in the Intel Quartus Prime
software before compilation. The device-wide reset signal overrides all other control
signals.
Figure 5. Intel Agilex LAB-Wide Control Signals
synclr0 labclk[0]
labclk_ph1[0] labclk_ph1[1]
labclkena0 labclkena1labclr0/
synclr1
labclr1
Dedicated Lane
LAB Row Clocks
Local
Interconnect
6
6
6
labclk[1]
Delay Cell
Delay Cell
3.2. ALM
The following sections cover the ALM resources, ALM output, and ALM operating
modes.
3.2.1. ALM Resources
Each ALM contains a variety of LUT-based resources that can be divided between two
combinational adaptive LUTs (ALUTs), a two-bits full adder, and four registers.
With up to eight inputs for the two combinational ALUTs, one ALM can implement
various combinations of two functions. This adaptability allows an ALM to be
completely backward-compatible with four input LUT architectures. One ALM can also
implement a subset of eight input functions.
One ALM contains four programmable registers. Each register has the following ports:
• Data in
• Data out
• Normal LAB clock
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• Delayed LAB clock
• Clock enable
• Synchronous clear
• Asynchronous clear
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the
clock enable signal, clock, and asynchronous or synchronous clear control signals of
an ALM register. The clock enable signal has priority over synchronous reset signal.
For combinational functions, the registers are bypassed and the output of the look-up
table (LUT) and adders drives directly to the outputs of an ALM. Two fast outputs are
available for 6 LUT outputs and bottom 5 LUT outputs to bypass the output mux and
connect to another LAB for critical path adjustment.
Figure 6. Intel Agilex ALM High-Level Block Diagram
datab
datac1
adder1
datad0
datae
6 LUT output
Sum output (Top)
Sum output (Bottom)
5 LUT output (Top)
5 LUT output (Bottom)
datac0
dataa
carry_in
carry_out
Combinational/
Memory ALUT0
Combinational/
Memory ALUT1
datad1
dataf
LUT
datab
dataa
labclk
reg1 To General Routing
reg0
reg3
reg2
labclk_phi1 6 LUT fast output
5 LUT fast output (Bottom)
adder0
3.2.2. ALM Output
The general routing outputs in each ALM drive the local, row, and column routing
resources. Six ALM outputs, including two fast output paths, can drive column, row, or
direct link routing connections.
The LUT, adder, or register output can drive the ALM outputs. Both the LUT or adder
and the ALM register can drive out of the ALM simultaneously.
Register packing improves device utilization by allowing unrelated register and
combinational logic to be packed into a single ALM. The ALM can also drive out
registered and unregistered versions of the LUT or adder output.
The following figure shows the Intel Agilex ALM connectivity. In the Intel Quartus
Prime Resource Property Editor, the entire ALM connection is simplified. Some routings
will be routed internally by the Intel Quartus Prime software.
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Figure 7. Intel Agilex ALM Connection Details
Legend:
HyperFlex Registers
To General
Routing
D
Q
D
Q
(e) (f) (g) (h)
D
Q
D
Q
aclr
DQ
nCEout
aclr
DQ
nCEout
aclr
DQ
nCEout
aclr
DQ
nCEout
4 LUT
4 LUT
4 LUT
4 LUT
datae
datad0
datac0
dataa
datab
datac1
datad1
dataf
carry_in
carry_out
Added_Sum0
5LUT_Top
6LUT
Added_Sum1
5LUT_Bottom
(c)
(a) (b) (d) (a) (b) (c) (d)
(e) (f) (g) (h) (e) (f) (g) (h) (e) (f) (g) (h)
synclr0
synclr1
labclkena0
labclkena1
labclk[0]
labclk[1]
labclk_phi1[0]
labclk_phi1[1]
labclr0
labclr1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
(i) (j) (i) (j)
3.2.3. ALM Operating Modes
The Intel Agilex ALM operates in any of the following modes:
• Normal mode
• Extended LUT mode
• Arithmetic mode
3.2.3.1. Normal Mode
Normal mode allows two functions to be implemented in one Intel Agilex ALM, or a
single function of up to six inputs.
Up to eight data inputs from the LAB local interconnect are inputs to the combinational
logic.
The ALM can support certain combinations of completely independent functions and
various combinations of functions that have common inputs. The Intel Quartus Prime
Compiler automatically selects the inputs to the LUT. ALMs in normal mode support
register packing.
The following figure shows a combination of different input connections for the LUT
mode. In your design, the Intel Quartus Prime software may assign different input
namings during compilation.
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Figure 8. ALM in Normal Mode
datab
datae
datad0
dataa
datac0 combout0
combout1
combout0
combout1
datac1
datad1
dataf
datab
datae
datad0
dataa
datac0
datac1
datad1
dataf
datab
datae
datad0
dataa
datac0
datac1
datad1
dataf
datab
datae
datad0
dataa
datac0
datac1
datad1
dataf
4-Input
LUT
4-Input
LUT
4-Input
LUT
6-Input
LUT
datae
datad
datac
dataa
datab
dataf
combout0
5-Input
LUT
5-Input
LUT
combout0
combout1
5-Input
LUT
combout0
combout1
5-Input
LUT
3-Input
LUT
Combinations of functions with fewer inputs than those shown are also supported. For
example, combinations of functions with the following number of inputs are supported.
• 4 and 3
• 3 and 3
• 3 and 2
• 5 and 2
For the packing of two 5-input functions into one ALM, the functions must have at
least two common inputs. The common inputs are dataa and datab. The
combination of a 4-input function with a 5-input function requires one common input
(either dataa or datab).
In a sparsely used device, functions that could be placed in one ALM may be
implemented in separate ALMs by the Intel Quartus Prime software to achieve the best
possible performance. As a device begins to fill up, the Intel Quartus Prime software
automatically uses the full potential of the Intel Agilex ALM. The Intel Quartus Prime
Compiler automatically searches for functions using common inputs or completely
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independent functions to be placed in one ALM to make efficient use of device
resources. In addition, you can manually control resource use by setting location
assignments.
Figure 9. 6-Input LUT Mode Function in Normal Mode
labclk
reg0
labclk_phi1
6-Input LUT
datae
datad
datac
dataa
datab
dataf
To General
Routing
reg1
reg2
reg3
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Figure 10. 3-Input LUT Mode Function in Normal Mode
dataa and datab are available for register packing.
3-Input LUT
datae
datad0
datac0
reg0
To General
Routing
reg1
reg2
reg3
datac1
datad1
dataf
datab
3-Input LUT
dataa
labclk
labclk_phi1
You can implement any three to six input function using the following inputs:
•datae
•datad0
•datac0
•datac1
•datad1
•dataf
•dataa and datab—whereby dataa and datab are shared across both LUTs to
provide flexibility to implement a different function in each LUT.
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Both dataa and datab inputs support the register packing feature. If you enable the
register packing feature, both dataa and datab inputs or either one of the inputs
bypass the LUT and directly feed into the register, depending on the packed register
mode used. For Intel Agilex devices, the following types of packed register modes are
supported:
• 5-input LUT with 1 packed register path
• 5-input LUT with 2 packed register paths
• Two 3-input LUTs with 2 packed register paths
The 3-input LUT with 2 packed register paths is illustrated in the 3-Input LUT Mode
Function in Normal Mode figure. For Intel Agilex devices, the 6-input LUT mode does
not support the register packing feature.
3.2.3.2. Extended LUT Mode
Figure 11. Supported 8-Input Functions in the Extended LUT Mode
Extended
LUT
datae
datad0
datac0
dataa
datab
datac1
datad1
dataf
labclk
reg0
labclk_phi1
To General
Routing
reg1
reg2
reg3
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Certain 8-input functions can be implemented in a single ALM using all the LUT inputs:
•datae
•datad0
•datac0
•dataa
•datab
•datac1
•datad1
•dataf
In the 8-input extended LUT mode, the packed register mode is supported, provided
that the packed register shares a dataa or datab input with the 8-input LUT.
3.2.3.3. Arithmetic Mode
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to perform pre-adder logic.
Therefore, each adder can add the output of two 4-input functions.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down
control, add and subtract control, and synchronous clear.
The clear and clock enable options are LAB-wide signals that affect all registers in the
LAB. You can individually disable or enable these signals for each pair of registers in
an adaptive LUT (ALUT). The Intel Quartus Prime software automatically places any
registers that are not used by the counter into other LABs.
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Figure 12. Intel Agilex ALM in Arithmetic Mode
labclk
4-Input LUT
reg0
datad0
datac0
dataa
datab
4-Input LUT
4-Input LUT
4-Input LUT
datac1
datad1
carry_in
carry_out
To General
Routing
reg1
labclk_phi1
reg2
reg3
3.2.3.3.1. Carry Chain
The carry chain provides a fast carry function between the dedicated adders in the
arithmetic mode.
The 2-bit carry select feature in Intel Agilex devices splits the propagation delay of
carry chains with the ALM. Carry chains can begin in either the first ALM or the sixth
ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local,
row, or column interconnects.
3.2.3.4. Time Borrowing and Latch Modes
In Intel Agilex devices, you can choose to use the registers in normal mode, time
borrowing mode, or latch mode depending on the selection of the LAB clocks
(LABCLK). There are a total of four LABCLK generated from two clock sources that
can be chosen for each register, provided that the same clock source is used for half of
the ALMs, as shown in Figure 7 on page 11.
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Within the four LABCLKs being generated, two out of the four LABCLKs are normal
LABCLK, while the remaining two LABCLK are the delayed clocks (LABCLK_Phi1).
The delay cell located in the LAB control block is responsible to add an extra delay on
the normal LABCLK and generate the delayed LABCLK_Phi1.
The following figures show the master and slave latches that within a register with a
timing diagram. The LABCLK_Phi1 is being routed into master latch while the normal
LABCLK is being connected into the slave latch. By delaying the clock of master latch,
an extra transparent window is added to accommodate long timing path prior to the
master latch.
Master Slave
xq
d
LABCLK_Phi1 LABCLK
cl cl
clock
LABCLK_Phi1
LABCLK
Normal
Time
Borrowed
LABCLK_Phi1
LABCLK
To accommodate and meet the hold timing during time-borrowing in the master latch,
an extra slave latch is added to the clock enable (CE) feedback path, to retain the old
data during the transparency window.
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DQ
D Q D Q
LABCLK_Phi1
(optionally delayed)
LABCLK
D
NSCLR
Note:
1. Add slave latch to CE feedback (CE_FB) path, holds previous state
during transparency window.
(1)
Q
CE_FB
Besides the time-borrowing mode, the Intel Agilex devices also support latch mode in
the ALM register, by controlling the LABCLK in the LAB control block. During the latch
mode, only one clock is available for the master and slave latch per LAB, respectively.
In the latch mode operation, LABCLK[1] is selected for the slave latch and held at
high, while LABCLK_Phi1[0] is selected for the master latch and the latch opens
when LABCLK_Phi1[0] equals to low.
xq
d
LABCLK_Phi1[0] LABCLK[1]
cl cl
Notes:
1. Master latch is used as a negative-latch during latch mode.
2. Slave latch is always open/transparent due to LABCLK[1] = Vcc.
(1) (2)
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4. Document Revision History for the Intel Agilex Logic
Array Blocks and Adaptive Logic Modules User Guide
Document
Version
Changes
2019.04.02 Initial release.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered