AMD XILINX VPK120 User manual

VPK120 Evaluaon Board
User Guide
UG1568 (v1.0) August 9, 2022
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Navigating Content by Design Process.................................................................................... 5
Additional Resources.................................................................................................................. 6
Block Diagram..............................................................................................................................6
Board Features............................................................................................................................ 7
Board Specifications....................................................................................................................9
Chapter 2: Board Setup and Configuration....................................................11
Standard ESD Measures........................................................................................................... 11
Board Component Location.....................................................................................................11
Default Jumper and Switch Settings....................................................................................... 16
Versal ACAP Configuration.......................................................................................................19
Chapter 3: Board Component Descriptions................................................... 21
Overview.....................................................................................................................................21
Component Descriptions......................................................................................................... 21
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 57
Overview.....................................................................................................................................57
Appendix B: Xilinx Design Constraints............................................................. 58
Overview.....................................................................................................................................58
Appendix C: Regulatory and Compliance Information........................... 59
CE Information...........................................................................................................................59
Compliance Markings............................................................................................................... 60
Appendix D: Additional Resources and Legal Notices.............................61
Xilinx Resources.........................................................................................................................61
Documentation Navigator and Design Hubs.........................................................................61
References..................................................................................................................................62
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Revision History.........................................................................................................................63
Please Read: Important Legal Notices................................................................................... 63
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Chapter 1
Introduction
Overview
The VPK120 evaluaon board features the Xilinx® Versal® ACAP XCVP1202 device. The
VPK120 board enables the demonstraon, evaluaon, and development of the applicaons listed
here, as well as other customer applicaons. Many features found on the VPK120 board are
subsets of exisng Versal ACAP boards (e.g., the VCK190 and VMK180 boards).
• Fiber opc
•Communicaons
• Data center compute acceleraon
• Aerospace and defense
• Test and measurement
The VPK120 evaluaon board is equipped with many of the common board-level features
needed for design development, including:
• QSFP-DD opcal transceiver support
• LPDDR4 component memory
• USB
• Ethernet networking interface
• One FMC+ expansion port
• PCIe®
Models of Boards
The following table lists the models for the VPK120 evaluaon board. See the VPK120
Evaluaon Board product page for details.
Chapter 1: Introduction
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Table 1: Models of VPK120 Evaluation Boards
Kit Description
EK-VPK120-G Xilinx Versal ACAP VPK120 evaluation kit
EK-VPK120-G-J Xilinx Versal ACAP VPK120 evaluation kit, Japan specific
EK-VPK120-G-ED (encryption
disabled)
Xilinx Versal ACAP VPK120 evaluation kit, China and Russia specific
Users of encryption-disabled kits will not be able to access the following features:
•Secure boot
•Secure key storage/management
•Crypto HW acceleration (PS and APU crypto accelerators)
•Encrypted bitstream loading
•Encrypted BOOT.BIN partitions
•PUF operation
•High-speed crypto (HSC)
Versal ACAP Kit Numbering
The Versal ACAP kit numbering is illustrated in the following gure.
Figure 1: Kit Numbering
EK - VP
Kit
Type
K 120 - G - J
ROHS
Indicator
Regional
Identifier
Silicon indicator
K = kit
Ensures there is no
confusion with silicon P/Ns
Options
J – Japan
ED – China/Russia
OEM – OEM kit
Product Number
Options
G – ROHS
Compliant
Family and series
(e.g., Versal ACAP
and Core)
Options
EK – Evaluation Kit
CK – Characterization Kit Examples
VPK120
VCK190
X26155-080422
Navigating Content by Design Process
Xilinx® documentaon is organized around a set of standard design processes to help you nd
relevant content for your current development task. All Versal® ACAP design process Design
Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This
document covers the following design processes:
Chapter 1: Introduction
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•Board System Design: Designing a PCB through schemacs and board layout. Also involves
power, thermal, and signal integrity consideraons. For more informaon, see Versal ACAP
Design Process Documentaon Board System Design.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VPK120 evaluaon board.
Block Diagram
A block diagram of the VPK120 evaluaon board is shown in the following gure.
Figure 2: Evaluation Board Block Diagram
Versal XCVP1202
VSVA2785
GTYP
GTYP
GTM
GTM
GTM
GTM
GTM
XPIO
GTYP
GTYP
GTYP
GTYP
PS/
PMC
2x LPDDR4
(1x32)
PCIe EP
GEN5 x16
1.8V
GPIO
3.3V
QSFP
Ctrl
FMC+
2x LPDDR4
(1x32)
USB 2.0
ULPI
SD 3.0
UART/I2C
PCIe Control
GEM
2x LPDDR4
(1x32)
EMIO
Mictor
GTYP
1588 CLK SMAs
QSFP-DD
QSFP-DD
1588 SMA
SysC
GPIO
2x QSPI
Lvl
Shftrs
Lvl
Shftrs
X26002-021822
Chapter 1: Introduction
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Board Features
The VPK120 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XCVP1202, VSVA2785 package
• Form factor: extended height PCIe®, double-slot (heatsink clearance)
• Onboard conguraon from:
○USB-to-JTAG bridge
○JTAG pod 2 mm 2x7 at cable connector
○microSD card (PS MIO I/F)
○Quad SPI (QSPI)/eMMC (system controller I/F)
○Dual QSPI
• Clocks
○ACAP bank 702/5/8 Si570 LPDDR4_CLK1/2/3 (DIMM) 200 MHz
○ACAP bank 503 Si570 REF_CLK 33.3333 MHz
○ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
○IEEE-1588 eCPRI 8A34001 clocks (various)
○ACAP bank 503 RTC Xtal 32.768 kHz
○ACAP bank GTY102/3/4/5 (REFCLK0) PCIe_CLK3/2/1/0 (from card edge)
○ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
○ACAP bank GTY200/1 (REFCLK1) FMC_SI570_BUF0/1 100 MHz
• Three LPDDR4 interfaces (2x32-bit 4 GB components each)
○XPIO triplet 1 (banks 700, 701, 702)
○XPIO triplet 2 (banks 703, 704, 705)
○XPIO triplet 3 (banks 706, 707, 708)
• PL FMCP HSPC (FMC+) connecvity
○FMCP1 HSPC full LA[00:33] bus
• PL GPIO connecons
○PL UART1 to FTDI
Chapter 1: Introduction
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○PL GPIO DIP switch (4-posion)
○PL GPIO LEDs (four)
○PL GPIO pushbuons (two)
○PL trace connector (J332)
○PL SYSCTLR_GPIO[0:15]
○PL 8A34001_GPIO[0:15]
• 28 GTYP transceivers (7 quads)
○PCIe 16-lane edge connector (16, banks GTYP102 - GTYP105)
○FMCP1 HSPC DP (8, banks GTYP200, GTYP201)
○Not used (4, bank GTYP106)
• 20 PL GTM transceivers (5 quads)
○QSFPDD1 (8, banks GTM204, GTM205)
○QSFPDD2 (8, banks GTM202, GTM203)
○User SMA connectors (1, bank GTM206)
• PCI Express endpoint connecvity
○16-lane (banks GTY102 - GTY105)
• PS PMC MIO connecvity
○PS MIO[0:12]: boot conguraon QSPI
- DC QSPI support
○PS MIO[13:25]: USB2.0
○PS MIO[26:36, 51]: SD1 I/F
○PS MIO[37]: ZU4_TRIGGER
○PS MIO[38]: PCIe_PWRBRK
○PS MIO[39:41]: SYSMON_I2C
○PS MIO[42:43]: UART0 to FTDI
○PS MIO[44:47]: I2C1, I2C0
○PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
○PS MIO[49] and LPD MIO[13,15:16,20]: power enable
○PS MIO[50] and LPD MIO[18:19]: PCIe status
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○PS LPD MIO [21:22]: oponal fan interface
○LPD MIO[23]: VADJ_FMC power rail
• Security: PSBATT buon baery backup
• SYSMON header
•Operaonal switches (power on/o, PROG_B, boot mode DIP switch)
•Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
○See Power and Status LEDs
• Power management
• System controller (XCZU4EG)
The VPK120 evaluaon board provides a rapid prototyping plaorm using the
XCVP1202-2MSEVSVA2785 device. See the Versal Architecture and Product Data Sheet: Overview
(DS950) for a feature set overview, descripon, and ordering informaon.
Board Specifications
Dimensions
Extended Height PCIe Form-Factor
Height: 7.478 inches (18.994 cm)
Length: 9.50 inches (24.13 cm) (¾ PCIe length)
Thickness: 64.24 mil ±08% (1.632 mm ±10%)
Note: Reserve two adjacent PCIe slots to accommodate fan-sink height.
Note: A 3D model of this board is not available.
See the VPK120 Evaluaon Board website for the XDC lisng and board schemacs.
Environmental
Note: The operang temperature range is not fully tested across the specied temperature range. It is for
general guidelines only. Customers should use the VPK120 evaluaon board for evaluaon purposes only
in a normal lab environment and should not operate beyond room temperature.
•Temperature:
Operang: 0°C to +45°C
Chapter 1: Introduction
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Storage: –25°C to +60°C
•Humidity: 5% to 95% non-condensing
Operating Voltage
+12 VDC
Mechanical
The VPK120 evaluaon board includes a mechanical sener to help ensure success with the
board under normal lab condions and use. While it is recommended to not remove this sener,
it is understood that it might be necessary to remove it for connued evaluaon. This is
especially true when operang in a PCIe chassis.
The mechanical sener screw torque is 4.5 in-lbs. When aaching or removing the mechanical
sener, ensure proper ESD precauons are taken. See Standard ESD Measures for suggesons
on best pracces.
• Removing the Sener
With power and other cabling unplugged, carefully unscrew the nine 4-40 screws in any order.
Care needs to be taken with the cooling soluon as the board is manipulated due to potenal
excessive forces.
•Aaching the Sener
1. With power and other cabling unplugged, carefully align the PCBA stando holes to the
sheet metal tray (sener) standos.
2. Insert two screws in opposite corners of the board/tray combinaon. Loosely ghten the
screws to aid in alignment.
3. Add the remaining seven screws and loosely ghten.
4. In a le to right or right to le paern, ghten all nine screws to 4.5 in-lbs.
Note: The tray will only t one direcon with the QSFP-DD connectors having a cutout below. See Board
Component Descripons for more informaon.
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