AMD XILINX VPK120 User manual

VPK120 Evaluaon Board
User Guide
UG1568 (v1.0) August 9, 2022
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Navigating Content by Design Process.................................................................................... 5
Additional Resources.................................................................................................................. 6
Block Diagram..............................................................................................................................6
Board Features............................................................................................................................ 7
Board Specifications....................................................................................................................9
Chapter 2: Board Setup and Configuration....................................................11
Standard ESD Measures........................................................................................................... 11
Board Component Location.....................................................................................................11
Default Jumper and Switch Settings....................................................................................... 16
Versal ACAP Configuration.......................................................................................................19
Chapter 3: Board Component Descriptions................................................... 21
Overview.....................................................................................................................................21
Component Descriptions......................................................................................................... 21
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 57
Overview.....................................................................................................................................57
Appendix B: Xilinx Design Constraints............................................................. 58
Overview.....................................................................................................................................58
Appendix C: Regulatory and Compliance Information........................... 59
CE Information...........................................................................................................................59
Compliance Markings............................................................................................................... 60
Appendix D: Additional Resources and Legal Notices.............................61
Xilinx Resources.........................................................................................................................61
Documentation Navigator and Design Hubs.........................................................................61
References..................................................................................................................................62
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Revision History.........................................................................................................................63
Please Read: Important Legal Notices................................................................................... 63
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Chapter 1
Introduction
Overview
The VPK120 evaluaon board features the Xilinx® Versal® ACAP XCVP1202 device. The
VPK120 board enables the demonstraon, evaluaon, and development of the applicaons listed
here, as well as other customer applicaons. Many features found on the VPK120 board are
subsets of exisng Versal ACAP boards (e.g., the VCK190 and VMK180 boards).
• Fiber opc
•Communicaons
• Data center compute acceleraon
• Aerospace and defense
• Test and measurement
The VPK120 evaluaon board is equipped with many of the common board-level features
needed for design development, including:
• QSFP-DD opcal transceiver support
• LPDDR4 component memory
• USB
• Ethernet networking interface
• One FMC+ expansion port
• PCIe®
Models of Boards
The following table lists the models for the VPK120 evaluaon board. See the VPK120
Evaluaon Board product page for details.
Chapter 1: Introduction
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Table 1: Models of VPK120 Evaluation Boards
Kit Description
EK-VPK120-G Xilinx Versal ACAP VPK120 evaluation kit
EK-VPK120-G-J Xilinx Versal ACAP VPK120 evaluation kit, Japan specific
EK-VPK120-G-ED (encryption
disabled)
Xilinx Versal ACAP VPK120 evaluation kit, China and Russia specific
Users of encryption-disabled kits will not be able to access the following features:
•Secure boot
•Secure key storage/management
•Crypto HW acceleration (PS and APU crypto accelerators)
•Encrypted bitstream loading
•Encrypted BOOT.BIN partitions
•PUF operation
•High-speed crypto (HSC)
Versal ACAP Kit Numbering
The Versal ACAP kit numbering is illustrated in the following gure.
Figure 1: Kit Numbering
EK - VP
Kit
Type
K 120 - G - J
ROHS
Indicator
Regional
Identifier
Silicon indicator
K = kit
Ensures there is no
confusion with silicon P/Ns
Options
J – Japan
ED – China/Russia
OEM – OEM kit
Product Number
Options
G – ROHS
Compliant
Family and series
(e.g., Versal ACAP
and Core)
Options
EK – Evaluation Kit
CK – Characterization Kit Examples
VPK120
VCK190
X26155-080422
Navigating Content by Design Process
Xilinx® documentaon is organized around a set of standard design processes to help you nd
relevant content for your current development task. All Versal® ACAP design process Design
Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This
document covers the following design processes:
Chapter 1: Introduction
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•Board System Design: Designing a PCB through schemacs and board layout. Also involves
power, thermal, and signal integrity consideraons. For more informaon, see Versal ACAP
Design Process Documentaon Board System Design.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VPK120 evaluaon board.
Block Diagram
A block diagram of the VPK120 evaluaon board is shown in the following gure.
Figure 2: Evaluation Board Block Diagram
Versal XCVP1202
VSVA2785
GTYP
GTYP
GTM
GTM
GTM
GTM
GTM
XPIO
GTYP
GTYP
GTYP
GTYP
PS/
PMC
2x LPDDR4
(1x32)
PCIe EP
GEN5 x16
1.8V
GPIO
3.3V
QSFP
Ctrl
FMC+
2x LPDDR4
(1x32)
USB 2.0
ULPI
SD 3.0
UART/I2C
PCIe Control
GEM
2x LPDDR4
(1x32)
EMIO
Mictor
GTYP
1588 CLK SMAs
QSFP-DD
QSFP-DD
1588 SMA
SysC
GPIO
2x QSPI
Lvl
Shftrs
Lvl
Shftrs
X26002-021822
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Board Features
The VPK120 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XCVP1202, VSVA2785 package
• Form factor: extended height PCIe®, double-slot (heatsink clearance)
• Onboard conguraon from:
○USB-to-JTAG bridge
○JTAG pod 2 mm 2x7 at cable connector
○microSD card (PS MIO I/F)
○Quad SPI (QSPI)/eMMC (system controller I/F)
○Dual QSPI
• Clocks
○ACAP bank 702/5/8 Si570 LPDDR4_CLK1/2/3 (DIMM) 200 MHz
○ACAP bank 503 Si570 REF_CLK 33.3333 MHz
○ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
○IEEE-1588 eCPRI 8A34001 clocks (various)
○ACAP bank 503 RTC Xtal 32.768 kHz
○ACAP bank GTY102/3/4/5 (REFCLK0) PCIe_CLK3/2/1/0 (from card edge)
○ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
○ACAP bank GTY200/1 (REFCLK1) FMC_SI570_BUF0/1 100 MHz
• Three LPDDR4 interfaces (2x32-bit 4 GB components each)
○XPIO triplet 1 (banks 700, 701, 702)
○XPIO triplet 2 (banks 703, 704, 705)
○XPIO triplet 3 (banks 706, 707, 708)
• PL FMCP HSPC (FMC+) connecvity
○FMCP1 HSPC full LA[00:33] bus
• PL GPIO connecons
○PL UART1 to FTDI
Chapter 1: Introduction
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○PL GPIO DIP switch (4-posion)
○PL GPIO LEDs (four)
○PL GPIO pushbuons (two)
○PL trace connector (J332)
○PL SYSCTLR_GPIO[0:15]
○PL 8A34001_GPIO[0:15]
• 28 GTYP transceivers (7 quads)
○PCIe 16-lane edge connector (16, banks GTYP102 - GTYP105)
○FMCP1 HSPC DP (8, banks GTYP200, GTYP201)
○Not used (4, bank GTYP106)
• 20 PL GTM transceivers (5 quads)
○QSFPDD1 (8, banks GTM204, GTM205)
○QSFPDD2 (8, banks GTM202, GTM203)
○User SMA connectors (1, bank GTM206)
• PCI Express endpoint connecvity
○16-lane (banks GTY102 - GTY105)
• PS PMC MIO connecvity
○PS MIO[0:12]: boot conguraon QSPI
- DC QSPI support
○PS MIO[13:25]: USB2.0
○PS MIO[26:36, 51]: SD1 I/F
○PS MIO[37]: ZU4_TRIGGER
○PS MIO[38]: PCIe_PWRBRK
○PS MIO[39:41]: SYSMON_I2C
○PS MIO[42:43]: UART0 to FTDI
○PS MIO[44:47]: I2C1, I2C0
○PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
○PS MIO[49] and LPD MIO[13,15:16,20]: power enable
○PS MIO[50] and LPD MIO[18:19]: PCIe status
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○PS LPD MIO [21:22]: oponal fan interface
○LPD MIO[23]: VADJ_FMC power rail
• Security: PSBATT buon baery backup
• SYSMON header
•Operaonal switches (power on/o, PROG_B, boot mode DIP switch)
•Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
○See Power and Status LEDs
• Power management
• System controller (XCZU4EG)
The VPK120 evaluaon board provides a rapid prototyping plaorm using the
XCVP1202-2MSEVSVA2785 device. See the Versal Architecture and Product Data Sheet: Overview
(DS950) for a feature set overview, descripon, and ordering informaon.
Board Specifications
Dimensions
Extended Height PCIe Form-Factor
Height: 7.478 inches (18.994 cm)
Length: 9.50 inches (24.13 cm) (¾ PCIe length)
Thickness: 64.24 mil ±08% (1.632 mm ±10%)
Note: Reserve two adjacent PCIe slots to accommodate fan-sink height.
Note: A 3D model of this board is not available.
See the VPK120 Evaluaon Board website for the XDC lisng and board schemacs.
Environmental
Note: The operang temperature range is not fully tested across the specied temperature range. It is for
general guidelines only. Customers should use the VPK120 evaluaon board for evaluaon purposes only
in a normal lab environment and should not operate beyond room temperature.
•Temperature:
Operang: 0°C to +45°C
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Storage: –25°C to +60°C
•Humidity: 5% to 95% non-condensing
Operating Voltage
+12 VDC
Mechanical
The VPK120 evaluaon board includes a mechanical sener to help ensure success with the
board under normal lab condions and use. While it is recommended to not remove this sener,
it is understood that it might be necessary to remove it for connued evaluaon. This is
especially true when operang in a PCIe chassis.
The mechanical sener screw torque is 4.5 in-lbs. When aaching or removing the mechanical
sener, ensure proper ESD precauons are taken. See Standard ESD Measures for suggesons
on best pracces.
• Removing the Sener
With power and other cabling unplugged, carefully unscrew the nine 4-40 screws in any order.
Care needs to be taken with the cooling soluon as the board is manipulated due to potenal
excessive forces.
•Aaching the Sener
1. With power and other cabling unplugged, carefully align the PCBA stando holes to the
sheet metal tray (sener) standos.
2. Insert two screws in opposite corners of the board/tray combinaon. Loosely ghten the
screws to aid in alignment.
3. Add the remaining seven screws and loosely ghten.
4. In a le to right or right to le paern, ghten all nine screws to 4.5 in-lbs.
Note: The tray will only t one direcon with the QSFP-DD connectors having a cutout below. See Board
Component Descripons for more informaon.
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Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in
total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
•Aach a wrist strap to an unpainted metal surface of your hardware to prevent electrostac
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
stac control. It does not increase or decrease your risk of receiving electric shock when you
are using or working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and
installing or replacing hardware, touch an unpainted metal surface of the system for a
minimum of ve seconds.
• Do not remove the device from the anstac bag unl you are ready to install the device in
the system.
• With the device sll in its anstac bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on
the adapter.
• If you need to lay the device down while it is out of the anstac bag, lay it on the anstac
bag. Before you pick it up again, touch the anstac bag and the metal frame of the system at
the same me.
• Handle the devices carefully to prevent permanent damage.
Board Component Location
The following gure shows the VPK120 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
Chapter 2: Board Setup and Configuration
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IMPORTANT! The following gure is for visual reference only and might not reect the current revision of
the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VPK120 version of interest for such details.
Figure 3: Evaluation Board Component Locations
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
49 47
1
2
3
4
56
7
6
8
11
10
9
12
13
14
15
16
17
18
18
19
20
21
22
23
24
25
26
27
28
29
30 31
32
33
34
38
35
36
37
39
40
41 42
43
44
45
48
46
54
50
51
52
53
55
X26014-010522
Board Component Descriptions
The following table idenes the components and references the respecve schemac
(038-05072-01) page numbers.
Chapter 2: Board Setup and Configuration
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CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the VPK120 board power
connector J16. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin
connector into J16 damages the VPK120 board and voids the board warranty.
Table 2: Board Component Locations
Callout
No. Ref. Des. Feature Notes Schematic Page
1 U1 Versal® ACAP XCVP1202-2MSEVSVA2785
The heatsink is not shown in Figure 31
3-23
2 U25, U26 LPDDR4 16 GBIT comp.
memory (B700-B702 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
3,27,28
3 U150, U151 LPDDR4 16 GBIT comp.
memory (B703-B705 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
4,29,30
4 U246, U247 LPDDR4 16 GBIT comp.
memory (B706-B708 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
5,31,32
5 J11 SYSMON header Sullins PBC06DAAN
Conn. hdr. vert. 12 pos. 2x6 2.54 mm pitch
12
6 J36 ACAP JTAG 2 mm 2x7 flat-cable
connector
Molex 0878321420
Conn. hdr. male vert. 14 pos 2x7 2 mm
48
7 J332 Mictor-38 Arm® trace
connector
TE connectivity AMP connectors
2-5767004-2
Conn. hdr. MICTOR 38 pos. 2x19 0.635 mm
26
8 J310 8A34001 I2C 2 mm 2x9 flat-
cable connector
Molex 0878321820
Conn. hdr. male vert. 18 pos. 2x9 2 mm
90
9 J344 USB-UART bridge, USB micro
type-A connector (USB 2.0)
Hirose ZX62D-AB-5P8(30)
Micro USB 2.0 type-AB
25
10 J308, U99 USB 2.0 type-A connector
USB ULPI transceiver
Wurth 629104190121, USB 2.0 type-A
Microchip USB3320C USB 2.0 Xcvr
41
11 J302 Versal ACAP SD 3.0 level
translator circuit, SD card
socket
Molex 5025700893
Micro SD card cage
39
12 U33, U35 I2C bus switches Texas Instruments TCA9548APWR
IC switch bus 1-In 8-Outs I2C 400 kHz
Bottom of board
43
13 U233 I2C bus expander Texas Instruments TCA6416APWR
IC exp. GPIO 16-bit I2C 400 kHz
Bottom of board
50
14 J1, J2 QSFP-DD 112G connector Molex 2147334000
QSFP-DD 112G connector and cage
45
15 P3 PCIe® endpoint 16 lane edge
connector
44
16 J307 GEM0 SGMII Ethernet PHY,
0x01, RJ45 w/mag
Halo HFJ11-1G01E-L12RL
RJ-45 Gigabit connector
40
17 J51 FMCP1 Samtec ASP-184329-01
560 pos. connector 14x40 1.27 mm
34-38
18 Various ACAP power management
system (VCCINT, VCC_SOC)
Infineon regulators 51-53
Chapter 2: Board Setup and Configuration
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Table 2: Board Component Locations (cont'd)
Callout
No. Ref. Des. Feature Notes Schematic Page
19 U160 VCC_PMC/PSFP/VCCO_MIO/
VCCAUX/VCC1V5 regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
55
20 U167 VCCAUX_PMC/LPDMGTYAVCC/
MGTVCCAUX/MGTAVCC
regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
56
21 U175 VCCO_502/UTIL_2V5/
PSLP_CPM5/MGTYVCCAUX
regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
57
22 U259 LPDMGTYAVTT regulator Infineon IR38060MTRPBF
IC REG BUCK ADJ 6A
60
23 U13 VCC_RAM_VCCINT_GT regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
61
24 U185 VADJ_FMC regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
62
25 U187 VCC1V1_LP4 regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
63
26 U189 MGTYAVTT regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
64
27 U261 UTIL_1V8 regulator Infineon IR3889MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
65
28 U190 UTIL_3V3 regulator Infineon IR3889MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
66
29 U191 UTIL_5V0 regulator Infineon IR3889MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
67
30 J325 PMBus 3-pin header Sullins PBC03SAAN
Conn. hdr. vert. 3 pos. 1x3 2.54 mm
43
31 Various Power good LEDs (see Power
and Status LEDs for more
details)
Various; see the Bill of Materials 69
32 J16 Power connector, 2x3, for AC-
DC power adapter
Molex 0039301060
Conn. ddr. RA 6 pos. 2x3 4.2 mm
49
33 JP1 Power connector, 2x4, for ATX
PCIe power
Astron 6652208-T0003T-H
Conn. hdr. male RA 8 pos. 2x4 4.2 mm
49
34 J233 Fan header (keyed 4-pin) Molex 0470533000
Keyed fan header 4 pos. 0.100" vert.
49
35 U205, U249 FMC clock generation and
buffering
SI570BAB002038DGR, 8P34S1102NLGI
Bottom of board
46
36 U258 PCIe 1:4 buffer, 100 MHz, 3.3V
LVDS
Skyworks/Silicon Labs SI53306-B-GMR
IC buffer clk. 1 to 4 3.3V
47
37 U11, U12 ACAP U1 QSPI Micron MT25QU01GBBB8E12-0SIT
IC flash NOR SPI 1 Gb
33
38 U32 ACAP U1 REF CLK, 33.33 MHz,
1.8V CMOS, 0x5D
Skyworks/Silicon Labs 570JAC000900DGR
Osc. XO 10-280 MHz
Bottom of board
42
Chapter 2: Board Setup and Configuration
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Table 2: Board Component Locations (cont'd)
Callout
No. Ref. Des. Feature Notes Schematic Page
39 U248 LPDDR4 CLK1, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
3
40 U3 LPDDR4 CLK2, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
4
41 U4 LPDDR4 CLK3, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
5
42 J334, J335, J336,
J337
ACAP GTM female vertical 34
GHz SMT 3.5 mm screw
connector
Carlisle TMB-V5F2-3L1 Conn. 11
43 DS1 Done LED (Active High-Z and
pulled High)
Lumex SML-LX0603GW-TR
LED green
14
44 DS2 Error out LED (Active High-Z
and pulled High)
Lumex SML-LX0603IW-TR
LED red
14
45 DS3, DS4, DS5,
DS6
User LEDS Lumex SML-LX0603GW-TR
LED green
48
46 U257 IEEE-1588 eCPRI input clock
multiplexor
Skyworks/Silicon Labs SI53340-B-GM
IC buffer 2:4 LVDS MUX
Bottom of board
92
47 U219 IEEE-1588 eCPRI CLK, various,
3.3V, 0x58
IDT 8A34001E-000AJG8
IC synch. man. unit 8-Ch 24 LVCMOS
Bottom of board
90-92
48 J328, J329, J338 IEEE-1588 eCPRI 8A34001 CLK
in SMA
Amphenol 132134-15
Conn. rcpt. SMA vert. 50R 12.4 GHz
90
49 J330, J331, J339 IEEE-1588 eCPRI 8A34001 CLK
out SMA
Amphenol 132134-15
Conn. rcpt. SMA vert. 50R 12.4 GHz
90
50 U125 XCZU4EG system controller Xilinx® XCZU4EG-2SFVC784E
FPGA MPSoC Zynq UltraScale+
71-79
51 U142 SYSCTLR clocks 33.33 MHz & 26
MHz I2C 0x6A
Skyworks/Silicon Labs Si5332FD10259-GM1
Low jitter clock generator with 6 outputs
87
52 U132 System controller LPDDR4 16
GBIT comp. memory
Micron MT53D512M32D2DS-046 WT:D
IC SDRAM LPDDR4 16 Gb 512Mx32 2133
MHz
83
53 J349 System controller SGMII
Ethernet, RJ45 w/magnetics
Halo HFJ11-1G01E-L12RL
RJ-45 Gigabit connector
81
54 J7, U19 System controller USB 3.0 type-
B connector , USB ULPI
transceiver
Wurth 692622030100, USB 3.0 type-B
Microchip USB3320C USB 2.0 Xcvr
86
55 DS34 System controller Done LED
(active-High)
Lumex SML-LX0603GW-TR
LED green
75
Notes:
1. The VPK120 evaluation board includes a heatsink with a thermal resistance of 0.38°C/W.
Chapter 2: Board Setup and Configuration
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Default Jumper and Switch Settings
The following gure shows the VPK120 board jumper header and switch locaons. Each
numbered component shown in the gure is keyed to the applicable table in this secon. Both
tables reference the respecve schemac page numbers.
Figure 4: Board Jumper Header and Switch Locations
1
2
3
4
5
6
8
7
9
10
11
12
13
15
17
18
20
16
16
19 14
22
21
23
X26013-042222
Jumpers
The following table lists the default jumper sengs.
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Table 3: Default Jumper Settings
Callout
Number Ref. Des. Function Default Schematic Page
1 J12 SYSMON VREFP SEL
1-2: External VREF
2-3: Disable external VREF
1-2 12
2 J26 POR_B supervisor SENSE input
1-2: VCCO_MIO ramp-up sense (1.8V)
2-3: VCCAUX_PMC ramp-up sense (1.5V)
1-2 15
3 J326 POR_B enable header
1-2: SYSCTLR can drive POR_B
3-4: PC4 can drive POR_B
5-6: FTDI can drive POR_B
Open: POR_B source not connected
1-2, 3-4 jumpered
5-6 open
15
4 J34 VCC fuse enable
1-2: Fuse enabled
2-3: Fuse disabled
2-3 16
5 J37 JTAG source enable
1-2: JTAG sources disabled
2-3: JTAG sources enabled
2-3 24
6 J300 USB shield GND
1-2: USB connector DC grounded
2-3: USB connector no DC grounded
1-2 41
7 J60 PCIe PRSNT_B WIDTH SEL
1-2: x1
3-4: x4
5-6: x8
7-8: x16
1-2, 3-4, 5-6, 7-8 44
8 J301 SD REF
1-2: 3.3V REF
2-3: GND REF
1-2 39
9 J203 SYSCTLR POR_B supervisor enable
1-2: SYSCTLR POR_B supervisor enabled
Open: SYSCTLR POR_B supervisor disabled
1-2 75
10 J11 SYSMON header
Open: header for test access
Open 12
11 J347 Fan type
1-2: System controller PWM
2-3: Versal ACAP MIO PWM
2-3 49
11 J348 TACH type
1-2: System controller TACH
2-3: Versal ACAP MIO TACH
2-3 49
12 J345 LPDMGTYAVTT enable select
Installed: Versal ACAP control
Not installed: enabled by UTIL_5V0_PGOOD
Open 68
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Switches
The following table lists the default switch sengs.
Table 4: Default Switch Settings
Callout
Number Ref. Des. Function Default Schematic Page
13 SW1 U1 mode 4-Pole DIP switch
Switch OFF = 1 = high; ON = 0 = low
Mode = SW1[1:4] = Mode[0:3]
SD = ON,OFF,OFF,OFF = 0111
QSPI32 = ON,OFF,ON,ON = 0100
JTAG = ON,ON,ON,ON = 0000
ON, OFF, OFF, OFF 14
14 SW2 VPK120 power-on reset (POR_B) Open 15
15 SW3 SYSCTLR JTAG source selection
Switch OFF = 1 = high; ON = 0 = low
SYSCTLR JTAG SOURCE SEL = SW3[1:2] = SEL[0:1]
PL JTAG = ON,ON = 00
FTDI JTAG = OFF,ON = 10
Trace Mictor38 JTAG = ON,OFF = 01
PCIe JTAG = OFF,OFF = 11
OFF, ON 24
16 SW4, SW5 User pushbutton inputs
Note: Pushbutton switch default = open = logic low
(not pressed).
Open 48
17 SW6 GPIO DIP
Switch OFF = 0 = low; ON = 1 = high
OFF, OFF, OFF, OFF 48
18 SW11 SYSCTLR mode 4-Pole DIP switch
Switch OFF = 1 = high; ON = 0 = low
Mode = SW1[1:4] = Mode[0:3]
QSPI32 = ON,OFF,ON,ON = 0100
eMMC = ON,OFF,OFF,ON = 0110
JTAG = ON,ON,ON,ON = 0000
ON, OFF, ON, ON 75
19 SW12 System controller power-on reset (SYSCTL_POR_B) Open 75
20 SW13 Main power OFF 49
21 SW14 User USB reset Open 41
22 SW15 User GEM reset Open 40
23 SW16 System controller FWUEN pushbutton
(SYSCTLR_MIO12_FWUEN_C2M_B)
Open 74
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Versal ACAP Configuration
The Versal XCVP1202 ACAP boot process is described in the “Plaorm Boot, Control, and
Status” secon of the Versal ACAP Technical Reference Manual (AM011). The VPK120 board
supports a subset of the modes documented in the technical reference manual via onboard boot
opons. The mode DIP switch SW1 conguraon opon sengs are listed in the following table.
Table 5: Mode Switch SW1 Configuration Option Settings
Boot Mode Mode Pins [0:3]2Mode SW1 [1:4]2
JTAG 00001,3ON, ON, ON, ON
QSPI32 0100 ON, OFF, ON, ON
SD1 (SD 3.0) 0111 ON, OFF, OFF, OFF
Notes:
1. Default switch setting.
2. Mode DIP SW1 poles [4:1] correspond to U1 XCVP1202 MODE[3:0].
3. Mode DIP SW1 individual switches ON=LOW (p/d to GND)=0, OFF=HIGH (p/u to VCCO)=1.
JTAG
The Vivado®, Xilinx SDK, or third-party tools can establish a JTAG connecon to the Versal
ACAP in the two ways described in this secon.
• FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 2.0 type-A micro
connector (J344), which requires:
○Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Conguraon Opon
Sengs" table in Versal ACAP Conguraon.
○Set 2-pole DIP SW3[1:2] set to 01 (ON, OFF) for JTAG MUX channel 2 FT4232 U20
bridge.
○On the 3-pin JTAG MUX, enable header J37 to enable the JTAG MUX. Move the 2-pin
jumper to be installed on pins 2-3. See Default Jumper and Switch Sengs for defaults and
Board Component Locaon for locaon.
○Power-cycle the VPK120 evaluaon board or press the power-on reset (POR) pushbuon
(SW2). SW2 is near the mode pin dip switch in the gure in Board Component Locaon).
• JTAG pod at cable connector J36 (2 mm 2x7 shrouded/keyed), which requires:
○Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Conguraon Opon
Sengs" table in Versal ACAP Conguraon.
○On the 3-pin JTAG MUX, enable header J37 to inhibit the JTAG MUX. Move the 2-pin
jumper to be installed on pins 1-2 for high-z mode. See Default Jumper and Switch Sengs
for defaults and Board Component Locaon for locaon.
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○2-pole DIP SW3[1:2] seng is XX as the MUX is inhibited/turned o.
○In this mode, the FT4232 device (U20) UART funconality connues to be available.
○Power-cycle the VPK120 board or press the power-on reset pushbuon (SW2). SW2 is
near the mode pin dip switch in the gure in Board Component Locaon).
QSPI32
This boot mode is supported onboard and is wired to XCVP1202 U1 bank 500 PMC_MIO[0:12]
pins. The supported QSPI conguraon is dual-parallel x8. To boot from QSPI, follow these steps.
1. Store a valid XCVP1202 ACAP boot image le in the QSPI.
2. Set boot mode SW1 for QSPI32 as indicated in the "Mode Switch SW1 Conguraon Opon
Sengs" table in Versal ACAP Conguraon.
3. Power-cycle the VPK120 board or press the POR pushbuon SW2. SW2 is near the mode
pin dip switch in the gure in Board Component Locaon.
SD1_3.0
To boot from a SD card installed in microSD card socket J302, follow these steps.
1. Store a valid XCVP1202 ACAP boot image le on a microSD card. Plug the SD card into the
VPK120 evaluaon board SD socket J302 connected to the XCVP1202 U1 bank 501 MIO
SD interface.
2. Set boot MODE SW1 for SD1_3.0 as indicated in the table in Versal ACAP Conguraon.
3. Power-cycle the VPK120 board or press the POR pushbuon SW2. SW2 is near the mode
pin dip switch in the gure in Board Component Locaon.
Chapter 2: Board Setup and Configuration
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