Analog Devices ADSP-BF53x Blackfin Service manual

a
ADSP-BF53x/BF56x Blackfin®Processor
Programming Reference
Revision 1.2, February 2007
Part Number
82-000556-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2007 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-BF53x/BF56x Blackfin Processor Programming Reference iii
CONTENTS
PREFACE
Purpose of This Manual ................................................................ xxv
Intended Audience ........................................................................ xxv
Manual Contents ......................................................................... xxvi
What’s New in This Manual ........................................................ xxvii
Technical or Customer Support .................................................. xxviii
Supported Processors .................................................................... xxix
Product Information .................................................................... xxix
MyAnalog.com ........................................................................ xxx
Processor Product Information ................................................. xxx
Related Documents ................................................................ xxxi
Online Technical Documentation .......................................... xxxii
Accessing Documentation From VisualDSP++ .................. xxxiii
Accessing Documentation From Windows ........................ xxxiii
Accessing Documentation From the Web .......................... xxxiv

Contents
iv ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Printed Manuals .................................................................... xxxiv
VisualDSP++ Documentation Set ...................................... xxxv
Hardware Tools Manuals ................................................... xxxv
Processor Manuals ............................................................. xxxv
Data Sheets ....................................................................... xxxv
Conventions ............................................................................... xxxvi
INTRODUCTION
Core Architecture ......................................................................... 1-1
Memory Architecture .................................................................... 1-4
Internal Memory ..................................................................... 1-5
External Memory .................................................................... 1-6
I/O Memory Space .................................................................. 1-6
Event Handling ............................................................................ 1-6
Core Event Controller (CEC) .................................................. 1-8
System Interrupt Controller (SIC) ........................................... 1-8
Syntax Conventions ...................................................................... 1-8
Case Sensitivity ....................................................................... 1-8
Free Format ............................................................................ 1-9
Instruction Delimiting ............................................................ 1-9
Comments ............................................................................ 1-10
Notation Conventions ................................................................ 1-10
Behavior Conventions ................................................................. 1-12

ADSP-BF53x/BF56x Blackfin Processor Programming Reference v
Contents
Glossary ...................................................................................... 1-13
Register Names ...................................................................... 1-13
Functional Units ................................................................... 1-14
Arithmetic Status Flags .......................................................... 1-15
Fractional Convention ........................................................... 1-16
Saturation ............................................................................. 1-17
Rounding and Truncating ...................................................... 1-19
Automatic Circular Addressing .............................................. 1-21
COMPUTATIONAL UNITS
Using Data Formats ...................................................................... 2-4
Binary String ........................................................................... 2-4
Unsigned ................................................................................. 2-4
Signed Numbers: Two’s-Complement ....................................... 2-5
Fractional Representation: 1.15 ................................................ 2-5
Register Files ................................................................................. 2-6
Data Register File .................................................................... 2-7
Accumulator Registers ............................................................. 2-8
Register File Instruction Summary ........................................... 2-9
Data Types .................................................................................. 2-11
Endianess .............................................................................. 2-13
ALU Data Types .................................................................... 2-14
Multiplier Data Types ............................................................ 2-14
Shifter Data Types ................................................................. 2-15
Arithmetic Formats Summary ................................................ 2-16

Contents
vi ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Using Multiplier Integer and Fractional Formats .................... 2-17
Rounding Multiplier Results ................................................. 2-19
Unbiased Rounding .......................................................... 2-20
Biased Rounding .............................................................. 2-22
Truncation ....................................................................... 2-23
Special Rounding Instructions ............................................... 2-24
Using Computational Status ....................................................... 2-24
ASTAT Register .......................................................................... 2-25
Arithmetic Logic Unit (ALU) ...................................................... 2-26
ALU Operations ................................................................... 2-26
Single 16-Bit Operations .................................................. 2-27
Dual 16-Bit Operations .................................................... 2-27
Quad 16-Bit Operations ................................................... 2-28
Single 32-Bit Operations .................................................. 2-29
Dual 32-Bit Operations .................................................... 2-29
ALU Instruction Summary .................................................... 2-30
ALU Division Support Features ............................................. 2-34
Special SIMD Video ALU Operations ................................... 2-35
Multiply Accumulators (Multipliers) ........................................... 2-35
Multiplier Operation ............................................................. 2-36
Placing Multiplier Results in Multiplier
Accumulator Registers .................................................... 2-37
Rounding or Saturating Multiplier Results ........................ 2-37
Saturating Multiplier Results on Overflow ............................. 2-38

ADSP-BF53x/BF56x Blackfin Processor Programming Reference vii
Contents
Multiplier Instruction Summary ............................................ 2-38
Multiplier Instruction Options .......................................... 2-40
Multiplier Data Flow Details ................................................. 2-42
Multiply Without Accumulate ............................................... 2-44
Special 32-Bit Integer MAC Instruction ................................. 2-46
Dual MAC Operations .......................................................... 2-47
Barrel Shifter (Shifter) ................................................................. 2-48
Shifter Operations ................................................................. 2-48
Two-Operand Shifts .......................................................... 2-49
Immediate Shifts ........................................................... 2-49
Register Shifts ............................................................... 2-50
Three-Operand Shifts ....................................................... 2-50
Immediate Shifts ........................................................... 2-50
Register Shifts ............................................................... 2-51
Bit Test, Set, Clear, Toggle ................................................ 2-52
Field Extract and Field Deposit ......................................... 2-52
Shifter Instruction Summary .................................................. 2-53
OPERATING MODES AND STATES
User Mode .................................................................................... 3-3
Protected Resources and Instructions ....................................... 3-4
Protected Memory ................................................................... 3-5
Entering User Mode ................................................................ 3-5
Example Code to Enter User Mode Upon Reset ................... 3-5
Return Instructions That Invoke User Mode ........................ 3-5

Contents
viii ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Supervisor Mode .......................................................................... 3-7
Non-OS Environments ........................................................... 3-7
Example Code for Supervisor Mode Coming
Out of Reset .................................................................... 3-8
Emulation Mode .......................................................................... 3-9
Idle State ...................................................................................... 3-9
Example Code for Transition to Idle State .............................. 3-10
Reset State .................................................................................. 3-10
System Reset and Powerup .......................................................... 3-12
Hardware Reset ..................................................................... 3-13
SYSCR Register .................................................................... 3-14
Software Resets and Watchdog Timer .................................... 3-14
SWRST Register ................................................................... 3-15
Core-Only Software Reset ..................................................... 3-16
Core and System Reset .......................................................... 3-16
PROGRAM SEQUENCER
Introduction ................................................................................. 4-1
Sequencer Related Registers ..................................................... 4-5
Instruction Pipeline ...................................................................... 4-7
Branches .................................................................................... 4-10
Direct Short and Long Jumps ................................................ 4-11
Direct Call ............................................................................ 4-12
Indirect Branch and Call ....................................................... 4-12
PC-Relative Indirect Branch and Call .................................... 4-13

ADSP-BF53x/BF56x Blackfin Processor Programming Reference ix
Contents
Subroutines ........................................................................... 4-13
Stack Variables and Parameter Passing ................................ 4-15
Condition Code Flag ............................................................. 4-18
Conditional Branches ........................................................ 4-19
Conditional Register Move ................................................ 4-20
Branch Prediction .................................................................. 4-20
Hardware Loops .......................................................................... 4-21
Two-Dimensional Loops ........................................................ 4-24
Loop Unrolling ..................................................................... 4-26
Saving and Resuming Loops .................................................. 4-27
Example Code for Using Hardware Loops in an ISR .......... 4-28
Events and Interrupts .................................................................. 4-29
System Interrupt Processing ................................................... 4-31
System Peripheral Interrupts .................................................. 4-33
SIC_IWR Register ................................................................. 4-34
SIC_ISR Register .................................................................. 4-35
SIC_IMASK Register ............................................................ 4-36
System Interrupt Assignment Registers (SIC_IARx) ................ 4-37
Core Event Controller Registers ............................................. 4-38
IMASK Register ................................................................ 4-38
ILAT Register ................................................................... 4-39
IPEND Register ................................................................ 4-40
Event Vector Table ................................................................ 4-41

Contents
x ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Return Registers and Instructions .......................................... 4-42
Executing RTX, RTN, or RTE in a Lower
Priority Event ................................................................ 4-45
Emulation Interrupt .............................................................. 4-45
Reset Interrupt ...................................................................... 4-46
NMI (Nonmaskable Interrupt) .............................................. 4-46
Exceptions ............................................................................ 4-47
Hardware Error Interrupt ...................................................... 4-47
Core Timer Interrupt ............................................................ 4-47
General-purpose Interrupts (IVG7-IVG15) ............................ 4-47
Interrupt Processing .................................................................... 4-48
Global Enabling/Disabling of Interrupts ................................ 4-48
Servicing Interrupts ............................................................... 4-48
Software Interrupts ............................................................... 4-50
Nesting of Interrupts ............................................................. 4-51
Non-nested Interrupts ...................................................... 4-51
Nested Interrupts ............................................................. 4-51
Example Prolog Code for Nested Interrupt
Service Routine .......................................................... 4-53
Example Epilog Code for Nested Interrupt
Service Routine .......................................................... 4-54
Logging of Nested Interrupt Requests ........................... 4-55
Self-Nesting of Core Interrupts ......................................... 4-55