Analog Devices LTC2949 User manual

LTC2949
1
Rev A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Current, Voltage, and Charge Monitor for
High Voltage Battery Packs
The LTC
®
2949 is a high precision current, voltage, tem-
perature,chargeandenergymeterforelectricaland hybrid
vehicles and other isolated current sense applications. It
infers charge and energy flowing in and out of the battery
pack by monitoring simultaneously the voltage drop over
up to two sense resistors and the battery pack voltage.
Low offset ΔΣADCs ensure accurate measurement of
voltage and current with insignificant power loss. Con-
tinuous integration of current and power ensures lossless
tracking of charge and energy delivered or received by
the battery pack.
The built-in serial interface can be configured to support
isolated isoSPI communication to the host or as SPI
interface.
The LTC2949 features 12 internally buffered high imped-
ance inputs (V1 to V12) for measuring voltages from
external sensors or resistor dividers allowing to measure
temperatures, HV-Link voltages, chassis isolation and
supervise contactor states. LTC2949 has up to five pro-
grammable digital outputs which can be set to ground,
supply or toggling at 400kHz.
Programmable threshold and tracking registers reduce
digital traffic to the host.
Electric Vehicle Battery Meter
APPLICATIONS
n Electric and Hybrid Vehicles
n Isolated Current Sensing
n Backup Battery Systems
n High Power Portable Equipment
All registered trademarks and trademarks are the property of their respective owners.
n Measures Battery Stack Voltage, Current and Power
n Indicates Accumulated Battery Charge and Energy
n 20-Bit Current Measurement with <1μV Offset
n Built-In Isolated isoSPI™ or SPI Interface
n LTC68xx/ADBMS68xx Compatible, Supports
Synchronous Measurements with Cell Monitors
n Up to 12 Buffered Voltage Measurement Inputs
n Up to 5 GPIOs, Configurable to Drive Ground, Supply
or Toggling at 400kHz
n High or Low Side Current Sense
n 0.3% Current and Voltage Accuracy
n 1% Energy and Charge Accuracy
n True Average ADCs
n I2C EEPROM Interface to Store Board Calibration Factors
n Threshold Registers for all Measured Quantities
n Engineered for ISO26262 Compliant Systems
n Open Wire Detection on Input Pins
n Available in 48-Lead LQFP Package
n AEC-Q100 Qualified for Automotive Applications
2949 TA01
6.5M
30k
50µΩ
6.5M
30k
100k
3.3M
3.3M
22k
22k
6.5M
6.5M
100k
1µF
STD4NK100Z
30k
MASTER
GND
LTC2949
BATP
I1P
I2P
V1
isoSPI
HV
LINK+
HV
LINK–
VREF
V5
V3
BATM
I1M
I2M
GND
V2
SPI
CHASSIS-GND
GPIO1
HV
BAT–
HV
BAT+
800V
CELL
MONITORS
V4
isoSPI A
LTC681x
isoSPI B
isoSPI A
LTC681x
isoSPI B
STACK
VOLTAGE
TEMPERATURE
LINK VOLTAGE
LINK VOLTAGE
LTC6820
AVCC
DVCC
CURRENT
CHARGE
POWER
ENERGY
SPI
isoSPI
GND
ISOLATION
RESISTANCE
ISOLATED COMMUNICATION
LT830x
• • •

LTC2949
2
Rev A
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TABLE OF CONTENTS
Features............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings..................................................................................................... 3
Order Information................................................................................................................. 3
Pin Configuration ................................................................................................................. 3
Electrical Characteristics ........................................................................................................ 4
Typical Performance Characteristics .........................................................................................10
Pin Functions .....................................................................................................................11
Pin Functions .....................................................................................................................12
Block Diagram....................................................................................................................13
Operation..........................................................................................................................14
Overview............................................................................................................................................................... 14
Modes of Operation .............................................................................................................................................. 15
Data Acquisition Channels .................................................................................................................................... 16
Power Measurement............................................................................................................................................. 19
Charge, Energy and Time...................................................................................................................................... 20
Overcurrent Comparators ..................................................................................................................................... 21
SERIAL INTERFACES ............................................................................................................22
Serial Interfaces Overview .................................................................................................................................... 22
4-Wire Serial Peripheral Interface (SPI) Physical Layer........................................................................................ 22
2-Wire Isolated Interface (isoSPI) Physical Layer................................................................................................. 23
Data Link Layer..................................................................................................................................................... 28
Network Layer....................................................................................................................................................... 28
REGISTER MAP...................................................................................................................41
REGISTER Description ..........................................................................................................42
MEMORY MAP AND Paging Mechanism............................................................................................................... 42
Register Map PAGE0............................................................................................................................................. 44
Register Map PAGE1 ............................................................................................................................................ 62
Application Information.........................................................................................................68
Temperature Measurement .................................................................................................................................. 68
Sense Resistor Temperature Compensation ......................................................................................................... 69
Current and Voltage Input Filtering ....................................................................................................................... 74
Powering the LTC2949 ......................................................................................................................................... 75
Package Description ............................................................................................................78
Revision History .................................................................................................................79
Typical Application ..............................................................................................................80
Related Parts .....................................................................................................................80

LTC2949
3
Rev A
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
V1
V2
V3
V4
V5
DNC
V6
V7
V8
V9
V10
V11
13 14 15 16 17 18 19 20 21 22 23 24
V12
SCL
SDA
BYP1
DGND
AGND
AVCC
DVCC
DNC DNC DNC DNC
48 47 46 45 44 43 42 41 40 39 38 37
VBATP VBATM DNC I1P CF1P CF1M I1M I2M CF2M CF2P I2P DNC
DNC
VREF
CLKO
CLKI
DNC
DNC
CSB (IM)
SCK (IP)
SDO (IBIAS
)
SDI (ICMP)
IOVCC
BYP2
TOP VIEW
LXE PACKAGE
48-LEAD (7mm ×7mm) PLASTIC LQFP
DNC: DO NOT CONNECT
TJMAX = 150°C, θJA = 20.46°C/W, θJC = 3.68°C/W
EXPOSED PAD (PIN 49), CONNECT TO AGND
49
GND
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
TRAY (250PC) TAPE AND REEL (2000PC) PART MARKING* PACKAGE DESCRIPTION MSL RATING TEMPERATURE RANGE
LTC2949ILXE#3ZZPBF LTC2949ILXE#3ZZTRPBF LTC2949LXE 48-LEAD PLASTIC eLQFP 3 –40°C to 85°C
LTC2949HLXE#3ZZPBF LTC2949HLXE#3ZZTRPBF LTC2949LXE 48-LEAD PLASTIC eLQFP 3 –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local
Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Supply Pins
AVCC to AGND ........................................ –0.3V to 14.5V
DVCC to DGND........................................ –0.3V to 14.5V
AVCC to DVCC........................................... –0.1V to 0.1V
DGND to AGND......................................... –0.1V to 0.1V
Analog Pins
I1P, I1M, I2P, I2M ......................... –0.3V to VAVCC + 0.3V
I1P to I1M, I2P to I2M ..............................................±1V
VBATP, VBATM ............................. –0.3V to VAVCC + 0.3V
V1-V12......................................... –0.3V to VAVCC + 0.3V
CLKO, DNC.........................................................(Note 3)
Digital Input/Output Pins
IOVCC, CLKI, CSB(IM), SCK(IP)................... –0.3V to 5V
SDI (ICMP), SDO (IBIAS)............................. –0.3V to 5V
SDA, SCL ................................................ –0.3V to 2.75V
Current In/Out of Pins
IP, IM ....................................................................±30mA
SDO (IBIAS) .............................................. –1mA to 9mA
V8-V12 ...................................................................±2mA
VREF (Note 4) .......................................................±2mA
BYP1 (Note 4)......................................... –10mA to 0mA
BYP2 (Note 4)......................................... –10mA to 0mA
Operating Ambient Temperature Range
LTC2949I.................................................–40°C to 85°C
LTC2949H.............................................. –40°C to 125°C
Storage Temperature Range…............... –65°C to 150°C

LTC2949
4
Rev A
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VAVCC Analog Supply Voltage l4.5 14 V
VDVCC Digital Supply Voltage l4.5 14 V
VUVLO Supply Undervoltage Lockout Threshold VAVCC, VDVCC Falling l4.5 V
ICC Average Supply Current into AVCC and DVCC Core State: STANDBY or MEASURE l16 20 mA
Core State: SLEEP 9 15 µA
Core State: SLEEP l150 µA
Additional DVCC Supply Current if isoSPI in
READY/ACTIVE States
Note:ACTIVE State Current Assumes tCLK = 1μs,
(Note 5)
RB1 + RB2 = 2k READY l4.8 5.8 mA
ACTIVE l6.1 7.8 mA
RB1 + RB2 = 20k READY l2.1 3 mA
ACTIVE l2.5 3.5 mA
VBYP1 BYP1 Regulated Output Voltage l2.25 2.5 2.75 V
BYP1 Load Current l–10 0 mA
BYP1 Load Regulation Error ILOAD = –10mA l–15 0 mV
BYP1 Undervoltage Lockout Threshold l2.25 V
VBYP2 BYP2 Regulation Output Voltage l3 3.25 3.6 V
BYP2 Load Current l–10 0 mA
BYP2 Load Regulation Error ILOAD = –10mA l–60 mV
Thermal Shutdown Temperature 170 °C
Current Sense ADC
Resolution (No Missing Codes) Slow Mode Filtered (Note 7) l20 Bit
Slow Mode (Note 7) l18 Bit
Fast Mode (Note 7) l15 Bit
Full-Scale Differential Input Voltage VI1P-VI1M, VI2P-VI2M ±124 mV
VDIFIDifferential Input Voltage Range VI1P-VI1M, VI2P-VI2M l±110 mV
Pin Voltage of I1P, I1M, I2P, I2M l–0.11 VAVCC+0.11 V
Current Sense Quantization Step Slow Mode Filtered 237.5 nV
Slow Mode 950 nV
Fast Mode 7.60371 µV
CFPx Input Leakage Current at CF1P, CF1M, I1P,
I1M, CF2P, CF2M, I2P, I2M Core State = SLEEP/STANDBY l60 nA
Differential Input Current from CF1P to CF1M,
CF2P to CF2M Core State:MEASURE;Pin Voltages: 0V ≤ VCF1P, VCF1M, VI1P, VI1M, VCF2P, VCF2M,
VI2P, VI2M ≤ VAVCC
VDIFI/100kΩ µA
Noise Slow Mode Filtered 160 nVRMS
Slow Mode 320 nVRMS
Fast Mode 3 µVRMS
Gain Error |VDIFI| ≤ 110mV 0.15 %
l0.3 %
Offset Voltage IADCx, IxP, IxM = 0V
VAVCC = VDVCC = 5V
Slow Mode l0 ±1 µV
Fast Mode l0 ±2 µV
Total Unadjusted Error |VDIFI|≥ 25mV l0.3 %
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.

LTC2949
5
Rev A
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Common Mode Rejection at DC l100 dB
Input Sampling Frequency 10.48 MHz
Conversion Time Slow Mode Filtered 400 ms
Slow Mode 100 ms
Fast Mode l0.782 0.8211 ms
Voltage Measurement by Power ADC
Resolution (No Missing Codes) Slow Mode (Note 7) l18 Bit
Fast Mode (Note 7) l15 Bit
VFSVFull-Scale Differential Input Voltage VVBATP – VVBATM ±6.14 V
VDIFVDifferential Input Voltage Range VVBATP – VVBATM l±4.8 V
Pin Voltage of VBATP, VBATM VAVCC ≥ 5V l–0.1 VAVCC+0.1 V
VAVCC < 5V l–0.1 VAVCC-1.5 V
LSBVDifferential Input Voltage Quantization Step Slow Mode 46.875 µV
Fast Mode 375.183 µV
Input Leakage Current Core State: SLEEP/STANDBY l60 nA
Differential Input Resistance Core State: MEASURE; Pin Voltages 0V
≤ VBATP, VBATM ≤ VAVCC
50 MΩ
l20 MΩ
Gain Error l0.3 %
Offset VBATP = VBATM = 0V l0 ±3 LSBV
Voltage Total Unadjusted Error 1V ≤ |VDIFV| ≤ 4.8V l0.4 %
Input Voltage Common Mode Rejection at DC l80 dB
Noise Slow Mode (Note 7) 3 µVRMS
Fast Mode (Note 7) 30 µVRMS
Input Sampling Rate 5.24 MHz
Conversion Time Slow Mode 100 ms
Fast Mode l0.782 0.8211 ms
Power Measurement by Power ADC
Resolution (No Missing Codes) Slow Mode (Note 7) l18 Bit
Fast Mode (Note 7) l11 Bit
FSPFull-Scale Power FSP = VFSV• VFSI/RISENSE/VDIVv±0.76504 [V2/Ω]
LSBPPower Quantization Step LSBP= FSP/217 5.8368 µ[V2/Ω]
POS Power Offset VDIF1= 0 1 LSBP
TUEPPower Total Unadjusted Error 1V ≤ |VDIFV| ≤ 4.8V, 25mV ≤ |VDIFI| ≤
110mV
l0.9 %
RMS Noise Slow Mode;VBATP –VBATM = 4.8V (Note 7) 0.3 LSBP
Slow Mode;VBATP –VBATM = 0V (Note 7) 0.03 LSBP
Input Sampling Frequency 5.24 MHz
Power Modulation Frequency 5.24 MHz
Conversion Time Slow Mode 100 ms
Fast Mode l0.782 0.8211 ms

LTC2949
6
Rev A
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Energy Measurement
TUEEEnergy Total Unadjusted Error 1V ≤ |VDIFV| ≤ 4.8V, 25mV ≤ |VDIFI| ≤
110mV, Ideal External Clock or 4MHz
Crystal
l0.9 %
1V ≤ |VDIFV| ≤ 4.8V, 25mV ≤ |VDIFI| ≤
110mV, Internal Clock
l1.9 %
Charge Measurement
TUECCharge Total Unadjusted Error 1V ≤ |VDIFV| ≤ 4.8V, 25mV ≤ |VDIFI| ≤
110mV, Ideal External Clock or 4MHz
Crystal
l0.4 %
1V ≤ |VDIFV| ≤ 4.8V, 25mV ≤ |VDIFI| ≤
110mV, Internal Clock
l1.4 %
Voltage Measurement by AUXILIARY ADC
Resolution (No Missing Codes) (Note 7) l15 Bit
VFSAUX Full-Scale Differential Input Voltage VVBATP – VVBATM, VMUXP – VMUXN ±6.14 V
VDIFAUX Differential Input Voltage Range VVBATP – VVBATM, VMUXP – VMUXN l±4.8 V
Pin Voltage of VBATP, VBATM, V1 – V12, CF1P,
CF1M, CF2P, CF2M VAVCC ≥ 5V l–0.1 VAVCC+0.1 V
VAVCC < 5V l–0.1 VAVCC–1.5 V
LSBAUX Differential Voltage Quantization Step Slow Mode 375 µV
Fast Mode 375.183 µV
Input Leakage Current l1 60 nA
Differential Input Resistance l40 MΩ
Gain Error |VDIFAUX| ≤ 4.8V l0.3 %
Offset VBATP = VBATM = 0V l0 ±1 LSBV
Total Unadjusted Error 1V ≤ |VDIFV| ≤ 4.8V l0.4 %
Input Voltage Common Mode Rejection at DC l80 dB
Sampling Rate 5.24 MHz
Conversion Time l0.782 0.8211 ms
On-Die Temperature Measurement by AUXILIARY ADC
Resolution (No Missing Codes) (Note 7) l13 Bit
Full-Scale Temperature 819.2 K
ΔTLSB Temperature Quantization Step 0.2 K
Total Unadjusted Error ±3 K
Conversion Time 13.1 ms
Self-Heating 20 K/W
Supply Voltage Measurement by AUXILIARY ADC
Resolution (No Missing Codes) (Note 7) l14 Bit
Full-Scale Differential Input Voltage 18.43 V
A/DVCC Measurement Quantization Step 2.2583 mV
Total Unadjusted Error l2 ±5 %
Conversion Time 6.55 ms
AUX MUX
Signal Range l–0.1 VAVCC+0.1 V

LTC2949
7
Rev A
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Pull-Up Current Source Pin Voltage < VAVCC − 3.0V l–250 –150 µA
Pull-Down Current Source Pin Voltage > 2.5V l200 250 µA
Reference Voltages
VREF Reference Pin Voltage 3 V
VREF Error l±1 %
VREF Temperature Coefficient 7 ppm/K
VREF Long Term Drift 80 ppm/√kHr
VREF Load Regulation Error –0.5mA ≤ ILOAD ≤ 0.5mA l–5 0 mV
VREF2 Internal Redundant Reference Voltage 2.39 V
VREF2 Error l±0.85 %
VREF2 Temperature Coefficient 10 ppm/K
VREF2 Long Term Drift 80 ppm/√kHr
Overcurrent Comparator
Pin Voltages I1P, I1M I2P, I2M l–0.11 VAVCC+0.11 V
Total Unadjusted Error |Vthr| ≤ 103mV l±5 mV
|Vthr| > 103mV l±10 mV
|Vthr| = 310mV l±20 mV
Programmable Deglitch Time Delay Tdegl 20, 80, 320µs lTdegl −10 Tdegl +37 µs
Tdegl 1280µs lTdegl −26 Tdegl +56 µs
Digital Input CLKI
Logic Input Threshold l0.4 2 V
Input Current DC Current l±1 μA
Input Capacitance (Note 7) l10 pF
External Clock Frequency l0.1 25 MHz
General Purpose Outputs GPIOx
Low Level Output Voltage at GPIOx IGPIOx = 0.5mA l0.4 V
High Level Output Voltage at GPIOx IGPIOx = –0.25mA lVDVCC
–0.5 V
GPIOx Toggling Frequency l370 400 430 kHz
SPI Interface DC Specification IOVCC, CSB, SCK, SDI, SDO
VIOVCC SPI Mode IOVCC Operating Voltage l1.8 4.5 V
Pin Voltages CSB, SCK, SDI, SDO lVIOVCC V
Logic Input Threshold (CSB, SCK, SDI) l0.3 •
VIOVCC
0.7 •
VIOVCC
V
DC Input Current (CSB, SCK, SDI) l±1 µA
Input Capacitance (CSB, SCK, SDI) (Note 7) l10 pF
Low Level Output Voltage at SDO VIOVCC ≥ 3.3V, ISDO = 3mA, 1.8V ≤ VIOVCC
≤ 3.3V, ISDO = 1mA
l0.4 V
SPI Timing Requirements (See Figure 7)
tCLK SCK Period (Note 6) l1 μs
t1SDI Setup Time Before SCK Rising Edge l25 ns
t2SDI Hold Time After SCK Rising Edge l25 ns

LTC2949
8
Rev A
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t3SCK Low tCLK = t3+ t4≥ 1μs l200 ns
t4SCK High tCLK = t3+ t4≥ 1μs l200 ns
t5CSB Rising Edge to CSB Falling Edge l0.65 μs
t6SCK Rising Edge to CSB Rising Edge (Note 6) l0.8 μs
t7CSB Falling Edge to SCK Rising Edge (Note 6) l1 μs
t8SCK Falling Edge to SDO Valid (Note 9), VIOVCC ≥ 3.3V l60 ns
(Note 9), VIOVCC < 3.3V l150 ns
isoSPI DC Specifications (See Figure 10)
Voltage at IOVCC to Select isoSPI l0.5 V
VIBIAS Voltage on IBIAS Pin READY/ACTIVE State l1.9 2 2.1 V
IDLE 0 V
IBIsolated Interface Bias Current RBIAS = 2kΩ to 20kΩ l0.1 1 mA
AIB Isolated Interface Current Gain VA≤ 1V, IB= 1mA l18 20 22 mA/mA
IB= 0.1mA l17 20 24.5 mA/mA
VATransmitter Pulse Amplitude VA= |VIP – VIM|l1.4 V
VICMP Threshold-Setting Voltage on ICMP Pin VTCMP = ATCMP • VICMP l0.2 1.5 V
Input Leakage Current on ICMP Pin VICMP = 0V to VBYP2 l±1 µA
Leakage Current on IP and IM Pins IDLE State, VIP or VIM = 0V to VBYP2 l±1 µA
ATCMP Receiver Comparator Threshold Voltage Gain VCM = VBYP2/2 to VBYP2 – 0.2V,
VICMP = 0.2V to 1.5V
l0.4 0.5 0.6 V/V
VCM Receiver Common Mode Bias IP, IM Not Driving VBYP2 –
VICMP/3 –
167mV
V
Receiver Input Resistance Single-Ended to IP, IM l27 35 43 kΩ
isoSPI IDLE/WAKE-UP Specifications (See Figure 3)
VWAKE Differential Wake-Up Voltage tDWELL = 240ns l200 mV
tDWELL Dwell Time at VWAKE Before Wake Detection VWAKE = 200mV l240 ns
tREADY Start-Up Time After Wake Detection l10 µs
tIDLE Idle Timeout Duration l4.3 6.4 8 ms
isoSPI Pulse Timing Specifications (See Figures 10,11)
tFILT(CS) Chip-Select Signal Filter Receiver l70 90 115 ns
tWNDW(CS) Chip-Select Valid Pulse Window Receiver l220 270 330 ns
t1/2PW(D) Data Half-Pulse Width Transmitter l40 50 60 ns
tFILT(D) Data Signal Filter Receiver l10 25 35 ns
tINV(D) Data Pulse Inversion Delay Transmitter l40 55 69 ns
tWNDW(D) Data Valid Pulses Window Receiver l70 90 110 ns
tRTN Data Return Delay l485 625 ns
I2C Interface DC Specification (SCL, SDA)
Logic Input Threshold (SDA) l0.9 1.6 V
DC Input Current (SDA) l±1 μA
Input Capacitance (SDA) (Note 7) l10 pF
Low Level Output Voltage at SDA, SCL I = 0.5mA l0.4 V

LTC2949
9
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C Interface Timing Specification (SCL, SDA)
fSCL(MAX) Maximum SCL Clock Frequency l8 10 kHz
tSCLLO SCL Low Period l80 µs
tSDALO SDA Low Period l80 µs
tBUF(MIN) Bus Free Time Between STOP/START l30 µs
tSU,STA(MIN) Minimum Repeated START Setup Time l30 µs
tHD,STA(MIN) Minimum Hold Time (Repeated) START
Condition
l30 µs
tSU,STO(MIN) Minimum Setup Time for STOP Condition l30 µs
tSU,DAT(MIN) Minimum Data Setup Time Input l30 µs
tHD,DAT(MIN) Minimum Data Hold Time Input l0 ns
tHD,DATO Minimum Data Hold Time Output l30 µs
tOF Data Output Fall Time (Notes 7, 8) l20 + 0.1
• CB
ns
Digital Core Timings (See Figure 3)
tBOOT Core Boot-Up Time from SLEEP or POWER-OFF
to STANDBY AVCC/DVCC Pins at Minimum Operating Voltage
l100 ms
tIDLE_CORE Core STANDBY Cycle Time (Note 10) l17 20 ms
tCONT Core MEASURE Cycle Time (Note 11) l90 100 110 ms
tMLCK,M Memory Lock Request to Acknowledge Time Core Status MEASURE l130 ms
tMLCK,S Memory Lock Request to Acknowledge Time Core Status STANDBY l40 ms
tACKN Time from Core Entering STANDBY to Return to
SLEEP, When Wake-Up is not Confirmed No Write of 0x0 to Reg. WKUPACK, No Write of 0x8 to Reg. OPCTRL
l0.6 1.5 s
Time Base
TUETB TUE Time Base Internal Clock 0.5 %
l1 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect the device
reliability and lifetime.
Note 2: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum values refer to absolute values.
Note 3: Do not apply a voltage or current source to these pins. They must
be unconnected, connected to capacitive loads or connected to a crystal
according to their pin description. Otherwise permanent damage may
occur.
Note 4: Do not apply a voltage source to these pins. Overloading these
pins might disrupt operation.
Note 5: Active supply current (ICC) is dependent on the amount of time
that the output drivers are active on IP and IM. During those times ICC will
increase by the 20 • IBdrive current. For the maximum data rate 1MHz, the
drivers are active approximately 5% of the time.
Note 6: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 7: Guaranteed by design and characterization, not subject to
production test.
Note 8: CB= capacitance of one bus line in pf (10pF < CB< 400pF)
Note 9: These specifications do not include rise time of SDO due to pull up
resistance and load capacitance on SDO pin.
Note 10: Cycle time at which STATUS/FAULTS and VREF registers are
updated.
Note 11: Cycle time at which STATUS/ALERT/FAULTS registers and all
slow channel measurement results are updated after the first update. The
first update after enabling any measurement is typically 50ms delayed.

LTC2949
10
Rev A
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TYPICAL PERFORMANCE CHARACTERISTICS
Current Measurement Gain Error
vs Temperature
Current Measurement Offset
vs Temperature
Current Measurement Offset
Distribution
Current Measurement Noise Filter
Response
Power as Voltage Gain Error vs
Temperature
AUXADC Gain Error vs
Temperature
Auxiliary ADC Measurement
Offset vs Temperature
Time Base Internal Clock TUE vs
Temperature
ADC Conversion Time Error Slow/
Fast vs Temperature
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.20
–0.15
–0.10
–0.05
0.00
0.05
0.10
0.15
0.20
CURRENT MEASUREMENT GAIN ERROR (%)
Gain Error vs Temperature
Current Measurement
2949 G01
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–3
–2
–1
0
1
2
3
CURRENT MEASUREMENT OFFSET (µV)
Offset vs Temperature
Current Measurement
2949 G02
12 Randomly Chosen Demo Boards
OFFSET VOLTAGE (µV)
–1
–0.5
0
0.5
1
0
2
4
6
8
10
12
NUMBER OF DEMO BOARDS
Distribution
Current Measurement Offset
2949 G03
Slow Mode Filtered
Slow Mode
Fast Mode
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
100k
1M
–80
–60
–40
–20
0
NOISE REJECTION (dB)
Noise Filter Response
Current Measurement
2949 G04
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.3
–0.2
–0.1
0.0
0.1
0.2
0.3
VOLTAGE MEASUREMENT GAIN ERROR (%)
vs Temperature
Power as Voltage Gain Error
2949 G05
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.3
–0.2
–0.1
0.0
0.1
0.2
0.3
VOLTAGE MEASUREMENT GAIN ERROR (%)
vs Temperature
AUXADC Gain Error
2949 G06
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–3
–2
–1
0
1
2
3
AUXILIARY ADC MEASUREMENT OFFSET (LSB)
Offset vs Temperature
AUXILIARY ADC MEASUREMENT
2949 G07
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.3
–0.2
–0.1
0.0
0.1
0.2
0.3
TIME BASE INTERNAL CLOCK TUE (%)
TUE vs Temperature
Time Base Internal Clock
2949 G08
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–6
–4
–2
0
2
4
6
ADC CONVERSION TIME SLOW/FAST (%)
Slow/Fast vs Temperature
ADC Conversion Time Error
2949 G09

LTC2949
11
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VREF vs Temperature VREF Load Regulation VREF2 vs Temperature
AVCC/DVCC Supply Current
Standby/Measure vs Temperature
AVCC/DVCC Supply Current vs
Temperature
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.996
2.997
2.998
2.999
3.000
3.001
3.002
3.003
3.004
3.005
3.006
VREF (V)
vs Temperature
VREF
2949 G10
125°C
85°C
25°C
–40°C
V
REF
LOAD CURRENT (mA)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
CHANGE IN V
REF
(mV)
V
REF
Load Regulation
2949 G11
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.375
2.380
2.385
2.390
2.395
2.400
2.405
VREF2 (V)
VREF2 vs Temperature
2949 G12
Standby/Measure, V
AVCC
=V
DVCC
=14V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
5
10
15
20
25
I
CC
(mA)
Standby/Measure vs Temperature
AVCC/DVCC Supply Current
2949 G13
Sleep Mode, V
AVCC
= V
DVCC
= 14V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1
10
100
1k
I
CC
(µA)
vs Temperature
AVCC/DVCC Supply Current
2949 G14
PIN FUNCTIONS
AVCC (Pin 19):Analog Supply Voltage. Bypass this pin to
AGND with a 0.1μF (or greater) capacitor. AVCC operating
range is 4.5V to 14V.
AGND (Pin 18):Analog Ground. Bypass this pin to AVCC
with a 0.1μF (or greater) capacitor.
BYP1 (Pin 16):Internal Supply Voltage. Bypass BYP1 to
DGND with a 1μF capacitor. BYP1 is regulated to 2.5V. Can
supply external circuitry (example EEPROM) with up to
10mA. Overloading might disrupt LTC2949 functionality.
BYP2 (Pin 25): Internal 3.25V Supply Voltage. Bypass
BYP2 to DGND with a 1μF capacitor. Can supply external
circuitry (example SPI isolator ADuM141E or ADuM4154)
with up to 10mA. Overloading might disrupt LTC2949
functionality.
CF1P, CF1M (Pins 44, 43):Filter Capacitor Inputs for the
first current channel. Connect a 1µF capacitor between
CF1P and CF1M for filtering differential noise and fast cur-
rent variations. Connect 0.1µF capacitors between AGND
and the filter pins for damping high frequency common
mode variations.

LTC2949
12
Rev A
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PIN FUNCTIONS
CF2P, CF2M (Pins 39, 40):Filter Capacitor Inputs for the
second current channel. Connect a 1µF capacitor between
CFI2P and CFI2M for filtering differential noise and fast
currentvariations.Connect0.1µFcapacitorsbetweenAGND
and the filter pins for damping high frequency common
mode variations.
CLKI (Pin 33):Clock Input. Connect to ground if internal
clock is used. For improved measurement accuracy, con-
necta4MHz crystalbetweenCLKIand CLKO and matching
capacitors to ground, or drive with an external clock. See
the Timebase Control section.
CLKO (Pin 34):Clock Output. Connect a 4MHz crystal
between CLKO and CLKI if used;leave pin unconnected
otherwise.
CSB/IM (Pin 30):Active Low Chip Select in SPI mode or
Isolated Interface Negative Input/Output in isoSPI mode.
DGND (Pin 17): Digital Ground. Connect to AGND.
DNC (Pins 6, 21, 22, 23, 24, 31, 32, 36, 37, 46):Do
not connect.
DVCC (Pin 20):Supply Voltage. Bypass this pin to DGND
with a 1μF capacitor. Operating range is 4.5V to 14V.
I1P, I1M (Pins 45, 42):Differential Input of I1ADC and
overcurrent comparator 1. Tie to AGND if unused.
I2P, I2M (Pins 38, 41):Differential Input of I2ADC and
overcurrent comparator 2. Tie to AGND if unused.
IOVCC (Pin 26):Serial Interface Configuration and Sup-
ply Pin. Tie pin to DGND for isoSPI communication. Tie
pin to a voltage ≥1.8V and ≤ 4.5V and bypass with 1µF
to DGND for standard SPI communication. In SPI mode
IOVCC supplies the digital input and output circuits of the
serial interface.
SCK/IP (Pin 29):SerialClockInputin SPI mode orIsolated
Interface Positive Input/Output in isoSPI mode.
SCL (Pin 14):I2C Master Clock Open Drain Output. Con-
nect to clock input of EEPROM.
SDA (Pin 15):I2C Data Input And Open Drain Output. Con-
nect to data line of EEPROM. SDA driven low at power up
preventsLTC2949togoautomaticallyintoSLEEPstateand
to execute HW memory BIST. Connect a 4.7k-10k pull-up
resistor from SDA to BYP1 to ensure correct operation of
auto-sleep and memory BIST.
SDI/ICMP (Pin 27):Serial Data Input in SPI mode or Iso-
lated Interface Comparator Voltage Threshold in isoSPI
mode. Tie ICMP to the resistor divider between IBIAS and
DGND to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to 1/2
the voltage on the ICMP pin.
SDO/IBIAS (Pin 28):Open Drain Serial Data Output in SPI
mode or Isolated Interface Current Bias in isoSPI mode.
In SPI mode tie with a pullup resistor to IOVCC. In isoSPI
mode tie IBIAS to DGND through a resistor divider to set
theinterfaceoutputcurrentlevel.WhentheisoSPIinterface
is enabled, the IBIAS pin voltage is regulated to 2V. The
IP/IM output current drive is set to 20 times the current
IB, sourced from the IBIAS pin.
V1, V2, V3, V4, V5, V6, V7 (Pins 1, 2, 3, 4, 5, 7, 8):
Voltage Measurement Inputs. Pins are internally buffered
before being applied to the AUXADC for ensuring high
input impedance (50MΩ) and low leakage. Can be left
floating if unused.
V8-V12/GPIO1-GPIO5 (Pins 9, 10, 11, 12, 13):General
PurposeVoltageIn–andDigitalOutputs.Pinsareinternally
buffered before being applied to the AUXADC for ensuring
high input impedance (50MΩ) and low leakage (<10nA).
Each pin can be switched to DVCC, switched to DGND or
to toggle at 400kHz (typ.) between DVCC and DGND. Pins
are tri-state in sleep mode. Can be left floating if unused.
VBATP,VBATM (Pins 48, 47):Battery Voltage Measure-
ment. The differential voltage between VBATP and VBATM
is internally buffered for ensuring high input impedance
(50MΩ) and low leakage (<10nA).
VREF (Pin 35):Reference Voltage Output. VREF provides
a buffered 3V reference voltage for temperature measure-
mentswith NTCs. Currentloadis limited to0.5mA. Bypass
this pin to AGND with a 1μF capacitor.
EXPOSED PAD (Pin 49): Connect to AGND.

LTC2949
13
Rev A
For more information www.analog.com
BLOCK DIAGRAM
50
50
50
50
7
5
CF1P
I1P
I1M
CF1M
VBATP
VBATM
1
FAST
CF2P
I2P
I2M
CF2M
CF1P
CF1M
CF2P
CF1M
AVCC
AUX
MOD
V1-V7
V8-V12 /
GPIO1-GPIO5
VREF1
1.2V
VREF2
2.39V
ISO26262
DIAGNOSTICS
AGND
2.5
VREF
OSC
CLKO
CLKI
ALU
CURRENT 1
CURRENT 1 THRESHOLDS
CURRENT 1 TRACKING
POWER 1
POWER 1 THRESHOLDS
POWER 1 TRACKING
POWER 2
POWER 2 THRESHOLDS
POWER 2 TRACKING
CURRENT 2
CURRENT 2 THRESHOLDS
CURRENT 2 TRACKING
CONTROL
STATUS
CHARGE & ENERGY THRESHOLDS
ENERGY 1 & 2
CHARGE & ENERGY TRACKING
BATTERY VOLTAGE
BATTERY VOLTAGE THRESHOLDS
BATTERY VOLTAGE TRACKING
FAST FIFO
TEMPERATURE
CHARGE 1 & 2
CURRENT HISTORY
... SEE REGISTER MAP...
SCK/IP
CSB/IM
SDO/IBIAS
SDI/ICMP
SERIAL I/O
GPIO CONTROL
IOVCC
SCL
SDA
P1
MOD
I1
MOD
I2
MOD
P2
MOD
1
1
P or V
P or V
SLOW
18 BIT, 100ms
15 BIT, 0.78ms
18 BIT, 100ms
15 BIT, 0.78ms
18 BIT, 100ms
15 BIT, 0.78ms
18 BIT, 100ms
15 BIT, 0.78ms
15 BIT, 0.78ms
AUX/MUX
VCC
TEMP
14 BIT, 6.5ms
13 BIT, 13ms
MUXP
MUXN
A/DVCC
SENSOR
TEMP
SENSOR
IPT
IMT
VREF2
VREF1*
AGND
DGND*
VREF**
BYP2*
BYP1*
DEGLITCH FILTER
FAST
SLOW
FAST
SLOW
FAST
SLOW
IPT
IMT
IPT
IMT
OCC2
OCC1
DEGLITCH FILTER
AUX MUX
LDO1
BYP2
BYP1
DVCC
AVCC
LDO2
* Measured value not accessible by user. Only used for internal diagnostics.
** VREF measurement value is only accessible by user from the AUX slow channel.
See also section 'Unused Input Pins V1-V12' for recommendation to allow VREF measurement from AUX fast channel.
See also 'Table 57. MUX Settings' for more details on AUX MUX configuration.

LTC2949
14
Rev A
For more information www.analog.com
OPERATION
OVERVIEW
The LTC2949 is a high precision current, voltage, charge
and energy meter for electrical and hybrid vehicles or
other applications requiring isolated data acquisition.
Operating from supply voltages from 4.5 to 14V, it infers
charge and energy flowing in and out of the battery pack
by monitoring simultaneously the current through up to
two sense resistors and the battery pack voltage. Five rail-
to-rail low-offset ΔΣ ADCs ensure accurate measurement
of currents, voltage and power with insignificant power
loss. The LTC2949 uses instantaneous multiplication of
voltage and current at a high sampling rate to infer ac-
curately power even in presence of fast load variations.
Additionally to the inputs for measuring currents and
battery voltage, the LTC2949 features 12 analog input
pins (V1 to V12) for measuring external voltages. Using
its built-in multiplexer, the LTC2949 performs differential
high input impedance rail-to-rail voltage measurements
between any pair of input pins. Pins V8 to V12 can be
configured as high voltage digital outputs, swinging from
ground to digital supply voltage (DVCC) for controlling
externalcomponents suchashighvoltage transistors.One
automatic measurement cycle of current, voltage, power,
temperature, supply voltage and two programmable mul-
tiplexer settings takes 100ms in slow mode. The LTC2949
repeatedlyperformssuchmeasurementsandrecalculates
energy, charge,timeand updates theminimum/maximum
tracking and threshold registers, resulting in continuous
integration of current and power with lossless tracking
of charge and energy delivered or received by the battery
pack. An on-chip oscillator provides a 1% precise time
baseforcalculatingtotalcharge,energyandtime.Ifhigher
accuracy is required, a 4MHz crystal connected between
pin CLKI and CLKO or an external clock can be used.
For time critical applications, a fast mode is available
which reduces conversion times to 782µs. Data acquired
during fast operation is stored in four FIFOs which contain
each up to 1000 fast ADC readings from 4 synchronously
measured parameters. Reading data from the FIFO yields
simultaneouslyconvertedconversionresults,enablingbat-
teryimpedancetracking,currentprofilingormonitoringof
other fast events, such as the pre-charging voltage before
closing contactors. Thresholds can be set for parameters
measured in slow mode, and the LTC2949 will set the
corresponding bit in the Alert Register if a threshold is
exceeded.Programmable heartbeatfunctionsonupto two
GPIOs allow to signal any enabled alert over an isolation
barrier, independent of the serial interface. Those pins
toggle at 400kHz and stop toggling in case of an alert.
The LTC2949 features a programmable analog overcur-
rent comparator for each current channel for applications
which require fast detection of overcurrent conditions. A
programmable deglitch filter allows to discard overcur-
rent conditions shorter than a predefined time duration*.
A 3V reference voltage output (VREF) is provided for
connecting external NTCs or voltage dividers allowing to
measuresignalsbelowground.Inslowmode,theLTC2949
provides means for linearizing temperature readings of up
to two external NTCs by solving Steinhart-Hart equations
with programmable coefficients. The LTC2949 can be
configuredtoautomaticallycompensateuser-programmed
temperature coefficients of low-cost shunt resistors by
using linearized NTC temperature readings.
The LTC2949 features programmable gain correction
factors to compensate for tolerances of external shunt
resistors and resistor dividers. A master I2C interface and
dedicated commands allow to read from and write to an
externalEEPROM whichcanbeused forstoringcalibration
factors and the entire register content of the LTC2949 to
guarantee data retention without supply. Storing correc-
tion factors in an EEPROM enables a modular approach
to factory-calibration of application boards.
Athermalshutdowncircuittripsatdietemperaturesabove
150°C and resets the IC to default state, only the thermal
shutdown bit itself is not reset.
Measured quantities are stored in internal registers acces-
sibleviatheonboardSPIorLTC-proprietaryisoSPIinterface
which allows fully isolated operation of the LTC2949. The
LTC2949wasdevelopedforcompatibilitywithLinear’sMul-
ticell Battery Monitors (LTC68XX). Various bus structures
ineitherSPIorisoSPI,multi-dropand/ordaisychainingare
possible. The LTC2949 supports a limited set of Linear’s
Battery Cell Monitor compatible commands for triggering
synchronous ADC conversions and reading back data.
*An overcurrent condition is signaled by a dedicated heartbeat pin for fastest response times.

LTC2949
15
Rev A
For more information www.analog.com
Digital data acquired in isolated operation is transferred
over external capacitors or transformers across an isola-
tion barrier. Bridging potential differences of several kV is
achieved by choosing appropriate external components.
All those features enable a wide variety of applications
beyond current and charge measurement, like measur-
ing isolation resistance, controlling pre-charge switches,
signalingalarmconditions,monitoringstateofcontactors,
etc. The LTC2949 offers various diagnosis functions to
support functional safety critical systems, see the Safety
Manual for more information.
MODES OF OPERATION
Core State Description
When all power supply voltages have risen above their
UVLO thresholds, the LTC2949 boots up, sets all registers
to their default state and enters after 1s its default SLEEP
state with a current consumption of 9µA (typ), prevent-
ing rapid discharge after insertion when being supplied
by a battery.
In SLEEP state, all GPIOs are tri-state and the LTC2949
monitorstheserialinterfaceandinitiatesthebootsequence
on a falling edge of CSB in SPI mode. In isoSPI mode the
isoSPIinterface mustfirstbewokenupbya wake-up pulse
before a pulse generating a negative edge on the internal
CSB can be sent. During the boot sequence, the host can
polltheSLEEPbitintheOperationControlRegistertocheck
thatthe LTC2949isawakeand inSTANDBYmode(seealso
Figure 20 about Wake-Up and Boot procedure). LTC2949
enters STANDBY state maximum 100ms (tBOOT) after the
first falling edge of CSB. In STANDBY state all reference
voltages are powered up and a clock is provided to digital
circuits.TheLTC2949automaticallyreturnstoSLEEPstate
if no wake up confirmation command is received within 1
second (tACKN) after entering STANDBY state. Wake up is
confirmed by writing 0x00 to register WKUPACK.
The LTC2949 enters SLEEP state ~200ms (tSLEEP) after
receivingasleepcommand.AnegativeedgeonCSBduring
OPERATION
Figure 1. LTC2949 Operation State Diagram
tSLEEP willpreventtheLTC2949fromenteringSLEEPstate.
In SLEEP, internal analog supplies and BYP1 are switched
off, causing the UVLOA and UVLOD bits to be set when
the LTC2949 resumes from SLEEP. An internal always-on
regulatedvoltagesuppliesthememoryandguaranteesdata
retention during SLEEP. If AVCC or DVCC drop below the
UVLO threshold, the UVLO bit of the internal always-on
supply UVLOSTBY is set and a power-on-reset occurs,
resetting all registers to their default value. In STANDBY
state, all internal circuitry is active but no measurements
except the reference voltage (VREF) are being made.
From STANDBY, the LTC2949 can be instructed to go into
MEASURE state by setting the single shot (SSHOT) or
continuous (CONT) bit in the Operations Control Register
OPCTRL.
isoSPI State Description
If the IOVCC pin is tied to a supply voltage ≥1.8V, the
LTC2949 operates in normal SPI mode and IOVCC sup-
plies the receiving circuit and output driving circuit for all
SPI signals.
Tying IOVCC to DGND enables the isoSPI port. The isoSPI
port has three different states:IDLE, READY and ACTIVE.
In IDLE state, the isoSPI port is powered down. Only
SLEEP
STANDBY
MEASURE
CORE LTC2949
SLEEP = 1
(tSLEEP)
SLEEP = 1
(tSLEEP)
NEGATIVE EDGE
ON CSB
(tBOOT)
NO WAKEUP
CONFIRMATION
(tACKN)
POWER UP
(tBOOT)
2949 F01
SSHOT = 1
OR
CONT = 1
CONV. DONE
AND
CONT = 0

LTC2949
16
Rev A
For more information www.analog.com
Figure 3. Timing of IsoSPI and Core States
OPERATION
Figure 2. isoSPI State Diagram
differential activity on IP-IM generates a wake-up signal
and the isoSPI port will enter READY state after tREADY
(10µs) and be ready to send or receive data. The current
consumption increases by several mA in READY. When
communication takes place the isoSPI port is in ACTIVE
state and supply current rises further depending on clock
frequency. In order to save power the isoSPI port enters
IDLE state when there has been no differential activity on
IP-IM for more than tIDLE (6.4ms typ.). Communication
to the LTC2949 core is only possible if the isoSPI port is
not in IDLE state. This means that even when the LTC2949
core is in STANDBY or MEASURE state and the isoSPI port
is in IDLE state, communication can only take place 10µs
(tREADY) after differential activity on IP-IM.
Figure 2 displays the sequence of states which the isoSPI
interface and the LTC2949 core go through from waking
up the interface until effectuating ADC measurements.
See also Figure 20 for recommended wake-up sequence
implementations.
DATA ACQUISITION CHANNELS
The LT2949 has two current ADCs (I1ADC, I2ADC), two
power ADCs (P1ADC, P2ADC) and one Auxiliary ADC
(AUXADC). I1ADC and P1ADC are grouped together and
form data acquisition channel 1 (CH1), I2ADC and P2ADC
form channel 2 (CH2) and the AUXADC together with
auxiliary multiplexer (AUXMUX), die-temperature sensor
and supply voltage sensor form channel AUX (CHAUX).
IDLE
READY
ACTIVE
isoSPI Port
IDLE TIMEOUT
(tIDLE)
WAKEUP SIGNAL
(tREADY)
2949 F02
TRANSMIT/RECEIVE
NO ACTIVITY ON
isoSPI PORT
CH1 and CH2 can be individually set to an 18-bit high
precision mode (slow mode, default) or a 15-bit fast
mode. Activating fast mode reduces conversion times
from 100ms to 782µs on the selected channel. The power
ADCs can be individually configured as voltage ADCs by
disabling the power multiplication after the input buffers
by setting the corresponding Power as Voltage (PasV) bit
in ADC Configuration Register (ADCCONF).
Slow, High Precision Mode
By default, LTC2949’s acquisition channels are in slow
high precision mode where conversions of CH1 or CH2
take 100ms and yield 18-bit conversion results of current
and power or current and voltage, if PasV set. During
these 100ms the auxiliary channel (CHAUX) measures
NOTE, THAT THE DIFFERENTIAL PULSE ON IP-IM TO WAKE-UP THE IsoSPI INTERFACE CAN BE REALIZED BY A CSB DRIVE LOW PULSE (CSB = 0 FOLLOW BY CSB = 1).
tDWELL tDWELL
tREADY tIDLE
VWAKE
tREADY
tBOOT
tIDLE
READYREADYREADY
SLEEPCORE STATE
IP-IM
isoSPI STATE
DATA LAYER CSB=0 CSB=1 CSB=0
CONFIRM WAKE-UP:
WRITE 0x0 TO WKUPACK
START MEASUREMENT:
WRITE 0x08 TO OPCTRL
CSB=1
STANDBY MEASURE
2949 F03
IDLEIDLE ACTIVE IDLE
tIDLE_CORE

LTC2949
17
Rev A
For more information www.analog.com
OPERATION
sequentially six different quantities using its Round Robin
(RR) mode starting with VBATP –VBATM (BAT) then die-
temperature (TEMP), AVCC supply voltage (VCC), two
AUXMUX inputs (SLOT1 and SLOT2), selectable by the
Multiplexer Setting Registers and finally the Reference
Voltage (VREF). Furthermore, a moving average of the last
four measurements of IADC1 and IADC2 in slow mode is
provided, yielding a 20-bit result. In slow, high precision
mode a single conversion or continuous conversions can
be triggered. The continuous slow mode (CONT) is the
most typical operation and also the prerequisite to make
fast conversions.
Single Shot Measurement Mode (SSHOT)
When bit SSHOT in the Operation Control Register is set,
the LTC2949 takes measurements of CH1 and CH2 as
well as the six auxiliary channel measurements described
above, updates the corresponding minimum, maximum
and threshold registers, resets bit SSHOT, sets the bit
UPDATE in Status Register and returns to the STANDBY
state.Notime measurements are made andthechargeand
energy registers are not updated and therefore not com-
pared against minimum/maximum thresholds. The host
can poll the UPDATE bit in the STATUS Register to detect
thecompletionofthemeasurementcycle.A measurement
starts within 20ms (tIDLE_CORE) after setting bit SSHOT.
Continuous Measurement Mode (CONT)
When the bit CONT in the Operation Control is set, the
LTC2949repeatedlytakesmeasurementsofCH1andCH2as
wellasthesixauxiliarychannelmeasurements,recalculates
energy, charge, time and updates the minimum/maximum
tracking and status registers every 100ms. The start of
continuous high precision measurements can take up to
20ms (tIDLE_CORE) after setting bit CONT. The current and
power ADCs run continuously in this mode, ensuring that
no charge or energy is missed. If a power ADC is configured
to measure voltage (PasV), the energy of the correspond-
ing channel is not accumulated. The LTC2949 remains in
continuous mode until bit CONT of the Operation Control
Register is reset by the user. If the SSHOT bit is set while
in continuous mode, the LTC2949 completes the current
measurement cycle and then enters single shot mode,
clearing the CONT bit in the Operation Control Register.
In continuous measurement mode, the host can poll for
the end of a measurement cycle by periodically checking
the corresponding time registers (TB1, TB2, TB3 or TB4)
for incrementation.
Accessing High Precision Results
At the end of each measurement cycle of 100ms, all result
register for the measured quantities are updated;in con-
tinuous mode, accumulated quantities are updated also.
Furthermore, the four preceding measurements of each
current channel are stored in Current History Registers
and their average in Current Average Registers, see the
Register Map section for more details. The completion
of register updates of the measurement results can be
detected by reading one of the time registers (TB1-TB4)
and looking for a changed value.
Fast Mode
The LTC2949 provides a fast mode with a reduced conver-
sion time of 782µs and a resolution of 15-bit. Fast mode
allows to start measurements at a precise point in time
andtherebyperformmeasurementssynchronizedwiththe
voltage measurements of LTC’s Battery Stack Monitors,
for example to deduce cell impedance of individual cells.
Fast Mode Configurations
The LTC2949 allows to set data acquisition channel 2 in
fast mode while data acquisition channel 1 stays in slow
high precision mode or to set both data acquisition chan-
nels 1 and 2 in fast mode by setting the corresponding bit
FACH1 or FACH2 in the Fast Control Register (FACTRL).
The auxiliary channel can be set to fast mode indepen-
dently of CH1 and CH2, converting only a single quantity
(selected by the Fast MUX Control Registers) instead of
Round-Robin (RR).
To enable short startup delays, the LTC2949 must be in
continuous mode (CONT=1) before triggering fast conver-
sions. Fast measurements are triggered either by an ADCV
command (fast single shot) or by setting bit FACONV in
the Fast Control Register (FACTRL). The ADCV command
triggers a single fast conversion of the selected channels
right after the correct PEC is received, synchronous to

LTC2949
18
Rev A
For more information www.analog.com
OPERATION
LTC’s Battery Stack Monitors. If fast measurements are
triggered by setting FACONV=1, LTC2949 executes a
sequence of fast conversions until FACONV or CONT is
reset. Samples acquired during fast continuous mode are
stored in individual FIFOs for up to four fast input channels
(I1, I2, BAT via P1 or P2 and AUX).
CH1 and CH2 automatically restart in slow high precision
mode after completion of joint fast mode conversions. If
CH2 was in fast mode while CH1 continued in slow high
precisionmode, CH2 willstopconverting after completion
offastmodeacquisitionsreadytoperformfurtherfastmode
conversions when requested either by an ADCV command
or by setting FACONV again. The auxiliary channel slow
mode Round-Robin (BAT, TEMP, VCC, SLOT1, SLOT2,
VREF)isautomaticallyrestartedafterallfastmeasurements
were stopped for 300 ms. In applications were continuous
high AUX measurement rates (faster than every 100ms)
are required, it is recommended to measure also VREF
and optionally VCC via external connections to V1-V12
and implement a manual Round-Robin by fast single shot
measurements in software.
Accessing Fast Mode Results
The last results of fast conversions can be read out by
the RDCV command providing sequentially the results of
I1, I2, BAT via P1 or P2 and AUX followed by an indica-
tor if the data is new (0xF) or old (0x0). BAT is the result
of the power ADC, if the ADC is set in voltage mode (bit
PasV=1), otherwise, the power ADC result is 0. If both
channels are in fast mode with their power ADCs in volt-
age mode, BAT is obtained from PADC1. Please note that
to be compliant with LTCs Battery Stack Monitors, RDCV
reports LSByte first.
Furthermore, the last 1000 fast conversion results of I1,
I2, BAT via P1 or P2 and AUX are stored in First-In-First-
Out Registers accessible by FIFOI1, FIFOI2, FIFOBAT and
FIFOAUX. Reading continuously from FIFOI1 provides
successively 3 bytes for each sample of the first current
ADC: I1 MSB, I1 LSB and a qualifier (TAG) whether the
corresponding FIFO data is fine (0x00), has been already
read because no new data has been added to the FIFO
since the whole FIFO was read (0x55, default), or has
been overwritten because the FIFO was filled without
being read (0xAA). The other FIFOs present the respec-
tive quantities accordingly. All tags are initialized to their
default value (0x55), if fast conversions are triggered by
an ADCV command (while FACONV =0) or by setting
FACONV. Also leaving the continuous mode by resetting
CONT will clear the FIFOs.
The LSB sizes of the fast conversion results are the same
for the RDCV and FIFO readings and are listed in Table 28.
When CH1 and CH2 are both in fast mode, 128 conversion
results of IADC1 and IADC2 are averaged and stored in
theirrespectivenon-accumulatedresultsregistersCurrent1
and Current2 and are added to the Charge1 and Charge2
registers ensuring that battery charge and discharge is
monitored also in fast mode.
Similarly 128 conversion results of PADC1 and PADC2
with 11 bit resolution are averaged and stored in their
respective non-accumulated results registers Power1 at
and Power2 and are added to the Energy1 and Energy2
registers if the PADCs are in Power Mode (PasV=0). If CH1
isin slowmode andCH2 in fastmode, onlyCH1 results are
reported in the Current and Power results registers, CH2
results can be accessed via RDCV or the respective FIFOs.
Recommended Configurations of Data Acquisition
Channels
Inatypicalapplicationcase,bothdataacquisitionchannels
offeredby LTC2949couldmonitorthe currentoverasingle
shunt resistor, where CH1 is used to do high precision
current and power measurements and charge and energy
integration, while channel two takes fast snapshots of cur-
rentand voltage forexampleforimpedancemeasurement.
Alternatively, the two data acquisition channels offered
by LTC2949 might be used to monitor currents over two
different shunt resistors. In this application case, both
channelsmightbeusedineitherfastorslowmode.CHAUX
can be configured fully independently from CH1 and CH2.
The default mode of AUXADC is RR, which is deactivated
by enabling fast mode on CHAUX.

LTC2949
19
Rev A
For more information www.analog.com
OPERATION
Table 1. Acquisition Channels Configurations
SINGLE SHUNT DUAL SHUNT
CH1 Slow Slow Fast
CH2 Fast Slow Fast
CHAUX RR/Fast RR/Fast RR/Fast
Single Shunt Configuration
If only one external shunt is used, CH1 can be used to
perform continuous high precision integrated charge and
energy measurements, while CH2 is used to perform fast
measurements synchronized with LTC's Battery Stack
Monitors. By setting bit CONT in the Operation Control
Register (OPCTRL) and bit FACH2 in the Fast Control
Register (FACTRL), CH1 will effectuate consecutive slow
measurements, while CH2 is available for fast measure-
ments triggered by an ADCV command. Measurements
of CH1 and its integrated quantities are updated every
100ms while CH2 results can be read out with an RDCV
command or obtained from the FIFO registers, in case of
fast continuous (FACONV) operation.
Dual Shunt High Precision Configuration
For dual shunt applications that require continuous un-
interrupted high precision coulomb counting and energy
measurement CH1 and CH2 should be both configured to
slow high precision mode by setting bit CONT in OPCTRL.
Conversions on CH1 and CH2 take 100ms and a new RR
cycleofCHAUXisstartedateverystartofconversionofCH1.
If fast voltage data is required, the AUXADC can be config-
ured for fast mode without interrupting charge and energy
accumulation on CH1 and CH2. After setting bits FACONV
and FACHA the AUXADC immediately stops RR mode and
continuously measures a single quantity selected by the
FastMUXControlRegisters.DataiswrittentotheFIFOAUX.
AfterclearingbitFACHAthe AUXADCautomaticallyreturns
to RR operation (after 300ms). Measurements of VREF,
internal die temperature and VCC are only available if RR
is enabled. Alternatively, external connections to V1-V12
can be applied to measure VREF and VCC (via an external
resistive divider) also in fast mode.
Figure 4. Power Measurement of Transient Signals
Dual Shunt Fast Measurement Configuration
CH1 and CH2 are both set to fast mode by setting bits
FACONV, FACH1 and FACH2. Charge is accumulated by
summing up 15-bit current results, energy by summing
up 11 bit power results.
One conversion takes 782µs and a new RR cycle is started
afterevery100ms. This configurationfits toanapplication
where two shunt resistors are used and fast current, volt-
age and power is required. E.g.:Fast impedance tracking
or measuring pre-charge voltage and current.
POWER MEASUREMENT
The LTC2949 measures power with additional ADCs that
multiply voltage (VBATP –VBATM) and current at the full
5.24MHzsamplingfrequency,priortoanyaveragingdueto
the analog-to-digital conversion. This maintains accuracy
even if current and voltage change in phase during the
100ms conversion time, which can happen if the power
is drawn from a battery with significant impedance. Figure
4 shows an example of the BAT voltage dropping from 4V
to 3V due to battery impedance when an AC current is
drawn by the load. In this example, the multiplication of
average current with average voltage would lead to a +8%
error in the calculated power as the voltage is significantly
lower than the average voltage at the moments where the
peak current is drawn. The scheme used by the LTC2949
avoids this error, maintaining specified accuracy with
signals up to 50kHz.
TIME (ms)
0
VOLTAGE (V)
CURRENT (µV)
5.0
4.0
3.5
2.5
4.5
3.0
2.0
120
80
60
20
100
40
0
0.4 0.80.2 0.6
2949 F04
10.90.3 0.70.1 0.5
VOLTAGE (VBATP–VBATM)
CURRENT (IP–IM)

LTC2949
20
Rev A
For more information www.analog.com
OPERATION
Figure 5. Reference Clock with a 4MHz Crystal
CHARGE, ENERGY AND TIME
The LTC2949 integrates the current and power measure-
ments over time to calculate charge and energy flowing
to the load. It also keeps track of total accumulated time
used for the integration.
ForthequantitieschargeandenergytheLTC2949provides
three sets of registers each, for the quantity "time" four
register sets.
Charge1, Energy1 and Time1 contain accumulated quan-
tities of Channel1. Charge2, Energy2 and Time2 contain
accumulated quantities of Channel2. Charge3 and Time3
contain the sum of charges monitored by Channel1 and
Channel2 and the corresponding time. Similarly Energy4
and Time4 contain the sum of energies monitored by
Channel1 and Channel2 and the corresponding time. See
the Accumulated Result Registers section in the Register
Map description for more details.
Each register set can be separately configured to accumu-
late current and power based on the sign of the measured
current.Aminimumcurrentthresholdcanalsobesetbelow
which integration is stopped. See the Control Registers
section in the Register Map description for more details.
Time Base
Accurately measuring charge and energy by integrating
current and power requires a precise integration period.
The LTC2949 uses either a trimmed internal oscillator or
an external clock as the time base for determining the in-
tegration period. It can use either an external square wave
clock in a frequency range between 100kHz and 25MHz
or a 4MHz crystal as external clock input. If an external
square wave is used, it should be connected to the CLKI
pin and the CLKO pin should be left unconnected.
Figure5 showstherecommendedcircuitifa crystalisused
to generate the reference clock. In case the internal clock
is used, tie CLKI to ground and leave CLKO unconnected.
Timebase Control
The LTC2949 uses the internal oscillator by default. If
an external clock or a crystal is used, the PRE and DIV
parameters in the Timebase Control Register need to be
set appropriately. The LTC2949 then compares its inter-
nal clock to the external frequency and represents Time,
Charge, and Energy as multiples of the external clock pe-
riod. To accommodate the large range of allowed external
frequencies, an internal prescaler must be configured via
the Timebase Control Register.
The prescaler consists of 2 stages, with the first divid-
ing the external frequency fREF by a factor 2PRE, and the
second by a factor DIV. PRE is set between 0 and 5 with
bits [2:0] of the Timebase Control Register. PRE should
be configured such that the external frequency divided by
2PRE is less than 1MHz as shown in Table 2:
Table 2. Parameter PRE with External Clock
fREF PRE 2PRE PRE[2:0]
0.1MHz ≤ fREF ≤ 1MHz 0 1 000
1MHz ≤ fREF ≤ 2MHz 1 2 001
2MHz ≤ fREF ≤ 4MHz 2 4 010
4MHz ≤ fREF ≤ 8MHz 3 8 011
8MHz ≤ fREF ≤ 16MHz 4 16 100
16MHz ≤ fREF ≤ 25MHz 5 32 101
Internal 7 111
The second stage of the prescaler then divides the result
by a factor DIV. DIV is set between 0 and 31 by bits [7:3]
of the Time Base Control Register. DIV should be set to the
next lower integer value of the ratio between the output
of the first stage of the prescaler (fREF_1 = fREF/2PRE) and
32768Hz or, in other terms:
DIV =floor
f
REF
2PRE •32768Hz
⎛
⎝
⎜⎞
⎠
⎟
If a crystal is used, the values are:PRE =2, DIV =30. The
Quick Eval™Software for the LTC2949 contains an easy
to use calculator for these parameters. Table 3 gives a few
examples for common frequencies.
LTC2949
X1: ABLS2-4.000MHZ-D4Y-T
CLKI CLKO
2949 F05
33pF
X1
33pF