LTC2949
9
Rev A
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C Interface Timing Specification (SCL, SDA)
fSCL(MAX) Maximum SCL Clock Frequency l8 10 kHz
tSCLLO SCL Low Period l80 µs
tSDALO SDA Low Period l80 µs
tBUF(MIN) Bus Free Time Between STOP/START l30 µs
tSU,STA(MIN) Minimum Repeated START Setup Time l30 µs
tHD,STA(MIN) Minimum Hold Time (Repeated) START
Condition
l30 µs
tSU,STO(MIN) Minimum Setup Time for STOP Condition l30 µs
tSU,DAT(MIN) Minimum Data Setup Time Input l30 µs
tHD,DAT(MIN) Minimum Data Hold Time Input l0 ns
tHD,DATO Minimum Data Hold Time Output l30 µs
tOF Data Output Fall Time (Notes 7, 8) l20 + 0.1
• CB
ns
Digital Core Timings (See Figure 3)
tBOOT Core Boot-Up Time from SLEEP or POWER-OFF
to STANDBY AVCC/DVCC Pins at Minimum Operating
Voltage
l100 ms
tIDLE_CORE Core STANDBY Cycle Time (Note 10) l17 20 ms
tCONT Core MEASURE Cycle Time (Note 11) l90 100 110 ms
tMLCK,M Memory Lock Request to Acknowledge Time Core Status MEASURE l130 ms
tMLCK,S Memory Lock Request to Acknowledge Time Core Status STANDBY l40 ms
tACKN Time from Core Entering STANDBY to Return to
SLEEP, When Wake-Up is not Confirmed No Write of 0x0 to Reg. WKUPACK, No
Write of 0x8 to Reg. OPCTRL
l0.6 1.5 s
Time Base
TUETB TUE Time Base Internal Clock 0.5 %
l1 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect the device
reliability and lifetime.
Note 2: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum values refer to absolute values.
Note 3: Do not apply a voltage or current source to these pins. They must
be unconnected, connected to capacitive loads or connected to a crystal
according to their pin description. Otherwise permanent damage may
occur.
Note 4: Do not apply a voltage source to these pins. Overloading these
pins might disrupt operation.
Note 5: Active supply current (ICC) is dependent on the amount of time
that the output drivers are active on IP and IM. During those times ICC will
increase by the 20 • IBdrive current. For the maximum data rate 1MHz, the
drivers are active approximately 5% of the time.
Note 6: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 7: Guaranteed by design and characterization, not subject to
production test.
Note 8: CB= capacitance of one bus line in pf (10pF < CB< 400pF)
Note 9: These specifications do not include rise time of SDO due to pull up
resistance and load capacitance on SDO pin.
Note 10: Cycle time at which STATUS/FAULTS and VREF registers are
updated.
Note 11: Cycle time at which STATUS/ALERT/FAULTS registers and all
slow channel measurement results are updated after the first update. The
first update after enabling any measurement is typically 50ms delayed.
