Analog Devices LTM4683 User manual

LTM4683
1
Rev. 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Low VOUT Quad 31.25A or Single 125A µModule
Regulator with Digital Power System Management
The LTM
®
4683 is a quad 31.25A or single 125A step-
down µModule
®
(power micromodule) DC/DC regulator
featuring remote configurability and telemetry monitor-
ing of power management parameters over PMBus. The
LTM4683 is comprised of digitally programmable analog
control loops, and is optimized for higher bandwidth and
transient response.
The LTM4683’s 2-wire serial interface allows outputs
to be margined, tuned, and ramped up and down at
programmable slew rates with sequencing delay times.
True input current sense, output currents and voltages,
output power, temperatures, uptime and peak values are
readable. Custom configuration of the EEPROM contents
is not required. At start-up, output voltages, switching
frequency, and channel phase angle assignments can be
set by pin-strapping resistors. The LTpowerPlay
®
graphical
user interface (GUI), DC1613AUSB-to-PMBus converter,
and evaluation kits are available.
The LTM4683 is offered in a 15mm ×22mm ×5.71mm BGA
package available with a RoHS-compliant terminalfinish.
APPLICATIONS
n Quad Digitally Adjustable Analog Loops with Digital
Interface for Control and Monitoring
n Wide Input Voltage Range: 4.5V to 14V
n Output Voltage Range: 0.3V to 0.7V
n ±0.5% DC Output Accuracy at 0.7V
n ±4.5% Current Readback Accuracy: 0°C to 125°C
n Optimized for Low Output Voltage Ranges
n 400kHz PMBus-Compliant I2C Serial Interface
n Supports Telemetry Polling Rates Up to 125Hz
n Integrated 16-Bit ∆Σ ADC
n Parallel and Current Share Multiple Modules
n 15mm ×22mm ×5.71mm BGA Package
Readable Data
n Input and Output Voltages, Currents, and Temperatures
n Running Peak Values, Uptime, Faults, and Warnings
n Onboard EEPROM Fault Log Record
Writable Data and Configurable Parameters
n Output Voltage, Voltage Sequencing, and Margining
n Digital Soft-Start/Soft-Stop Ramp, Program Analog Loop
n OV/UV/OT, UVLO, Frequency and Phasing
n Multi-Rail Processor Power, Configurable Core Power
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Quad 31.25A µModule Regulator with Digital Interface for Control and Monitoring Channel Efficiency vs Load Current
POWER GOOD MONITORS
FAULT INTERRUPTS
ON/OFF CONTROL
4.5V TO 14V
C
BULK
22µF
×6
22µF
×6
LOAD
0.7V AT 31.25A
C
BULK
LOAD
0.6V AT 31.25A
C
BULK
LOAD
0.5V AT 31.25A
C
BULK
LOAD
0.4V AT 31.25A
CER
CER
CER
CER
4683 TA01a
PGOOD0,1,2,3
WP_23 WP_01 SYNC_01 SYNC_23 SHARE_CLK_01 SHARE_CLK_23 ALERT_01 ALERT_23 SDA_01 SDA_23 SCL_01 GND SGND_23 SGND_01 SCL_23
FAULT0,1,2,3
RUN0,1,2,3
RUNP
VIN_VBIAS
SVIN_23
VIN23
IN_23–
IN_23+
SVIN_01
VIN01
IN_01–
IN_01+
VOSNS3–
VOSNS3+
VOUT3
VOSNS2–
VOSNS2+
VOUT2
VOSNS1–
VOSNS1+
VOUT1
VOSNS0–
VOSNS0+
VOUT0
LTM4683
I2C/SMBus I/F WITH PMBus COMMAND
SET TO/FROM IPMI OR OTHER
BOARD MANAGEMENT CONTROLLER
SYNCHRONIZATION TIME
BASE REGISTER WRITE
PROTECTION
FOR COMPLETE CIRCUIT
SEE FIGURE 48
(FROM 4.5V TO 5.5V
CONNECT VIN, SVIN,
AND INTVCC TOGETHER)
+
+
+
+
RSENSE1
RSENSE2
LOAD CURRENT (A)
0
5
10
15
20
25
30
35
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
4683 TA01b
12VIN, 0.3VOUT, 250kHz
12VIN, 0.4VOUT, 350kHz
12VIN, 0.5VOUT, 425kHz
12VIN, 0.6VOUT, 500kHz
12VIN, 0.7VOUT, 575kHz
Configurable Output Array
31.25A
31.25A
31.25A
31.25A
62.5A
31.25A
31.25A
93.75A
31.25A
62.5A
62.5A
125A

LTM4683
2
Rev. 0
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TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics ................................. 5
Typical Performance Characteristics .................. 12
Pin Functions .............................................. 15
Simplified Block Diagram ............................... 23
Decoupling Requirements............................... 23
Functional Diagram ...................................... 24
Test Circuits ............................................... 25
Operation................................................... 27
Power Module Introduction ....................................27
Power Module Major Features Overview ................27
EEPROM with ECC..................................................28
Power-Up and Initialization .....................................29
Soft-Start................................................................30
Time-Based Sequencing .........................................30
Voltage-Based Sequencing .....................................31
Shutdown ...............................................................31
Light-Load Current Operation .................................31
Switching Frequency and Phase .............................32
PWM Loop Compensation......................................32
Output Voltage Sensing ..........................................32
INTVCC/VBIAS Power...............................................33
Output Current Sensing and Sub Milliohm DCR
Current Sensing......................................................33
Input Current Sensing.............................................33
PolyPhase Load Sharing.........................................34
Internal Temperature Sense....................................34
RCONFIG (Resistor Configuration) Pins ....................34
Table1. VOUTn_CFG Pin Strapping Look-Up Table
for the LTM4683’s Output Voltage, Coarse Setting
(Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top
Resistor = 14.3k..................................................35
Table2. VTRIMn_CFG Pin Strapping Look-Up
Table for the LTM4683’s Output Voltage, Fine
Adjustment Setting (Not Applicable if MFR_
CONFIG_ALL[6] = 1b) Top Resistor = 14.3k........35
Table3. FSWPH_nn_CFG Pin Strapping Look-Up
Table to Set the LTM4683’s Switching Frequency
and Channel Phase-Interleaving Angle (Not
Applicable if MFR_CONFIG_ALL[6] = 1b), nn = 01
or 23 Channels, Set Top Resistor to 14.3k..........36
Table4. ASEL_nn Pin Strapping Look-Up Table
to Set the LTM4683’s Subordinate Address
(Applicable Regardless of MFR_CONFIG_ALL[6]
Setting)...............................................................37
Table5. LTM4683 MFR_ADDRESS Command
Examples Expressed in 7- and 8-Bit Addressing 37
Fault Detection and Handling..................................37
Status Registers and ALERT Masking...................38
Figure5. LTM4683 Status Register Summary per
Controller............................................................39
Mapping Faults to FA U LTnPins.............................40
Power Good Pins..................................................40
CRC Protection .....................................................40
Serial Interface .......................................................40
Communication Protection ...................................40
Device Addressing .................................................. 41
Responses to VOUT and IIN/IOUT Faults ................... 41
Output Overvoltage Fault Response ..................... 41
Output Undervoltage Response............................42
Peak Output Overcurrent Fault Response .............42
Responses to Timing Faults....................................42
Responses to VIN OV Faults....................................42
Responses to OT/UT Faults.....................................43
Internal Overtemperature Fault Response.............43
Overtemperature and Undertemperature
FaultResponse...................................................43
Responses to Input Overcurrent and Output
Undercurrent Faults ................................................43
Responses to External Faults..................................43
Fault Logging..........................................................43
Bus Timeout Protection ..........................................44
Similarity Between PMBus, SMBus and I2C 2-Wire
Interface .................................................................44
PMBus Serial Digital Interface................................44
Figure7 to Figure24 PMBus Protocols ..................45
Table6. Abbreviations of Supported Data Formats ... 45
Figure6. PMBus Timing Diagram.........................45
PMBus Command Summary ............................ 49
PMBus Commands .................................................49

LTM4683
3
Rev. 0
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TABLE OF CONTENTS
Table7. PMBus Commands Summary (NOTE: The
Data Format Abbreviations are Detailed in Table8). 49
Table8. Data Format Abbreviations......................54
Applications Information ................................ 55
VIN to VOUT Step-Down Ratios................................55
Input Capacitors .....................................................55
Output Capacitors...................................................55
Light Load Current Operation .................................55
Switching Frequency and Phase .............................56
Output Current Limit Programming ........................57
Minimum On-Time Considerations..........................58
Variable Delay Time, Soft-Start and Output Voltage
Ramping .................................................................58
Digital Servo Mode .................................................58
Soft Off (Sequenced Off)........................................59
Undervoltage Lockout.............................................60
Fault Detection and Handling..................................60
Open-Drain Pins .....................................................61
Phase-Locked Loop and Frequency Synchronization .. 61
Input Current Sense Amplifier.................................62
Programmable Loop Compensation .......................62
Checking Transient Response.................................62
PolyPhase Configuration ......................................64
Connecting The USB to I2C/SMBus/PMBus Controller
to the LTM4683 In System .....................................64
LTpowerPlay: An Interactive GUI for DigitalPower .65
PMBus Communication and Command Processing65
Thermal Considerations and Output CurrentDerating. 67
Table13. Single Channel Output Voltage vs
Capacitor Selection, 10A to 20A Load Step with
10A/µs Slew Rate ...............................................72
Table14. Single Channel Output Voltage vs
Capacitor Selection, All Ceramic Configuration,
10A to 20A Load Step with 10A/µs Slew Rate ....73
Table15. Dual Connected Channels Output Voltage
vs Capacitor Selection, Bulk and Ceramic Cap
Configuration, 10A to 30A Load Step with 20A/µs
Slew Rate ........................................................... 74
Table16. Quad Connected Channels Output Voltage
vs Capacitor Selection, Bulk and Ceramic Cap
Configuration, 10A to 40A Load Step with 15A/µs
Slew Rate ...........................................................75
EMI Performance....................................................76
Safety Considerations.............................................76
Layout Checklist/Example ...................................... 76
Typical Applications ...................................... 78
PMBus Command Details ............................... 83
Addressing and Write Protect.................................83
General Configuration Commands..........................85
On/Off/Margin ........................................................86
PWM Configuration ................................................88
Voltage....................................................................91
Input Voltage and Limits.......................................91
Output Voltage and Limits ....................................92
Output Current and Limits ......................................95
Input Current and Limits.......................................97
Temperature............................................................98
Power Stage DCR Temperature Calibration...........98
Power Stage Temperature Limits..........................98
Timing ....................................................................99
Timing—On Sequence/Ramp...............................99
Timing—Off Sequence/Ramp ............................ 100
Precondition for Restart ..................................... 101
Fault Response ..................................................... 101
Fault Responses All Faults.................................. 101
Fault Responses Input Voltage ........................... 102
Fault Responses Output Voltage......................... 102
Fault Responses Output Current......................... 105
Fault Responses IC Temperature ........................ 106
Fault Responses External Temperature............... 107
Fault Sharing......................................................... 108
Fault Sharing Propagation .................................. 108
Fault Sharing Response...................................... 110
Scratchpad ........................................................... 110
Identification..........................................................111
Fault Warning and Status...................................... 112
Telemetry.............................................................. 118
NVM Memory Commands .................................... 122
Store/Restore ..................................................... 122
Fault Logging...................................................... 123
Block Memory Write/Read.................................. 127
Package Description ................................... 128
Table25. LTM4683 BGA Pinout.......................... 128
Package Description ................................... 129
Revision History ........................................ 131
Package Photos ......................................... 132
Design Resources ...................................... 132
Related Parts ............................................ 132

LTM4683
4
Rev. 0
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Terminal Voltages
VINnn (Note 4), SVIN_nn, IIN_nn+, IIN_nn−,
VIN_VBIAS, RUNP ........................................ –0.3V to 16V
(SVIN_nn – IIN_nn+), (IIN_nn+– IIN_nn−)....... –0.3V to 0.3V
SWn............................ −1V to 16V, −5V to 16V Transient
INTVCC_nn, VBIAS ......................................... –0.3V to 6V
VOUTn.........................................................–0.3V to 1.0V
VOSNSn+......................................................–0.3V to 1.0V
VOSNSn−..................................................... –0.3V to 0.3V
RUNn, SDA_nn, SCL_nn, ALERT_nn ......... –0.3V to 5.5V
FSWPH_nn_CFG, VOUTn_CFG,
VTRIMn_CFG, ASEL_nn.......................... –0.3V to 2.75V
FA U LTn, SYNC_nn, SHARE_CLK_nn,
WP_nn, PGOODn...................................... −0.3V to 3.6V
COMPna, COMPnb.................................... –0.3V to 2.7V
TSNSn....................................................... –0.3V to 0.8V
n = 0, 1, 2, 3 and nn =01, 23
VDD33_nn and VDD25_nn are outputs not to be driven.
Temperatures
Internal Operating Temperature Range
(Notes 2, 13, 15, 16)............................... –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature... 245°C
(Note 1)
5 6 7 8 9 10 11 12 13 141 432 15
A
B
C
D
E
F
G
H
K
J
L
T
R
P
N
M
U
AB
AA
Y
W
V
VOUT0
GND
GND
GND
GND
RUN0 RUN1
FSWPH_01_CFG
VTRIM3_CFG
VOUT0_CFG
VOUT1_CFG
TOP VIEW
BGA PACKAGE
330-PIN (15mm × 22mm × 5.71mm)
TJMAX = 125°C, θJCtop = 2.8°C/W, θJCbottom = 1.4°C/W, θJA = 4.73°C/W
VOUT1
VOUT2
VOUT3
SW0
SW1
SW3
VIN23
VIN01
SW2
ASEL_01
SHARE_CLK_01
VTRIM0_CFG
VDD25_01 VTRIM1_CFG
VIN_VBIAS
COMP1b
VDD33_01
VOSNS1–
COMP1a VOSNS1+
VOSNS2+
INTVCC_01
SVIN_01
SCL_23 ALERT_23
RUN3
SYNC_23 SDA_23
PGOOD0 PGOOD1
COMP2b COMP2a
RUNP
FAULT0
ALERT_01
SYNC_01
TSNS0
TSNS1
TSNS3
SVIN_23 INTVCC
_23
COMP0b COMP0a
IN_01+VOSNS0–
IN_01–
IN_23–
VOSNS2–
TSNS2
IN_23+
VOSNS0+
PGOOD2 VOSNS3+
PGOOD3 VOSNS3–
FAULT2COMP3a
FAULT3COMP3b
VDD33_23 WP_23
VBIAS
SGND_01
SGND_23
FAULT1
RUN2
SDA_01
VOUT3_CFG
SCL_01
WP_01
VDD25_23
VTRIM2_CFG
FSWPH_23_CFG
VOUT2_CFG
SHARE_CLK_23
ASEL_23
NOTES:
1) θVALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS, WEIGHT = 6.4g (TYP.).
2) θJA VALUE IS OBTAINED WITH DEMO BOARD.
3) SEE THERMAL CONSIDERATIONS AND OUTPUT CURRENTDERATING FOR LAB MEASUREMENT
AND DERATING INFORMATION.
ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH
PART MARKING PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)DEVICE FINISH CODE
LTM4683EY#PBF SAC305 (RoHS) LTM4683Y e1 BGA 4 –40°C to 125°C
LTM4683IY#PBF SAC305 (RoHS) LTM4683Y e1 BGA 4 –40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings

LTM4683
5
Rev. 0
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn = 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VINnn Input DC Voltage Test Circuit 1
Test Circuit 2, VIN_OFF < VIN_ON = 4V
l
l
5.75
4.5
14
5.75
V
V
VOUTnRange of Output Voltage Regulation
for Each Channel
VOUTnDifferentially Sensed on VOSNSn+/VOSNSn– Pin-Pair,
Commanded by Serial Bus or with Resistors Present at
Start-Up on VOUTn_CFG
l 0.3 0.7 V
VOUTn(DC) Output Voltage, Total Variation with
Line and Load for Each Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
VOUTnCommanded to 0.5V, VOUTnLow Range,
(MFR_PWM_MODEn[1] = 1b), (Notes 5, 6)
l0.4965
0.492
0.50
0.50
0.5035
0.508
V
V
VUVLO Undervoltage Lockout Threshold,
When VIN < 4.3V
VINTVCC_nn Falling
VINTVCC_nn Rising
3.55
3.90
V
V
Input Specifications
IINRUSH(VINnn)Input Inrush Current at Start-Up Test Circuit 1, VOUTn= 0.5V, VIN = 12V, No Load Besides
Capacitors; TON_RISEn= 3ms
200 mA
IQ(SVINnn)Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn= RUNP = 3.3V
Shutdown, RUN0n= RUNP = 0V
40
23
mA
mA
IS(VINnn,PSM) Input Supply Current in Pulse-
Skipping Mode Operation
Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b,
IOUTn= 100mA
20 mA
IS(VINnn,FCM) Input Supply Current in Forced
Continuous Mode Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b,
12V to 0.5V, IOUT = 31.25A, RUNP = 0V, VBIAS = Off
1.8 A
IS(VINnn,SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUNn= 0V, RUNP = 0V, VBIAS = Off 300 µA
Output Specifications
IOUTnOutput Continuous Current Range
Each Channel
(Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using
~IOUT = 40A for IOUT_OC_FAULT_LIMIT, Page 96
0 31.25 A
∆VOUTn(LINE)
VOUTn
Line Regulation Accuracy
Each,Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
SVIN and VINnElectrically Shorted Together and INTVCC
Open Circuit;IOUTn= 0A, 5.75V ≤ VIN ≤ 14V, VOUT Low Range,
(MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH =
425kHz, (Note 5)
l
0.03
0.03 ±0.2
%/V
%/V
∆VOUTn(LOAD)
VOUTn
Load Regulation Accuracy
Each,Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0A ≤ IOUTn≤ 31.25A, VIN ≥ 5.75V, VOUT Low Range,
(MFR_PWM_MODEn[1] = 1b), (Notes 5, 6)
l
0.03
0.2 0.5
%
%
VOUTn(AC) Output Voltage Ripple 10 mVP-P
fS(Each Channel) VOUTnRipple Frequency FREQUENCY_SWITCH Set to 350kHz (0xFABC) l325 350 375 kHz
∆VOUTn(START) Turn-On Overshoot TON_RISEn= 3ms (Note 12) 8 mV
tSTART Turn-On Start-Up Time Time from VIN Toggling from 0V to 12V to Rising Edge
PGOODn. TON_DELAYn= 0ms, TON_RISEn= 3ms
l35 ms
tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUNnto Rising Edge of
PGOODn. TON_DELAYn= 0ms, TON_RISEn= 3ms,
VIN Having Been Established for at Least 70ms
2.75 3.3 3.8 ms
∆VOUTn(LS) Peak Output Voltage Deviation for
Dynamic Load Step
Load: 10A to 30A and 30A to 10A at 10A/µs,
VOUTn= 0.50V, VIN = 12V (Note 12)
30 mV
tSETTLE Settling Time for Dynamic Load Step
per Channel
Load: 10A to 30A and 30A to 10A at 10A/µs,
VOUTn= 0.50V, VIN = 12V, (Note 12)
18 µs

LTM4683
6
Rev. 0
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn= 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOUTn(OCL_PK) Output Current Limit, Peak High
Range per Channel
Cycle-by-Cycle Inductor Peak Current Limit Inception,
Utilizing MFR_PWM_MODE[7] = 1, Using IOUT = 41.75A
for IOUT_OC_FAULT_LIMIT, Page 96
45 A
IOUTn(OCL_AVG) Output Current Limit, Time Averaged
per Channel
Time-Averaged Output Inductor Current Limit Inception
Threshold, Commanded by IOUT_OC_FAULT_LIMITn,
(Note 12), Utilizing MFR_PWM_MODE[7] = 1, Using
~IOUT = 41.75A, Page 96
40A, See IOUT-RB-ACC
Specification (Output Current
Readback Accuracy)
Control Section
VFBCMnChannel 0 to Channel 3 Feedback
Input Common Mode Range
VOSNSn–Valid Input Range (Referred to SGND)
VOSNSn+Valid Input Range (Referred to SGND)
l
l
–0.1 0.3
1.0
V
V
VOUT-RNGL Full-Scale Command Voltage, Range
Low (0.3V to 2.75V) per Channel;
Limit to 1V (Note 14)
VOUTnCommanded to 2.750V, MFR_PWM_MODEn[1] = 1b
Set Point Accuracy
Resolution
LSB Step Size
l
l
2.7
−0.5
12
0.688
2.8
+0.5
V
%
Bits
mV
RVSNSn+VOSNSn+Impedance to SGND 0.3V ≤ VVOSNSn+– VSGND ≤ 1.0V 50 kΩ
tON(MIN) Minimum On-Time (Note 8 ) per Channel 85 ns
RCOMPnResolution
Compensation Resistor RTH(MAX)
Compensation Resistor RTH(MIN)
MFR_PWM_COMP[4:0] = 0 to 31 (See Figure1,
NoteSection)
5
62
0
Bits
kΩ
kΩ
gmnResolution
Error Amplifier gm(MAX)
Error Amplifier gm(MIN)
LSB Step Size
VCOMP = 1.35V, MFR_PWM_COMP[7:5] = 0 to 7 3
5.76
1
0.68
Bits
mmho
mmho
mmho
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
NOV/UV_COMP Resolution, Output Voltage
Supervisors
(Notes 13, 14) 9 Bits
VOV-RNG Output OV Comparator Threshold
Detection Range
High Range Scale Not Used, Low Range Scale,
MFR_PWM_MODEn[1] = 1b (Note 14)
0.3 2.7 V
VOUSTP Output OV and UV Comparator
Threshold Programming LSB Step Size
(Note 14),
Low Range Scale, MFR_PWM_MODEn[1] = 1b 5.6 mV
VOV-ACC-nOutput OV Comparator Threshold
Accuracy Channel 0 to Channel 3
(Note 13)
0.3V ≤ VVOSNSn+– VVOSNSn–≤ 0.7V, MFR_PWM_MODEn[1] = 1b l±5 %
VUV-RNGnOutput UV Comparator Threshold
Detection Range
Low Range Scale, MFR_PWM_MODEn[1] = 1b,
High Range Scale N/A, Output Limited to 0.7V 0.3 2.7
V
VUV-ACCnOutput UV Comparator Threshold
Accuracy Channel 0 to Channel 3
(Note 13)
0.3V ≤ VVOSNSn+– VVOSNSn–≤ 0.7V, MFR_PWM_MODE[1] = 1b l±5 %
tPROP-OV Output OV Comparator
ResponseTimes
Overdrive to 10% Above Programmed Threshold 100 µs
tPROP-UV Output UV Comparator
ResponseTimes
Under Drive to 10% Below Programmed Threshold 100 µs

LTM4683
7
Rev. 0
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ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn= 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog OV/UV SVIN_nn Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
NSVIN-OV/UV-COMP SVIN_nn OV/UV Comparator
Threshold-Programming Resolution
(Note 14) 9 Bits
SVIN-OU-RANGE SVIN_nn OV/UV Comparator
Threshold-Programming Range
Limited to Abs Max = 16V l4.5 16 V
SVIN-OU-STP SVIN_nn OV/UV Comparator Threshold-
Programming LSB Step Size
(Note 14) 76 mV
SVIN-OU-ACC SVIN_nn OV/UV Comparator
Threshold Accuracy
9V < SVIN ≤ 16V
4.5V ≤ SVIN ≤ 9V
l
l
±3
±270
%
mV
tPROP-SVIN-HIGH-VIN SVIN_nn OV/UV Comparator
Response Time, High VIN Operating
Configuration
Test Circuit 1, and:
VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V
VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V
l
l
100
100
µs
µs
tPROP-SVIN-LOW-VIN SVIN_nn OV/UV Comparator
Response Time, Low VIN Operating
Configuration
Test Circuit 2, and:
VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V
VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V
l
l
100
100
µs
µs
Channel nOutput Voltage Readback (READ_VOUTn)
NVO-RB Output Voltage Readback Resolution
and LSB Step Size
(Note 14) 16
244
Bits
µV
VO-F/S Output Voltage Full-Scale
Digitizable,Range
VRUNn= 0V, (Note 14), Limited to 1.0V Max Operating 8 V
VO-RB-ACC Output Voltage Readback Accuracy Channel n: 0.3V ≤ VVOSNS+– VVOSNS–< 0.7V l Within±3.5mV of Reading
tCONVERT-VO-RB Output Voltage Readback
Update,Rate
MFR_ADC_CONTROL = 0x00, (Notes 9, 14)
MFR_ADC_CONTROL = 0x01 through 0x0C, (Notes 9, 14),
MFR_ADC_CONTROL Section
90
8
ms
ms
Input Voltage SVIN_nn Readback (READ_VIN)
NSVIN-RB Input Voltage Readback Resolution
and LSB Step Size
(Notes 10, 14), Limited to Abs Max = 16V 10
15.625
Bits
mV
SVIN-F/S Input Voltage Full-Scale
Digitizable,Range
(Notes 11, 14), Limited to 14V Operating 43 V
SVIN-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V ≤ SVIN ≤ 14V lWithin ±2% of Reading
tCONVERT-SVIN-RB Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00, (Notes 9, 14)
MFR_ADC_CONTROL = 0x01, (Notes 9, 14)
90
8
ms
ms
ChannelnOutput Current (READ_IOUTn), Duty Cycle (READ_DUTY_CYCLEn) and Computed Input Current (MFR_READ_IINn) Readback
NIO-RB Output Current Readback Resolution
and LSB Step Size
(Notes 10, 14) 10
34.1
Bits
mA
IOUT-F/S Output Current Full-Scale
Digitizable,Range
(Note 14),
Utilizing MFR_PWM_MODE[7] = 1, Using IOUT_OC_
FAULT_LIMIT = 61A, Page 96
54 A
IOUT-RB-ACC Output Current, Readback Accuracy READ_IOUTn, Channel 0 to Channel 3, 0 ≤ IOUTn≤ 25A,
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
See Histograms in Typical Performance Characteristics,
(Note 12)
lWithin 1.5A of Reading
IOUT-RB (31.25A) Full Load Output Current Readback (Note 12), See Histograms in Typical Performance
Characteristics
31.25 A

LTM4683
8
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn= 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONVERT-IO-RB Output Current Readback
Update,Rate
MFR_ADC_CONTROL = 0x00, (Notes 9, 14)
MFR_ADC_CONTROL = 0x06 (CH0,2 IOUT) or 0x0A (CH1,3
IOUT), (Notes 9, 14), See MFR_ADC_CONTROL SECTION
90
8
ms
ms
Input Current Readback
N Resolution (Note 10) 10 Bits
VIINSTP LSB Step Size Full-Scale Range = 16mV
LSB Step Size Full-Scale Range = 32mV
LSB Step Size Full-Scale Range = 64mV
Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV
Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV
Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV
15.26
30.52
61
µV
µV
µV
IIN_TUE Total Unadjusted Error Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–|, (Note 7)
Gain = 4, 4mV ≤ |VIIN+ – VIIN–|, (Note 7)
Gain = 2, 6mV ≤ |VIIN+ – VIIN–|, (Note 7)
2
1.3
1.2
%
%
%
VOS Zero-Code Offset Voltage (Note 14) ±50 µV
tCONVERT Update Rate (Notes 9,14), See MFR_ADC_CONTROL SECTION for
Faster Update Rates
90 ms
Supply Current Readback (Note 15)
N Resolution (Note 10) 10 Bits
VICHIPSTP LSB Step Size Full-Scale
Range=256mV
Onboard 1Ω Resistor 244 µV
ICHIP_RB ICHIP Readback SVIN_nn Current 50 mA
tCONVERT Update Rate (Notes 9,14), See MFR_ADC_CONTROL SECTION for
Faster Update Rates
90 ms
Temperature Readback (T0, T1)
TRES-RB Temperature Readback Resolution Channel n, and Controller, (Note 14) 0.25 °C
T0_TUE External Temperature Total
Unadjusted Readback Error
Supporting Only ∆VBE Sensing 2.5 °C
T1_TUE Internal TSNS TUE VRUNn= 0V, fSYNC = 0kHz, (Note 7) ±1 °C
tCONVERT Update Rate (Note 9)
MFR_ADC_CONTROL = 0x04, 0x0C, or 0x08 (Notes 9, 14)
90
8
ms
ms
INTVCC_nn Regulator, VBIAS
VINTVCC_nn Internal VCC Voltage No Load 6V ≤ SVIN_nn ≤ 14V l5.25 5.5 5.75 V
VLDO_INT INTVCC Load Regulation ICC = 0mA to 50mA, 6V ≤ SVIN_nn ≤ 14V 0.5 ±2 %
VIN_VBIAS Input Range for VIN_VBIAS 7 14 V
RUNP VBIAS Enable RUNP Rising 0.8 0.85 V
VBIAS 5.5V Internal Regulator 7V ≤ VIN_VBIAS ≤ 14V, VSVIN_nn > 7V 5.25 5.5 5.75 V
SVIN_THR VSVIN_nn Threshold to Enable
VBIASSwitchover
SVIN_nn Rising 7 7.5 V
SVIN_THF VSVIN_nn Threshold to Disable
VBIASSwitchover
SVIN_nn Falling 6.5 V

LTM4683
9
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn= 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD33_nn Regulator
VVDD33nn Internal VDD33 Voltage VINTVCC_nn > 4.5V 3.2 3.3 3.4 V
ILIM VDD33 Current Limit VDD33_nn = GND, VIN_nn = INTVCC_nn = 4.5V 100 mA
VVDD33_OV VDD33 Overvoltage Threshold (Note 14) 3.5 V
VVDD33_UV VDD33 Undervoltage Threshold (Note 14) 3.1 V
VDD25_nn Regulator
VVDD25nn Internal VDD25 Voltage 2.5 V
ILIM VDD25 Current Limit VDD25_nn = GND, VIN_nn = INTVCC_nn = 4.5V 80 mA
Oscillator and Phase-Locked Loop (PLL)
fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC, VIN = 12V 250 750 kHz
fOSC Oscillator Frequency Accuracy Frequency Switch = 250kHz to 1000kHz, (Note 14) l±7.5 %
VTH(SYNC_nn)SYNC Input Threshold (Note 14) VSYNC Falling
VSYNC Rising
1
1.5
V
V
VOL(SYNC_nn)SYNC Low Output Voltage ILOAD = 3mA, (Note 14) 0.2 0.4 V
ILEAK(SYNC_nn)SYNC Leakage Current in
SubordinateMode
0V ≤ VSYNC_nn ≤ 3.6V ±5 µA
θSYNC-θ0,θ2 SYNC to Ch0, Ch2 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW0, SW2
MFR_PWM_CONFIG[2:0] = 0,2,3 (Note 14)
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1,θ3 SYNC to Ch1, Ch3 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW1, SW3
MFR_PWM_CONFIG[2:0] = 3 (Note 14)
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
Endurance (Note 15) 0°C ≤ TJ≤ 85°C During EEPROM Write Operations l10,000 Cycles
Retention (Note 15) TJ< 125°C l10 Years
Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ< 85°C
During EEPROM Write Operation
440 4100 ms
Leakage Current SDA_nn, SCL_nn, ALERT_nn, RUNn
IOL Input Leakage Current OV ≤ VPIN ≤ 5.5V l±5 µA
Leakage Current FAULTn, PGOODn
IGL Input Leakage Current OV ≤ VPIN ≤ 3.6V l±2 µA
Digital Inputs SCL_nn, SDA_nn, RUNn
VIH Input High Threshold Voltage l1.35 V
VIL Input Low Threshold Voltage l0.8 V
VHYST Input Hysteresis SCL, SDA 0.08 V
CPIN Input Capacitance 10 pF
Digital Input WP_nn (Note 14)
IPUWP Input Pull-Up Current WP 10 µA

LTM4683
10
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN, SVIN = 12V, RUNn= 3.3V,
RUNP=12V, FREQUENCY_SWITCH = 425kHz and VOUTncommanded to 0.5V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Open-Drain Outputs SCL_nn, SDA_nn, FAULTn, ALERT_nn, RUNn, SHARE_CLK_nn, PGOODn
VOL Output Low Voltage ISINK = 3mA 0.4 V
Digital Inputs SHARE_CLK_nn, WP_nn (Note 14)
VIH Input High Threshold Voltage l1.5 1.8 V
VIL Input Low Threshold Voltage l0.6 1 V
Digital Filtering of FAULTn (Note 14)
IFLTG Input Digital Filtering FAULTn3 µs
Digital Filtering of PGOODn (Note 14)
IFLTG Output Digital Filtering PGOODn100 µs
Digital Filtering of RUNn (Note 14)
IFLTG Input Digital Filtering RUN 10 µs
PMBus Interface Timing Characteristics (Note 14)
fSCL Serial Bus Operating Frequency l10 400 kHz
tBUF Bus Free Time Between Stop
andStart
l1.3 µs
tHD(STA) Hold Time After Repeated Start
Condition after This Period, the First
Clock is Generated
l0.6 µs
tSU(STA) Repeated Start Condition Setup Time l0.6 10000 µs
tSU(ST0) Stop Condition Setup Time l0.6 µs
tHD(DAT) Date Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3 0.9
µs
µs
tSU(DAT) Data Setup Time
Receiving Data
l
0.1 µs
tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event 32
255
ms
tLOW Serial Clock Low Period l1.3 10000 µs
tHIGH Serial Clock High Period l0.6 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:The LTM4683 is tested under pulsed-load conditions such that
TJ≈TA. The LTM4683E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization, and correlation with statistical process
controls. The LTM4683I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. TJis calculated
fromthe ambient temperature TAand the power dissipation PDaccording
to the following formula: TJ= TA+ (PD• θJA).
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance,
andother environmental factors.
Note 3: All currents into the device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to ground unless
otherwisespecified.
Note 4: The power inputs—VIN01 and VIN23—and their respective power
outputs—VOUT0, 1 and VOUT2, 3—are tested independently in production. A
shorthand notation is used in this document that allows these parameters
to be referred to by “VINnn” and “VOUTn”, where nis permitted to take on
a value of 0 to 3. This italicized “n” notation and convention is extended
to encompass all such pin names, and register names with channel-
specific, i.e., paged data. For example, VOUT_COMMANDnrefers to the
VOUT_COMMAND command code datalocated in Pages 0 and1, which in