Analog Devices ADP50460008 User manual

Compact PMU with Six DC-to-DC Channels,
Two LDOs, Load Switch, and RTC
ADI Confidential
ADP50460008
Rev. Sp0
Information fur
nished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by AnalogDevices for its use, nor for anyinfringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.
FEATURES
Wide input voltage range: 2.1 V to 5.5 V
2.5 MHz switching frequency
Current mode architecture for best transient performance
Internal compensation and soft start
I2C-programmable output levels and power sequencing
PSM mode on Channel 1
Power
Channel 1: synchronous boost regulator, 1.2 A maximum
Channel 2: H-bridge buck-boost regulator, 0.9 A maximum
Channel 3: synchronous buck regulator, 1.8 A maximum
Channel 4: synchronous buck regulator, 0.9 A maximum
Channel 5: 45 mΩ load switch, 0.8 A
Channel 6: synchronous buck regulator, 0.9 A maximum
Channel 7: HV boost regulator for backlight LED,
up to 23.75 V (typical)
Channel 8: LDO regulator, 100 mA maximum
Channel 9: low quiescent current LDO, 50 mA maximum
Auxiliary
Real-time clock (RTC) with backup battery charger
Flexible power sequence control
Reset for external microprocessor
Package
4 mm × 4 mm, 64-ball WLCSP
APPLICATIONS
Digital still cameras
Digital video cameras
Multimedia devices
Space-constrained portable equipment
GENERAL DESCRIPTION
The ADP5046 is a compact, multi-output power management unit
(PMU) designed for space-constrained applications that require
high efficiency power regulation. The device includes a boost,
a buck-boost, and three buck regulators; two LDOs; a backlight
driver; a load switch; and an RTC/backup battery manager. The
total solution size is minimized through a combination of chip scale
packaging; high frequency switches; and the integration of power
FETs, external compensation, and feedback resistors. To ensure
maximum flexibility, the voltage outputs, power sequencing, and
soft start time can be programmed via the I2C interface or set by
factory programming.
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
SUB CPU
32kHz
BACKUP BATTERY
ANALOG
BACKLIGHT LEDs
AUXILIARY
AUXILIARY
I/O
SYSTEM
VCORE
I
2
C
INTERFACE
REGISTER
POWER
SEQUENCER
RTC
LOGIC
BACKUP
BATTERY
CHARGER
RESET
CH 7 BOOST
REGULATOR
CH 6BUCK
REGULATOR
CH5LOAD SWITCH
CH 4BUCK
REGULATOR
CH 3BUCK
REGULATOR
CH 2BUCK-BOOST
REGULATOR
CH 1 SYNC BOOST
REGULATOR
ALARM OUT
RESET OUT CH 8 LDO
REGULATOR
MEMORY
XTAL
OSCILLATOR
CH 9 KEEP ALIVE
LDO
REGULATOR
10847-001
Figure 1.

ADP50460008 ADI Confidential
Rev. Sp0 | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC-to-DC Converter Block Specifications .............................. 5
Linear Regulator Block Specifications....................................... 7
Load Switch Specifications.......................................................... 7
Housekeeping Block Specifications ........................................... 8
I2C Interface Timing Specifications ........................................... 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 18
Introduction ................................................................................ 18
Enable........................................................................................... 18
Wake-Up Sequence .................................................................... 19
Reference Block .......................................................................... 20
32 kHz Oscillator........................................................................ 20
Real-Time Clock (RTC)............................................................. 20
Power-Up Sequencer.................................................................. 21
Countdown Alarm Timer ......................................................... 22
Undervoltage Protection (UVP) and Overvoltage Protection
(OVP)........................................................................................... 23
VREGO Keep Alive LDO Circuit ............................................ 23
UVLO_SYS Circuit .................................................................... 23
UVLO_RTC Circuit................................................................... 23
System Reset for External Processor (POCO) ........................... 24
Backup Battery Charger ............................................................ 24
Backup Memory ......................................................................... 24
I2C Interface ................................................................................ 24
Voltage Regulator Block ............................................................ 26
Housekeeping Block................................................................... 33
Control Register Map..................................................................... 34
Control Register Read/Write and Reset .................................. 35
Control Register Details ............................................................ 36
Applications Information .............................................................. 47
External Component Selection for Buck Regulators............. 47
External Component Selection for the Buck-Boost Regulator
(Channel 2) ................................................................................. 48
External Component Selection for Boost Regulators............ 50
Typical Power Supply for Digital Still Cameras (DSC) ......... 52
Layout and Design Recommendations ................................... 53
Thermal Considerations............................................................ 54
Applications Circuit ................................................................... 55
Trim Settings for the ADP50460008............................................ 56
Factory Programming Defaults................................................ 56
Outline Dimensions ....................................................................... 57
Ordering Guide .......................................................................... 57
REVISION HISTORY
9/12— Revision Sp0: Initial Version

ADI Confidential ADP50460008
Rev. Sp0 | Page 3 of 60
SPECIFICATIONS
TJ= 25°C, VVBATT= VVDD = 3.6 V, VVDDIO = 3.3 V, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.1 3.6 5.5 V Includes VBATT, PVIN2, PVIN3, PVIN4,
PVIN6, VIN8, and VDDIO
Minimum Power-Up V
V BAT T
Voltage V
POWER-UP MIN
2.3 V
QUIESCENT CURRENT
Operating Quiescent Current
VBATT IQ(VBATT_OP1) 13 µA No switching, EN = high
IQ(VBATT_OP2) 20 40 µA No switching, EN = high, VVBATT= 5.5 V
VDD I
Q(VDD_OP1)
3.9 mA No switching, EN = high
I
Q(VDD_OP2)
4.75 7 mA No switching, EN = high, V
VDD
= 5.5 V
Channel 1 Power Save Mode (PSM),
I
VBATT
+ I
VDD
IQ(PSM_OP) 60 µA No switching, EN = low, VVBATT= 3.0 V,
4.2 V, 5.5 V
VDDIO I
Q(VDDIO)
0.25 µA V
VDDIO
= V
SCL
= V
SDA
= 3.3 V
PVIN2 IQ(PVIN2)1 µA No switching, VVBATT= VVDD = VPVIN2 = 3.6 V,
EN = high
PVIN3 IQ(PVIN3)1 µA No switching, VVBATT= VVDD = 3.6 V,
EN = high
PVIN4
I
Q(PVIN45)
1
µA
No switching, V
VBATT
= V
VDD
= 3.6 V,
EN = high
VIN5 I
Q(VIN5)
1 µA V
VBATT
= V
VDD
= 3.6 V
PVIN6 IQ(PVIN6)1 µA No switching, VVBATT = VVDD = 3.6 V,
EN = high
VIN8 I
Q(VIN8)
32 µA No load, V
IN8
= V
OUT8
+ 0.5 V, V
OUT8
= 3.3 V
System Lockout Current, I
VBATT
+ I
VDD
I
Q(LOCKOUT)
2 µA V
VBATT
= V
VDD
= 1.8 V, EN = low
BACKUP BATTERY MODE
BU3INT Operating Quiescent Current
(Backup Battery Mode)
IQ(STNBYBACKUP) 1.5 µA Includes RTCOSC, RTC logic, and
UVLO_RTC;1VVBATT = VVDD = 0 V;
V
BU3INT
= 2.0 V
Lockout Current
(Backup Battery Mode)
IQ(LOCKBACKUP) 0.1 µA Battery voltage disconnected from
VBATT node; VBU3INT = 1.0 V
UVLO
System Undervoltage Lockout
Threshold (Rising)
VUVLO_SYS12.522 2.6 2.75 V See Table 74, Register OPT_UVLO_SYS_R,
Bit 7 (SEL_VTH_R) = 0b
2.2 2.3 2.43 V See Table 74, Register OPT_UVLO_SYS_R,
Bit 7 (SEL_VTH_R) = 1b
Hysteresis V
HSY_UVLO_SYS
0.2 V
VDD Undervoltage Lockout Threshold
(Rising)
VUVLO_VDD 2.19 V
Hysteresis V
HYS(UVLO_VDD)
0.1 V
OSCILLATOR CIRCUIT
Switching Frequency 1 f
SW1
2.125 2.5 2.875 MHz
2 2.5 3 MHz −10°C ≤ T
J
≤ +85°C
Switching Frequency 2
fSW2
1.12
1.25
1.38
MHz
1.0625 1.25 1.4275 MHz −10°C ≤ T
J
≤ +85°C
LOGIC INPUTS
EN Pin
Low Level Threshold V
IL(EN)
0.3 × V
VREGO
V V
VREGO
= 3.2 V, −10°C ≤ T
J
≤ +85°C
High Level Threshold V
IH(EN)
0.7 × V
VREGO
V V
VREGO
= 3.2 V, −10°C ≤ T
J
≤ +85°C
SCL and SDA Pins
Low Level Threshold V
IL(I2C)
0.3 × V
VDDIO
V V
VDDIO
= 3.3 V, −10°C ≤ T
J
≤ +85°C
High Level Threshold V
IH(I2C)
0.7 × V
VDDIO
V V
VDDIO
= 3.3 V, −10°C ≤ T
J
≤ +85°C

ADP50460008 ADI Confidential
Rev. Sp0 | Page 4 of 60
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS
SDA Pin
Low Level Output Voltage V
OL(SDA)
0.4 V 3.0 mA sink current, −10°C ≤ T
J
≤ +85°C
Leakage Current I
LEAK(SDA)
10 nA V
SDA
= 3.3 V
CLKO Pin
Low Level Output Voltage V
OL(CLKO)
0.4 V 3.0 mA sink current, −10°C ≤ T
J
≤ +85°C
High Level Output Voltage V
OH(CLKO)
V
VREGO
− 0.4 V 3.0 mA source current, −10°C ≤ T
J
≤ +85°C
ALMO Pin
Low Level Output Voltage V
OL(ALMO)
0.4 V 3.0 mA sink current, −10°C ≤ T
J
≤ +85°C
High Level Output Voltage V
OH(ALMO)
V
VREGO
− 0.4 V 3.0 mA source current, −10°C ≤ T
J
≤ +85°C
POCO Pin
Low Level Output Voltage V
OL(POCO)
0.4 V 3.0 mA sink current, −10°C ≤ T
J
≤ +85°C
High Level Output Voltage V
OH(POCO)
V
VREGO
− 0.4 V 3.0 mA source current, −10°C ≤ T
J
≤ +85°C
1RTCOSC refers to the XTAL oscillator; RTC logic refers to the alarm function and RTC registers.

ADI Confidential ADP50460008
Rev. Sp0 | Page 5 of 60
DC-TO-DC CONVERTER BLOCK SPECIFICATIONS
TJ= 25°C, VVBATT = VVDD = 3.6 V, VVDDIO = 3.3 V, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 1 BOOST REGULATOR
Channel 1 Output Voltage (V
OUT1
)
Adjustable Range, 3 Bits V
OUT1
3.8 5.3 V
Voltage Accuracy V
OUT1(DEFAULT)
−1.5 +1.5 % Default VID code
−2.5 +2.5 % −10°C ≤ T
J
≤ +85°C
Load Regulation ∆V
OUT1
/I
LOAD
−0.2 %/A I
VOUT1
= 100 mA to 600 mA
Line Regulation ∆V
OUT1
/V
V BAT T
0.1 %/V V
V BAT T
= 2.1 V to 4.5 V
Switching Node (SW1 Pins)
High-Side Power FET, R
DS(ON)
R
DS(ON)1H
100 mΩ I
D
= 100 mA
Low-Side Power FET, R
DS(ON)
R
DS(ON)1L
115 mΩ I
D
= 100 mA
Low-Side Switch Current Limit I
CL1
3 3.4 A −10°C ≤ T
J
≤ +85°C
Minimum Off Time t
OFF1(MIN)
100 ns
Soft Start Time t
SS1
4 ms Default SFTTIM code
Power Save Mode (PSM)
Output Voltage on PSM V
OUT1PSM
3.6 V EN = low
PSM SW1 Low-Side Power FET, RDS(ON)
RDS(ON)2L
1
Ω
ID= 30 mA, EN = low
PSM On Time t
ONPSM1
450 ns V
V BAT T
= 3.0 V
CHANNEL 2 BUCK-BOOST REGULATOR
Channel 2 Output Voltage (V
OUT2
)
Adjustable Range, 3 Bits V
OUT2
3.3 3.65 V
Voltage Accuracy V
OUT2(DEFAULT)
−1.5 +1.5 % Default VID code
−2.5 +2.5 % −10°C ≤ T
J
≤ +85°C
Load Regulation ∆V
OUT2
/I
LOAD
−0.4 %/A I
VOUT2
= 100 mA to 600 mA
Line Regulation ∆V
OUT2
/V
PVIN2
0.1 %/V V
PVIN2
= 2.1 V to 4.5 V
Switching Node (SWA2 Pins)
High-Side Power FET, R
DS(ON)
R
DS(ON)PRI2H
95 mΩ I
D
= 100 mA, V
PVIN2
= 3.6 V
Low-Side Power FET, R
DS(ON)
R
DS(ON)PRI2L
120 mΩ I
D
= 100 mA, V
PVIN2
= 3.6 V
High-Side Switch Current Limit I
CL2
2 2.5 A −10°C ≤ T
J
≤ +85°C
Switching Node (SWB2 Pins)
High-Side Power FET, RDS(ON)
RDS(ON)SEC2H
100
mΩ
ID= 100 mA, VOUT2 = 2.8 V
Low-Side Power FET, R
DS(ON)
R
DS(ON)SEC2L
130 mΩ I
D
= 100 mA, V
OUT2
= 2.8 V
Minimum Off Time t
OFF2(MIN)
100 ns
Soft Start Time t
SS2
4.5 ms Default SFTTIM code
C
OUT
Discharge Switch On Resistance R
DIS2
100 Ω
CHANNEL 3 BUCK REGULATOR
Channel 3 Output Voltage (FB3 Pin)
Adjustable Range, 4 Bits V
FB3
0.96 1.26 V
Feedback Voltage Accuracy at Default VID Code V
FB3(DEFAULT)
−1 +1 % Default VID code
−2.5 +2.5 % −10°C ≤ T
J
≤ +85°C
Load Regulation ∆V
OUT3
/I
LOAD
0.3 %/A I
VOUT3
= 100 mA to 1.4 A
Line Regulation ∆V
OUT3
/V
PVIN3
0.1 %/V V
PVIN3
= 2.1 V to 4.5 V
Switching Node (SW3 Pins)
High-Side Power FET, R
DS(ON)
R
DS(ON)3H
65 mΩ I
D
= 100 mA
Low-Side Power FET, RDS(ON)
RDS(ON)3L
50
mΩ
ID= 100 mA
Switch Current Limit I
CL3
2.3 3 A −10°C ≤ T
J
≤ +85°C
Soft Start Time t
SS3
4 ms Default SFTTIM code
C
OUT
Discharge Switch On Resistance R
DIS3
1 kΩ

ADP50460008 ADI Confidential
Rev. Sp0 | Page 6 of 60
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 4 BUCK REGULATOR
Channel 4 Output Voltage (FB4 Pin)
Adjustable Range, 2 Bits V
FB4
1.60 2.70 V
Feedback Voltage Accuracy at Default VID Code V
FB4(DEFAULT)
−1 +1 % Default VID code
−2
+2
%
−10°C ≤ TJ≤ +85°C
FB4 Load Regulation ∆V
OUT4
/I
LOAD
0.2 %/A I
VOUT4
= 100 mA to 600 mA
FB4 Line Regulation ∆V
OUT4
/V
PVIN4
0.1 %/V V
PVIN4
= 2.1 V to 4.5 V
Switching Node (SW4 Pin)
High-Side Power FET, R
DS(ON)
R
DS(ON)4H
160 mΩ I
D
= 100 mA
Low-Side Power FET, R
DS(ON)
R
DS(ON)4L
130 mΩ I
D
= 100 mA
Switch Current Limit I
CL4
1.2 1.5 A −10°C ≤ T
J
≤ +85°C
Soft Start Time t
SS4
4 ms Default SFTTIM code
C
OUT
Discharge Switch On Resistance R
DIS4
1 kΩ
CHANNEL 6 BUCK REGULATOR
Channel 6 Output Voltage (FB6 Pin)
Adjustable Range, 3 Bits V
FB6
1.46 2.50 V
Feedback Voltage Accuracy at Default VID Code V
FB6(DEFAULT)
−1 +1 % Default VID code
−2 +2 % −10°C ≤ T
J
≤ +85°C
Load Regulation
∆VOUT6/ILOAD
0.4
%/A
IVOUT6 = 100 mA to 600 mA
Line Regulation ∆V
OUT6
/V
PVIN6
0.1 %/V V
PVIN6
= 2.1 V to 4.5 V
Switching Node (SW6 Pin)
High-Side Power FET, R
DS(ON)
R
DS(ON)6H
180 mΩ I
D
= 100 mA
Low-Side Power FET, R
DS(ON)
R
DS(ON)6L
120 mΩ I
D
= 100 mA
Switch Current Limit I
CL6
1.2 1.5 A −10°C ≤ T
J
≤ +85°C
Soft Start Time t
SS6
4 ms Default code
C
OUT
Discharge Switch On Resistance R
DIS6
1 kΩ
CHANNEL 7 BOOST REGULATOR AND LED DRIVER
LSTR7 Pin Sink Current ILSTR7 33.3 mA IID7[4:0] = 00000b,
R
SET7
= 15 kΩ
OVP7 Threshold Voltage V
OVP7
22 23.7 25 V −10°C ≤ T
J
≤ +85°C
SW7 Low-Side Power FET, R
DS(ON)
R
DS(ON)7
450 mΩ I
D
= 50 mA, −10°C ≤ T
J
≤ +85°C
SW7 Switch Current Limit I
CL7
0.45 0.65 A −10°C ≤ T
J
≤ +85°C
SW7 Minimum Off Time t
OFF7(MIN)
60 ns
Channel 7 Soft Start Time from 0 mA to Full Current Limit
1
t
SS7
8 ms Default code
Channel 7 ISET7 Voltage V
ISET
487.5 500 512.5 mV R
SET7
= 15 kΩ
1Soft start time for Channel 7 depends on the forward voltage of the LED used.

ADI Confidential ADP50460008
Rev. Sp0 | Page 7 of 60
LINEAR REGULATOR BLOCK SPECIFICATIONS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 8 LDO
Output Voltage Adjustable Range, 3 Bits V
OUT8
1.5 3.5 V V
VIN8
= V
OUT8
+ 0.5 V
Voltage Accuracy at Default VID Code V
OUT8(DEFAULT)
−1.5 +1.5 % V
VIN8
= V
OUT8
+ 0.5 V
−2.5 +2.5 % V
VIN8
= V
OUT8
+ 0.5 V, −10°C ≤ T
J
≤ +85°C
Load Regulation ∆V
OUT8
/I
LOAD
0.002 %/mA I
VOUT8
= 1 mA to 100 mA, V
VIN8
= V
OUT8
+ 0.5 V
Line Regulation ∆V
OUT8
/V
VIN8
0.02 %/V V
VIN8
= (V
OUT8
+ 0.5 V) to 5.5 V, I
VOUT8
= 1 mA
Power Supply Reject Ratio PSRR 50 dB f = 1 kHz, V
OUT8
= 3.40 V, V
VIN8
= V
OUT8
+ 0.5 V
Output Noise OUT
NOISE
300 µV rms 10 Hz to 100 kHz, V
OUT8
= 3.40 V
Dropout Voltage at 100 mA1V
DROP
110 mV V
OUT8
programmed to 3.40 V
Output Current Limit I
CL8
200 mA V
OUT8
drops 5% from nominal voltage
1Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage.
LOAD SWITCH SPECIFICATIONS
TJ= 25°C, VVBATT = VVDD = 3.6 V, VVDDIO = 3.3 V, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Conditions/Comments
CHANNEL 5 LOAD SWITCH
Load Switch, R
DS(ON)
R
DS(ON)5
45 mΩ I
D
= 100 mA, V
VIN5
= 1.8 V
C
OUT
Discharge Switch On Resistance R
DIS5
1 kΩ

ADP50460008 ADI Confidential
Rev. Sp0 | Page 8 of 60
HOUSEKEEPING BLOCK SPECIFICATIONS
TJ= 25°C, VVBATT = VVDD = 3.6 V, VVDDIO = 3.3 V, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit Conditions/Comments
CHANNEL 9 LDO
Keep Alive LDO Operating Quiescent Current I
Q(VDD)
4.3 µA No load, V
VDD
= 3.6 V
Keep Alive LDO Output Voltage VVREGO1 3.135 3.2 3.265 V IVREGO = 1 mA, VIN = VOUT + 0.5 V,
−10°C ≤ T
J
≤ +85°C
VVREGO22.94 3.0 3.06 V IVREGO = 1 mA, −10°C ≤ TJ≤ +85°C,
V
VDD
= V
VREGO
+ 0.5 V
Current Limit Threshold I
REGO LIM
75 115 155 mA −10°C ≤ T
J
≤ +85°C
Keep Alive LDO Load Regulation ∆V
VREGO
/I
LOAD
0.04 %/mA 10 µA < I
VREGO
< 50 mA, V
VDD
= 5.0 V
Keep Alive LDO Line Regulation ∆VVREGO/VVDD 0.01 %/V VVDD = (VVREGO + 0.5 V) to 5.5 V,
I
VREGO
= 1 mA
Keep Alive LDO PSRR V
VREGO
PSRR 40 dB f = 1 kHz
KEEP ALIVE LDO RESET ( POCO )
Keep Alive LDO RESET Voltage Threshold (Rising)1
V
TH(POCO)
2.8
V
Hysteresis1
V
HYS(POCO)
0.2
V
End of RESET Delay Time t
DLY(POCO)
4 ms
BACKUP BATTERY CHARGER
Backup Battery Charger Output Voltage V
BU3INT
3.0 V I
BU3INT
= 1 µA
Backup Battery Connect Switch On Resistance, M1 R
CONREGO
110 Ω
REAL-TIME CLOCK (RTC)
RTC Operating Voltage Range
VBU3INT
1.6
3.3
V
RTC Oscillator Start-Up Time t
START
0.4 sec
RTC CLK Frequency Error −5 +5 ppm
SEQUENCER AND SUPERVISORY CIRCUIT
Undervoltage Protection Threshold V
UVP
67 %
Overvoltage Protection Threshold V
OVP
125 %
Undervoltage Protection Latch Delay t
DLY( UV )
200 ms
Overvoltage Protection Latch Delay t
DLY(OVP)
1.2 ms
Programmable Enable Delay Range, 4 Bits t
DLY
0 30 ms
Default Enable Delay Time from EN to Channel 1 On t
DLY1(DE FAULT )
0 ms
Default Enable Delay Time from EN to Channel 3 On t
DLY3(DEFAULT)
12 ms
Default Enable Delay Time from EN to Channel 2 On t
DLY2(DEFAULT)
16 ms
Default Enable Delay Time from EN to Channel 8 On t
DLY8(DEFAULT)
16 ms
Default Enable Delay Time from EN to Channel 6 On t
DLY6(DEFAULT)
22 ms
Default Off Delay Time from Channel 2 Shutdown to
Channel 3 Shutdown
t
OFFDLY(2)
,
t
OFFDLY(3)
30
ms
1Detected at the VREGO pin.

ADI Confidential ADP50460008
Rev. Sp0 | Page 9 of 60
I2C INTERFACE TIMING SPECIFICATIONS
TJ= 25°C, VVBATT = VVDD = 3.6 V, VVDDIO = 3.3 V, unless otherwise noted.
Table 6.
Parameter Min Typ Max Unit Description
f
SCL
400 kHz SCL clock frequency
t
HIGH
0.6 µs SCL high time
t
LOW
1.3 µs SCL low time
t
SU,DAT
100 ns Data setup time
t
HD,DAT
0 0.9 µs Data hold time1
t
SU,STA
0.6 µs Setup time for repeated start
t
HD,STA
0.6 µs Hold time for start or repeated start
t
BUF
1.3 µs Bus-free time between a stop condition and a start condition
t
SU,STO
0.6 µs Setup time of a stop condition
t
R
20 + 0.1C
B
2300 ns Rise time of SCL and SDA
t
F
20 + 0.1C
B
2300 ns Fall time of SCL and SDA
t
SP
0 50 ns Pulse width of suppressed spike
C
B2
400 pF Capacitive load for each bus line
1A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the
SCL falling edge.
2B of CBis the total capacitance of one bus line in picofarads (pF).
Timing Diagram
SS
P
Sr
S = START CONDITION
Sr = REPEATED START CONDITION
P= STOP CONDITION
SCL
SDA
tHD,DAT
tSU,DAT tHD,STA
tSU,STA tSU,STO
tHIGH
tRtFtFtSP tR
tLOW tBUF
10847-002
Figure 2. I2C Interface Timing Diagram

ADP50460008 ADI Confidential
Rev. Sp0 | Page 10 of 60
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VBATT to GND −0.3 V to +6.5 V
VREGO to GND
−0.3 V to +6.5 V
VDD to GND −0.3 V to +6.5 V
VDDIO to GND −0.3 V to +6.5 V
PVIN2 to PGND2 −0.3 V to +6.5 V
PVIN3 to PGND3 −0.3 V to +6.5 V
PVIN4 to PGND4 −0.3 V to +6.5 V
PVIN6 to PGND6 −0.3 V to +6.5 V
PVIN7 to PGND7 −0.3 V to +6.5 V
VIN5 to GND −0.3 V to +3.6 V
VIN8 to GND −0.3 V to +6.5 V
VOUT1 to PGND1 −0.3 V to +6.5 V
VOUT2 to PGND2 −0.3 V to +6.5 V
VOUT5 to GND −0.3V to VIN5 + 0.3 V
PGNDx to GND −0.3 V to +0.3 V
SW1 to PGND1 −0.5 V to +6.5 V
SWA2 to PGND2 −2.0 V to +6.5 V
SWB2 to PGND2 −0.5 V to +6.5 V
SW3 to PGND3
−2.0 V to +6.5 V
SW4 to PGND4 −2.0 V to +6.5 V
SW6 to PGND6 −2.0 V to +6.5 V
SW7 to PGND7 −0.5 V to +27 V
OVP7 to GND −0.3 V to +27 V
LSTR7 to BLGND7 −0.3 V to +6.5 V
ISET7 to GND −0.3 V to VDD + 0.3 V
BLGND7 to GND −0.3 V to +0.3 V
EN to GND −0.3 V to +6.5 V
I
VIN5
to I
VOUT5
1 A
FB3 to GND −0.3 V to +6.5 V
FB4 to GND
−0.3 V to +6.5 V
FB6 to GND −0.3 V to +6.5 V
BU3INT to RTCGND −0.3 V to +3.6 V
XIN and XOUT to RTCGND −0.3 V to BU3INT + 0.3 V
CLKO to GND −0.3 V to VREGO + 0.3 V
SCL and SDA to GND −0.3 V to VDDIO + 0.3 V
POCO to GND −0.3 V to VREGO + 0.3 V
ALMO to GND −0.3 V to VREGO + 0.3 V
TEST1 to GND −0.3 V to VDD + 0.3 V
TEST2 to GND −0.3 V to VDD + 0.3 V
TEST3 to GND −0.3 V to VDD + 0.3 V
TEST4 to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Operating Ambient Temerature Range −25°C to +85°C
Operating Junction Temperature Range
1
−25°C to +125°C
1To guarantee reliability, it is recommended that the ADP5046 not be operated
with an average TJof >90°C for an extended period of time.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case conditions; that is, a device
soldered in a circuit board for surface-mount packages. Note
that actual θJA depends on the application environment.
Table 8. Thermal Resistance
PCB Type
1
θ
JA
2
Unit
1S0P 60.6 °C/W
2S2P 26.9 °C/W
1PCB type conforms to JEDEC51-9.
21.25 W power dissipation.
ESD CAUTION

ADI Confidential ADP50460008
Rev. Sp0 | Page 11 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
A
B
C
D
E
F
G
H
2345678
SW7 PGND7 BLGND7 VIN5 VOUT5 PGND3 SW3 PVIN3
PVIN2 PVIN2 OVP7 LSTR7 DL3 PGND3 SW3 PVIN3
SWA2 SWA2 ISET7 TEST4 TEST3 FB3 VIN8 VOUT8
PGND2 PGND2 ALMO VDDIO GND GND VOUT1 VOUT1
SWB2 SWB2 TEST2 SDA SCL VDD SW1 SW1
VOUT2 VOUT2 EN TEST1 VBATT VREGO SW1 SW1
PVIN6 FB6 FB4 POCO CLKO RTCGND PGND1 PGND1
SW6 PGND6 PGND4 SW4 PVIN4 XOUT XIN BU3INT
10847-003
Figure 3. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin
No. Mnemonic Description
1A SW7 Switching Node for Channel 7 (Boost Regulator and LED Driver). Leave this pin open if Channel 7 is not used.
1B PVIN2 Input Power Supply for Channel 2 (Buck-Boost Regulator).
1C SWA2 Primary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
1D PGND2 Power Ground for Channel 2 (Buck-Boost Regulator).
1E SWB2 Secondary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
1F VOUT2 Output Voltage for Channel 2 (Buck-Boost Regulator).
1G PVIN6 Input Power Supply for Channel 6 (Buck Regulator).
1H
SW6
Switching Node for Channel 6 (Buck Regulator).
2A PGND7 Power Ground for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
2B PVIN2 Input Power Supply for Channel 2 (Buck-Boost Regulator).
2C SWA2 Primary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
2D PGND2 Power Ground for Channel 2 (Buck-Boost Regulator).
2E SWB2 Secondary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
2F VOUT2 Output Voltage for Channel 2 (Buck-Boost Regulator).
2G FB6 Feedback for Channel 6 (Buck Regulator).
2H PGND6 Power Ground for Channel 6 (Buck Regulator).
3A BLGND7 Analog Ground for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
3B OVP7 Overvoltage Sensing for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
3C
ISET7
LED Current Reference for Channel 7 (Boost Regulator and LED Driver). Leave this pin open if Channel 7 is not used.
3D ALMO Alarm Output. This pin can be connected to an external processor. This pin is also a VREGO domain CMOS output.
Leave this pin open if ALMO is not used.
3E TEST2 Test Pin. Connect to ground.
3F EN Enable. Logic high turns on the PMU.
3G FB4 Feedback for Channel 4 (Buck Regulator).
3H PGND4 Power Ground for Channel 4 (Buck Regulator).

ADP50460008 ADI Confidential
Rev. Sp0 | Page 12 of 60
Pin
No. Mnemonic Description
4A VIN5 Input Power Supply for Channel 5 (Load Switch).
4B LSTR7 LED String Sink for Channel 7
(Boost Regulator and LED Driver). This pin connects to the cathode side of the LED string.
Connect this pin to ground if Channel 7 is not used.
4C TEST4 Test Pin. Connect to ground.
4D VDDIO Supply Voltage for the I
2
C Interface. This pin is typically connected externally to the Channel 2 output.
4E SDA Data Input/Output for the I2C Interface.
4F TEST1 Test Pin. Connect to ground.
4G
POCO
RESET Output for Sub-CPU. Leave this pin open if POCO is not used. This pin is also a VREGO domain CMOS output.
4H
SW4
Switching Node for Channel 4 (Buck Regulator).
5A VOUT5 Output Voltage for Channel 5 (Load Switch).
5B DL3 Channel 3 External FET Gate Driver. Leave this pin open if the external NFET is not used.
5C TEST3 Test Pin. Connect to ground.
5D GND Ground.
5E SCL Clock Input for the I2C Interface.
5F VBATT Power Supply Input for the Internal Circuits.
5G CLKO 32 kHz Clock Buffered Output. Leave this pin open if the 32 kHz output is not used. This pin is also a VREGO domain
CMOS output.
5H PVIN4 Input Power Supply for Channel 4 (Buck Regulator).
6A PGND3 Power Ground for Channel 3 (Buck Regulator).
6B
PGND3
Power Ground for Channel 3 (Buck Regulator).
6C FB3 Feedback for Channel 3 (Buck Regulator).
6D GND Ground.
6E VDD Power Supply. Connect to Channel 1 output through a 0.1 Ω/10 µF RC filter.
6F VREGO Keep Alive LDO Output.
6G RTCGND Ground for RTC. This pin is internally connected to GND. Do not connect this pin to the power ground plane of the PCB.
6H XOUT Real-Time Clock Crystal Driver Output. Bypass with a compensation capacitor to RTCGND. Connect this pin to ground
if the 32 kHz oscillator is not used.
7A SW3 Switching Node for Channel 3 (Buck Regulator).
7B SW3 Switching Node for Channel 3 (Buck Regulator).
7C VIN8 Power Supply Input for Channel 8 (LDO Regulator). Connect this pin to ground if Channel 8 is not used.
7D VOUT1 Output Voltage for Channel 1 (Boost Regulator).
7E SW1 Switching Node for Channel 1 (Boost Regulator).
7F SW1 Switching Node for Channel 1 (Boost Regulator).
7G PGND1 Power Ground for Channel 1 (Boost Regulator).
7H XIN Real-Time Clock Crystal Driver Input. Bypass with a compensation capacitor to RTCGND. Connect this pin to ground
if the 32 kHz oscillator is not used.
8A
PVIN3
Input Power Supply for Channel 3 (Buck Regulator).
8B PVIN3 Input Power Supply for Channel 3 (Buck Regulator).
8C VOUT8 Output Voltage for Channel 8 (LDO Regulator). Leave this pin open if Channel 8 is not used.
8D VOUT1 Output Voltage for Channel 1 (Boost Regulator).
8E SW1 Switching Node for Channel 1 (Boost Regulator).
8F SW1 Switching Node for Channel 1 (Boost Regulator).
8G PGND1 Power Ground for Channel 1 (Boost Regulator).
8H BU3INT Power Supply for the Real-Time Clock XTAL Oscillator and Associated Logic. Connect a capacitor of 1 µF minimum to
RTCGND. If the 32 kHz oscillator is not used, leave this pin open with only the capacitor connected.

ADI Confidential ADP50460008
Rev. Sp0 | Page 13 of 60
TYPICAL PERFORMANCE CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
110 100
OUTPUT CURRENT (mA)
EFFICIENCY(%)
V
IN
= 4.5V
V
IN
= 2.6V V
IN
= 3.6V
10847-004
Figure 4. Efficiency, Channel 1 (PSM), VOUT1= 3.6 V
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
OUTPUT CURRENT (mA)
EFFICIENCY(%)
VIN= 4.5V
VIN= 2.6V
VIN= 3.6V
10847-005
Figure 5. Efficiency, Channel 1 (PWM), VOUT1= 5.0 V
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
OUTPUT CURRENT (mA)
EFFICIENCY(%)
VIN= 4.5V
VIN= 2.6V
VIN= 3.6V
10847-006
Figure 6. Efficiency, Channel 2, VOUT2= 3.3 V
0
10
20
30
40
50
60
70
80
90
100
10 1000100 10,000
OUTPUT CURRENT (mA)
EFFICIENCY(%)
VIN= 4.5V
VIN= 2.6V
VIN= 3.6V
10847-007
Figure 7. Efficiency, Channel 3, VOUT3= 1.1 V
0
10
20
30
40
50
60
70
80
90
100
10010 1000
OUTPUT CURRENT (mA)
EFFICIENCY(%)
VIN= 4.5V
VIN= 2.6V
VIN= 3.6V
10847-008
Figure 8. Efficiency, Channel 4, VOUT4= 2.7 V
10010 1000
0
10
20
30
40
50
60
70
80
90
100
OUTPUT CURRENT (mA)
EFFICIENCY(%)
VIN= 4.5V
VIN= 2.6V
VIN= 3.6V
10847-009
Figure 9. Efficiency, Channel 6, VOUT6= 1.8 V

ADP50460008 ADI Confidential
Rev. Sp0 | Page 14 of 60
0
10
20
30
40
50
60
70
80
90
100
010 20 30 40
OUTPUT CURRENT (mA)
V
IN
= 3.6V
V
IN
= 2.6V
V
IN
= 4.5V
NOTES
1. THE OUTPUT VOLTAGE DEPENDS ON THE
FORWARD VOLTAGE (V
F
) OF THE LEDs.
EFFICIENCY (%)
10847-010
Figure 10. Efficiency, Channel 7 with Four White LEDs Connected in Series
(Output Voltage Depends on the Forward Voltage (VF) of the LEDs)
3.50
3.55
3.60
3.65
3.70
110 100
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
10847-011
Figure 11. Load Regulation, Channel 1 (PSM), VOUT1 = 3.6 V
4.90
4.92
4.94
4.96
4.98
5.00
5.02
5.04
5.06
5.08
5.10
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
110 100 1000
10847-012
Figure 12. Load Regulation, Channel 1 (PWM), VOUT1 = 5.0 V
3.32
3.32
3.30
3.28
3.26110 100 1000
OUTPUT CURRENT (mA)
OUTPUT VOTAGE (V)
10847-013
Figure 13. Load Regulation, Channel 2, VOUT2 = 3.3 V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
1.088
1.092
1.096
1.100
1.104
1.108
1.112
1.116
10 100 1000 10,000
10847-014
Figure 14. Load Regulation, Channel 3, VOUT3= 1.1 V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
2.63
2.65
2.67
2.69
2.71
2.73
2.75
2.77
110 100 1000
10847-015
Figure 15. Load Regulation, Channel 4, VOUT4= 2.70 V

ADI Confidential ADP50460008
Rev. Sp0 | Page 15 of 60
OUTPUT CURRENT (mA)
1.78
1.79
1.80
1.81
1.82
OUTPUT VOLTAGE (V)
110 100 1000
10847-016
Figure 16. Load Regulation, Channel 6, VOUT6= 1.8 V
3.30
3.35
3.40
3.45
3.50
110 100
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
10847-017
Figure 17. Load Regulation, Channel 8, VOUT8= 3.4 V
2ms/DIV
EN
VOUT2
VOUT3
VOUT6
EN 2V/DIV
VOUT2 2V/DIV VOUT3 1V/DIV
VOUT6 2V/DIV
10847-018
Figure 18. Soft Start, VOUT2, VOUT3, and VOUT6
1µs/DIV
I
2
C ON
V
OUT1
SCL
SDA
V
OUT4
V
OUT5
CHANNEL7
SDA 5V/DIV
SCL 5V/DIV V
OUT1
2V/DIV
V
OUT4
2V/DIV
V
OUT5
2V/DIV CHANNEL7 5V/DIV
10847-019
Figure 19. Soft Start, VOUT1, VOUT4, VOUT5, and Channel 7 Output

ADP50460008 ADI Confidential
Rev. Sp0 | Page 16 of 60
500mA
10mAV
OUT1
I
LOAD
I
LOAD
V
OUT1
400µs/DIV
V
OUT1
50mV/DIV
I
LOAD
250mA/DIV
C
OUT
= 44µF ±180mV
L= 2.2µH
10847-020
Figure 20. Load Transient Channel 1 (PWM), VOUT1 = 5.0 V, 10 mA to 500 mA
500mA
10mAV
OUT2
I
LOAD
I
LOAD
V
OUT2
400µs/DIV
V
OUT2
100mV/DIV
I
LOAD
250mA/DIV
C
OUT
= 10µF ±200mV
L= 2.2µH
10847-021
Figure 21. Load Transient Channel 2, VOUT2 = 3.3 V, 10 mA to 500 mA
800mA
10mAV
OUT3
I
LOAD
I
LOAD
V
OUT3
400ms/DIV
V
OUT3
50mV/DIV
I
LOAD
250mA/DIV
C
OUT
= 44µF ±50mV
L= 1.0µH
10847-022
Figure 22. Load Transient Channel 3, VOUT3 = 1.1 V, 10 mA to 800 mA
500mA
10mAV
OUT4
I
LOAD
I
LOAD
V
OUT4
400µs/DIV
V
OUT4
50mV/DIV
I
LOAD
250mA/DIV
C
OUT
= 10µF ±100mV
L= 2.2µH
10847-023
Figure 23. Load Transient Channel 4, VOUT4 = 2.7 V, 10 mA to 500 mA
500mA
10mAV
OUT6
I
LOAD
I
LOAD
V
OUT6
400µs/DIV
V
VOUT6
50mV/DIV
I
LOAD
250mA/DIV
C
OUT
= 22µF, ±100mV
L= 2.2µH
10847-024
Figure 24. Load Transient Channel 6, VOUT6 = 1.8 V, 10 mA to 500 mA
100mA
10mAV
OUT8
I
LOAD
400µs/DIV
V
OUT8
20mV/DIV
I
LOAD
50mA/DIV
C
OUT
= 22µF ±40mV
V
OUT8
I
LOAD
10847-025
Figure 25. Load Transient Channel 8, VOUT8 = 3.4 V, 10 mA to 100 mA

ADI Confidential ADP50460008
Rev. Sp0 | Page 17 of 60
4.2V
2.6V
V
IN
V
OUT1
V
IN
400µs/DIV
V
OUT1
50mV/DIV
V
IN
1V/DIV
C
OUT
= 22µF
L= 2.2µH ±150mV
V
OUT1
10847-026
Figure 26. Line Transient, Channel 1 (PWM), VOUT1 = 5.0 V, 10 mA
4.2V
2.6V
V
IN
V
OUT2
400µs/DIV
V
VOUT2
100mV/DIV
V
IN
1V/DIV
C
OUT
= 10µF
L= 2.2µH ±300mV
V
OUT2
V
IN
10847-027
Figure 27. Line Transient, Channel 2, VOUT2 = 3.3 V, 10 mA
4.2V
2.6V
400µs/DIV
V
OUT3
50mV/DIV
V
IN
1V/DIV
C
OUT
= 44µF
L= 1µH
±80mV
V
IN
V
OUT3
V
OUT3
V
IN
10847-028
Figure 28. Line Transient, Channel 3, VOUT3 = 1.1 V, 10 mA
4.2V
2.6V
400µs/DIV
V
OUT4
100mV/DIV
V
IN
1V/DIV
C
OUT
= 10µF
L= 2.2µH ±100mV
V
IN
V
OUT4
V
OUT4
V
IN
10847-029
Figure 29. Line Transient, Channel 4, VOUT4 = 2.7 V, 10 mA
4.2V
2.6V
V
IN
V
OUT6
400µs/DIV
V
OUT6
50mV/DIV
V
IN
1V/DIV
C
OUT
= 22µF
L= 2.2µH ±100mV
V
OUT6
V
IN
10847-030
Figure 30. Line Transient, Channel 6, VOUT6 = 1.8 V, 10 mA

ADP50460008 ADI Confidential
Rev. Sp0 | Page 18 of 60
THEORY OF OPERATION
INTRODUCTION
The ADP5046 is a highly integrated power management unit
(PMU) that features six switching regulators, two LDOs, a load
switch, a backup battery charger, a real-time clock, and a 32 kHz
oscillator. The PMU can be activated by a logic level high on the
EN pin or following an alarm event that is generated by the
countdown timer.
The ADP5046 also includes a slave-only I2C interface for
communication with an external processor. Through the I2C
interface, it is possible to change parameters, such as the output
voltage, soft start, and sequencing of the regulators, and to set
the RTC registers and the countdown alarm. Some parameters
are factory defined to address different system requirements
that must be available before the system powers up and programs
the PMU registers. Contact an Analog Devices, Inc., representative
for information about the factory programming options that are
available.
ENABLE
The enable pin (EN) controls the on and off states of the ADP5046.
A high logic level on the EN pin turns the device on, whereas
a low logic level turns the device off.
A low-to-high transition on the EN pin starts the activation circuit
by enabling the reference block after three 32 kHz clock cycles.
Then the activation circuit checks for fault conditions, such as
the VVDD voltage being below the threshold, the temperature
being too high, the oscillator not running, and the reference
voltage being below the nominal level. If no fault is detected, the
power-up sequence is generated after the turn-on delay time,
which is factory programmed for each regulator channel.
The default power-up sequence of the regulators is Channel 2
first, Channel 3 second, Channel 6 third, and Channel 8 fourth,
while Channel 1 stays in PSM mode. No regulator sequence is
generated when the device is turned off (EN = low) except the
Channel 1 PSM mode. All the active regulators, except Channel 3,
are turned off simultaneously. Channel 3 is turned off after the
disable delay time (default = 30 ms), upon a high-to-low
transition at the EN pin.
The ADP5046 can also turn on after the countdown timer
decrements to 0 and an alarm is generated. Then Bit 6
(TIMEOUT) in Register RTCAL_HR (Address 35) is
set to 1.
EN_REF
VDD
EN
VREGO
LEVEL
SHIFTER POWER
CONTROL
VDD
REF_GOOD
TO
SEQUENCER
10847-031
Figure 31. Enable Circuit
EN
INTERNAL
REF ENABLE
TYP3 CLK
REF_GOOD TYP4 CLK
CHANNEL1 ON
2 CLK + ENABLE
DELAY TIME
MIN 500µs
DISABLE
DELAY TIME
10847-032
Figure 32. Enable Timings

ADI Confidential ADP50460008
Rev. Sp0 | Page 19 of 60
WAKE-UP SEQUENCE
The ADP5046 wake-up sequence is shown in Figure 33. Wake-up
starts when the main battery voltage rises above the system under-
voltage level (UVLO_SYS). The ADP5046 remains in standby
mode as long as the EN pin is set to a logic level low. In this
mode, the PSM boost regulator and the low quiescent current
regulator keep alive LDO are active.
A high logic level at the EN pin initiates the turn-on sequence,
which starts by checking that there are no fault conditions and
that the internal biasing circuits have reached the nominal
operating conditions.
If the state machine does not detect a fault condition, the
regulator turn-on sequence begins after the enable turn-on
delay has elapsed.
The regulators (except Channel 4, Channel 5, and Channel 7)
turn on according to the predefined timing sequence. The
ADP5046 remains in the wake-up state as long as the EN pin is
at logic level high and no undervoltage condition is detected.
An undervoltage condition triggers the power-down sequence
(instant shutoff system), where the active regulators are turned
off and the ADP5046 waits for a new activation from the EN pin.
UVLO?
STANDBY?
ENABLE DELAY
ON
POCO
MAIN BATTERY
CONNECT
VBATT < UVLO_SYS
VBATT > UVLO_SYS
KEEPALIVE LDO
AND
CHANNEL1 (PSM)
ON
EN = L
EN = L
EN = H
EN = H
REF_GOOD
OK?
TEMP < 160°C
VDD > 2.19V
VREF > 1.0V
TEMP > 160°C
VDD < 2.19V
VREF < 1.0V
EVENT TIMER
0.5s
CH 2, CH 3,
CH 6 (OPT),
CH 8 (OPT) ON
WAKE-UP
OPERATION?
DISABLE DELAY
ON
CH 2, CH 3,
CH 6, CH 8 OFF
OVP? UVP?
V
OVP
>125%
V
OVP
<125%
V
UVP
<67%
V
UVP
>67%
OVPDELAY
ON UVPDELAY ON
YES
NO
YES
NO
YES
NO
YES
NO
YES
NO
YES
NO
10847-033
Figure 33. Wake-Up Sequence

ADP50460008 ADI Confidential
Rev. Sp0 | Page 20 of 60
REFERENCE BLOCK
The reference block contains the voltage reference circuit. It also
monitors the overtemperature, the switching oscillation, the power
supply, and the reference voltage; and it is activated by a logic
high at the EN pin or by a countdown timer alarm event. The
REF_GOOD signal enables the sequencer.
REF_GOOD SEQUENCER
OVERTEMP
OSC_GOOD
UVLO_VDD
VREF_OK
15 CLOCKS
UVLO_VDD
10847-034
Figure 34. Internal Reference Control
Table 10. Conditions for REF_GOOD Generation
Status Signal Conditions
OVERTEMP Overtemperature.
High: temperature < 140°C.
Low: temperature > 160°C.
OSC_GOOD Switching oscillation.
High: 15 clocks after the VVDD voltage is above the
threshold.
Low: the oscillator did not start.
UVLO_VDD Power supply.
High: 2.19 V rising.
Low: 2.06 V falling.
VREF_OK Reference voltage.
High: reference voltage > 1.00 V.
32 kHz OSCILLATOR
The oscillator circuit uses an external 32.768 kHz crystal and
two small capacitors to generate the clock signal that is used as
a time base for the RTC block. The buffered 32 kHz clock signal
is available at a dedicated pin (CLKO), and it is used as a reference
signal for external circuits. The CLKO logic level high is defined
by the voltage of the VREGO pin. Note that the ground connection
for the two capacitors should be directly to the RTCGND pin and
not to any other ground plane on the PCB.
CLKO
RTC
OSCILLATOR
XIN
XOUT
RTC LOGIC
RESET BU3INT
RESET
BU3INT
VREGO
LEVEL
SHIFTER
BU3INT VDD
BU3INTBU3INT
RESET BU3INT
TO
REGISTER
POCO
RTCGND
10847-035
Figure 35. 32 kHz Generation and Distribution
The 32 kHz oscillator has a dedicated calibration register
(Register RTCADJ, Address 40) to fine-tune the frequency (see
Table 54). The value that is written in Register RTCADJ, Bits[5:0],
is the correction amount in parts per million (ppm). The
calibration range is ±61 ppm. Bit 6 (ADJS) in Register RTCADJ
sets the correction sign (0 = frequency decrease, 1 = frequency
increase).
REAL-TIME CLOCK (RTC)
The RTC block keeps track of the elapsed time, and it operates
as long as either the main battery voltage (VVBATT) or the backup
battery voltage (VBU3INT) is above the respective UVLO level.
When the voltage supplying the RTC block is below the under-
voltage threshold (UVLO_RTC), all registers are cleared to 0.
The RTC block has 33 bits that are capable of counting up to
100 years. The following registers support the RTC date and
time:
•RTCT_SEC for seconds, from 0 to 59
•RTCT_MIN for minutes, from 0 to 59
•RTCT_HR for hours, from 0 to 23
•RTCT_DAY for days, from 0 to 30
•RTCT_MO for months, from 0 to 11
•RTCT_YR for years, from 0 to 127
•RTCT_WK for day of the week, from 0 to 6
The year register (Register RTCT_YR, Address 38) contains the
offset value, starting from the Year 2000 (RTCT_YR = 0).
All RTC registers are both read and write. After the first power-up,
all RTC registers are set to 0. The RTC block includes leap year
adjustments.
RTC
OSCILLATOR FREQ DIVIDER COMPENSATION
CONTROL
I
2
C
SEC MIN HOUR DAY MONTH YEARWEEK
SCL
SDA
1Hz
XIN
XOUT
REGISTERS
10847-036
Figure 36. Real-Time Clock Block Diagram