Analog Devices ADT7473 User manual

dBCool®Remote Thermal
Monitor and Fan Controller
ADT7473
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties thatmay result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic TMIN control mode optimizes system acoustics
intelligently
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium®4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully ROHS compliant
GENERAL DESCRIPTION
The ADT7473 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise sensitive or power
sensitive applications requiring active system cooling. The
ADT7473 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique dynamic TMIN control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution can
be monitored using the THERM input. The ADT7473 also
provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
FUNCTIONAL BLOCK DIAGRAM
04686-001
BAND GAP
EFERENCE
VALUE AND
R
10-BIT
ADC
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
GND
PWM1
PWM2
AU
FAN SPEED
C
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEM NTE
CONTROL
TOMATIC
ONTROL
D
C
YNAMIC
T
MIN
ONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANC
MONITORING
E
THERM
INPUT
SIGNAL
CONDITION GIN
AND
ANALOG
MULTIPLEXER
V
CC
TO ADT7473
V
CC
D1+
D1–
D2+
D2–
V
CCP
BAND GAP
TEMP SENSOR
SRC
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
SERIAL BUS
INTERFACE
S
C
LSD
A
SMBALERT
ADT7473
Figure 1.

ADT7473
Rev. A | Page 2 of 76
T
Fe
G
Sp
Ab
Pi
Ty
Serial Bus Interface..................................................................... 11
Write Operations ........................................................................ 12
Read Operations ......................................................................... 13
SMBus Timeout .......................................................................... 13
nput...................................................... 13
................... 13
VCCP Limit Registers ................................................................... 14
Additional ADC Functions for Voltage Measurements ........ 14
Temperature Measurement Method ........................................ 15
Series Resistance Cancellation.................................................. 17
Factors Affecting Diode Accuracy ........................................... 17
Additional ADC Functions for Temperature Measurement 19
Li
ABLE OF CONTENTS
atures .............................................................................................. 1
eneral Description......................................................................... 1
Functional Block Diagram .............................................................. 1
ecifications..................................................................................... 4
Timing Diagram ........................................................................... 5
solute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
n Configuration and Function Descriptions............................. 7
pical Performance Characteristics ............................................. 8
Product Description....................................................................... 10
Comparison Between ADT7467 and ADT7473 .................... 10
How to Set the Functionality of Pin 9...................................... 10
Recommended Implementation............................................... 10
Voltage Measurement I
Analog-to-Digital Converter .................................................... 13
Input Circuitry .........................................................
Voltage Measurement Registers................................................ 13
mits, Status Registers, and Interrupts....................................... 20
Limit Values ................................................................................ 20
Interrupt Status Registers .......................................................... 21
THERM Timer ........................................................................... 23
Fan Presence Detect................................................................... 31
Sleep States .................................................................................. 31
XNOR Tree Test Mode .............................................................. 31
Power-On Default ...................................................................... 31
Pr
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 40
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 40
Step 6: TRANGE for Temperature Channels................................ 41
ogramming the Automatic Fan Speed Control Loop ............ 33
Automatic Fan Control Overview............................................ 33
Step 1: Hardware Configuration .............................................. 34
Step 2: Configuring the Mux .................................................... 36
Step 3: T Settings for Thermal Calibration Channels
MIN ...... 38
Step 7: TTHERM for Temperature Channels ............................... 44
Step 8: THYST for Temperature Channels.................................. 45
Step 10: High and Low Limits for Temperature Channels ... 50
Step 11: Monitoring THERM
Dynamic TMIN Control Mode ................................................... 47
Step 9: Operating Points for Temperature Channels............. 49
................................................... 52
Enhancing System Acoustics .................................................... 53
Step 12: Ramp Rate for Acoustic Enhancement..................... 55
Register Tables ................................................................................ 58
Outline Dimensions ....................................................................... 76
Ordering Guide .......................................................................... 76

ADT7473
Rev. A | Page 3 of 76
o Table 1 ............................................................................4
able 3..............................................................................6
parisons Between the ADT7467
tion.....................................................................10
Ch ERT
REVISION HISTORY
2/06—Rev. 0 to Rev. A.
Changes t
Change to T
Changes to Com
and ADT7476 sec
anges to SMBAL Interrupt Behavior Section 21
Changes to Interrupt Mask Register 1 (0x74) Section ...............22
Changes to Fan Drive Using PWM Control................................26
Changes to Reading Fan Speed from the ADT7473...................28
C s to O g G ................76
6/05—Revisi nit l Version
.................
hange rderin uide...........................................
on 0: I ia

ADT7473
Rev. A | Page 4 of 76
SPECIFICATIONS
TAVMIN to VMAX, unless other noted.1
Table 1.
Pa in yp it est Conditions/Comments
= TMIN to TMAX, VCC = wise
rameter M T Max Un T
POWER SUPPLY
Supply Voltage .0 63 3.3 3. V
Supply Current, ICC 1.5 A terface inactive, ADC active3 m In
TE ERTERMP-TO-DIGITAL CONV
Local Sensor Accuracy 0.5 TA≤ 85°C± ±1.5 °C 0°C ≤
±2.5 ≤ TA≤ 125°C°C −40°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy 1.5 ≤ 85°C±0.5 ± °C 0°C ≤ TA
±2.5 ≤ TA≤ +125°C°C −40°C
Resolution 0.25 °C
Remote Sensor Source Current irst current6 µA F
6 econd current3 µA S
6 d current9 µΑ Thir
AN CONVERTER
(IN D ATTENTUATORS)
ALOG-TO-DIGITAL
N
CLUDING MUX A
Total Unadjusted Error (TUE) ±1.5 %
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity 0.1± %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
19 ms Averaging disabled
Input Resistance 70 120 kΩ For VCCP channel
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±6 % 0°C ≤ T ≤ 70°C
A
±10 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5,000 RPM Fan count = 0x0438
10,000 RPM Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA
High Level Output Current, IOH µA VOUT = VCC 0.1 20
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA
High Level Output Current, IOH 0.1 1.0 µA VOUT = VCC
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV

ADT7473
Rev. A | Page 5 of 76
Min Typ Max Unit Test Conditions/CommentsParameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
3.6 V Maximum input voltage
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCC V
Input Low Voltage, VIL 0.4 V
DIGITAL INPUT CURRENT
Input High Current, IIH ±1 µA VIN = VCC
Input Low Current, IIL ±1 µA V = 0
Input Capacitance, CIN 5
IN
pF
SERIAL BUS TIMING See Figure 2
Clock Frequency, fSCLK 10 Hz400 k
Glitch Immunity, tSW 50 ns
Bus Free Time, t 4.7 µs
BUF
SCL Low Time, tLOW 4.7 µs
SCL High Time, tHIGH 4.0 50 µs
SCL, SDA Rise Time, tr1,000 ns
SCL, SDA Fall Time, tf 300 µs
Data Setup Time, tSU;DAT 250 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
ll voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA= 25°C and represent most likely parametric norm. Logic inputs accept input
igh voltages up to VMAX, even when device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a
rising edge.
TIMING DIAGRAM
Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
1A
h
SCL
SD
A
PS
SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
04686-002
Figure 2. Serial Bus Timing Diagram

ADT7473
Rev. A | Page 6 of 76
Table 2.
Parameter Rating
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
ecified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
θJA θJC Unit
Positive Supply Voltage (VCC) 3.6 V
Voltage on Any Input or Output Pin −0.3 V to +3.6 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 260°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD Rating 1500 V
θJA is sp
Package Type
16-Lead QSOP 150 39 °C/W
ESD CAU
ESD (electrostatic dischar s 4000 V readily accumulate on
e human te
oprietary ESD ti
trostatic s. ormance
gradatio of fun
TION
ge) sensitive device. Electrostatic charges as high a
th
pr
body and
protec
st equipment and can discharge without detection. Although this product features
on circuitry, permanent damage may occur on devices subjected to high energy
elec
de
discharge
n or loss
Therefore, proper ESD precautions are recommended to avoid perf
ctionality.

ADT7473
Rev. A | Page 7 of 76
PTIONSPIN CONFIGURATION AND FUNCTION DESCRI
04686-003
12
11
10
9
D1–
D2+
D2–
TACH4/GPIO/THERM/SMBALERT
16
15
14
13
SDA
PWM1/XTO
V
CCP
D1+
5
6
7
8
PWM2/SMBALERT
TACH1
TACH2
PWM3
1
2
3
4
SCL
GND
V
CC
TACH3
ADT7473
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND Ground Pin for the ADT7473.
3 VCC Power Supply. Powered by 3.3 V.
4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
5 PWM2
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulate ontrol Fan 2 speed.
y drive.
d output to c
Can be configured as a high or low frequenc
SMBALERT Digital Output (Open Drain). Can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
7 TACH2 Digital I put (Open Drain). Fan tachometer input to measure speed of Fan 2.n
8 PWM3
Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
GPIO General-Purpose Open Drain Digital I/O.
THERM Bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input as well as to assert when
an ADT7473 THERM overtemperature limit is exceeded. For example, the pin can be connected to the PROCHOT
output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an
output to signal overtemperature conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 oltage (0 V to 3 V).VCCP Analog Input. Monitors processor core v
15 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
XTO Also functions as the output from the XNOR tree in XNOR test mode.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

ADT7473
Rev. A | Page 8 of 76
TYPICAL PERFORMANCE CHARACTERISTICS
60
0 204060
LEAKAGE RESISTANCE (MΩ)
80 10010 30 50 70 90
TEMPERATURE ERROR (°C)
–60
–40
–20
0
20
40
04686-004
D+ TO GND
D+ TO V
CC
Figure 4. Remote Tempera re Error vs. PCB Resistance tu
0
–10
–20
–30
–40
–50
–60
024681012
CAPACITANCE (nF)
TEMPERATURE ERROR (°C)
14 16 18 20 22
04686-006
Figure 5. Temperature Error vs. Capacitance Between D+ and D−
30
25
20
15
10
5
0
–5
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
100mV
60mV
40mV
04686-007
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
40mV
04686-008
–10
60mV
100mV
Figure 7. Remote Temperature Error s. Common-Mode Noise Frequencyv
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0 3.1 3.2 3.3 3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5 3.6
1.00
0.98
04686-009
Figure 8. Normal IDD vs. Power Supply
100mV
250mV
15
10
5
0
–5
–10
–15
0 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
TEMPERATURE ERROR (
°
C)
04686-010
Figure 9. Internal Temperature Error vs. Frequency

ADT7473
Rev. A | Page 9 of 76
04686
6
-011
4
2
0
–2
–4
–6
TEMPERATURE ERROR (
°
C)
–8
0 100M 200M 300M
FREQUENCY (Hz)
400M 500M 600M
–10
100mV
250mV
–12
Error vs. Power Supply Noise FrequencyFigure 10. Remote Temperature
3.0
2.5
2.0
1.5
1.0
ERROR (°C)
0.5
0
–0.5
TEMPERATURE
–40 –20 0 20 40 60 85
OIL BATH TE
–1.0
–1.5
105 125
04686-012
MPERATURE (°C)
Figure 11. Internal Temperature Error vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
RATURE ERROR (°C)
0
–0.5
MPE
–40 –20 40 60 85
TH TEMPERATURE (°C)
–1.0
–1.5
105 125
04686-013
0 20
OIL BA
TE
–2.0
rature Figure 12. Remote Temperature Error vs. Tempe

ADT7473
Rev. A | Page 10 of 76
ION
s controller has a serial
d
PRODUCT DESCRIPT
The ADT7473 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bu
data line for reading and writing addresses and data (Pin 16),
and an input line for the serial clock (Pin 1). All control an
programming functions for the ADT7473 are performed over
the serial bus. Additionally, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
COMPARISON BETWEEN ADT7467 AND ADT747
The following list shows some comparisons between the
ADT7467 and the ADT7473:
•The ADT7473 can be powered via a 3.3 V supply only, and
does not support 5 V operation, while the AD
3
T7467 does.
n
°C resolution. This is not available on
Violating this specification results in irreversible damage
to the ADT7473. See the ADT7473 Specifications sectio
for more information.
•High frequency PWM drive can be independently selected
for each PWM channel on the ADT7473. This is not
available on the ADT7467.
•The range and resolution of the temperature offset register
can be changed from a ±64°C range at 0.5°C resolution to
a ±128°C range at 1
the ADT7467.
•THERM overtemperature events can be disabled/enabled
individually on each temperature channel. This is not
available on the ADT7467.
•Bit 7 of Configuration Register 1 is no longer supported
because the ADT7473 cannot be powered via a 5 V supply.
•Bit 0 of Configuration Register 1 (0x40) remains writable
after the lock bit is set. This bit enables monitoring.
•2-wire fan speed
ADT7473.
LERT
measurement is not supported on the
HOW TO SET THE FUNCTIONALITY OF PIN 9
Pin 9 on the ADT7473 has four possible functions: SMBA ,
THERM, GPIO, and TACH4. The user chooses the required
functionality by setting Bit 0 and Bit 1 of Configuration
Register 4 (0x7D).
Table 5. Pin 9 Settings
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7473, as shown in Figure 13, allows the
system designer to use the following features:
•
•
•
•
•Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
Three TACH fan speed measurement inputs.
VCC measured internally through Pin 3.
CPU temperature measured using Remote 1 temperature
channel.
Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.
TACH2
PWM3
TACH3
D1+
GND
ADT7473
TACH1
PWM1
CPU FAN
AMBIENT
TEMPERATURE
SMB
04686-015
D1–
SCL
SDA
ALERT
D2+
D2–
THERM
PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
CPU
ure 13. ADT7473 Co
ICH
Fig nfiguration

ADT7473
Rev. A | Page 11 of 76
ed out
-bit serial bus address of 0101110
it from the slave device. Transitions on the data
cur during the low period of the clock signal and
le during the high period, because a low-to-high
hen the clock is high might be interpreted as a stop
mber of data bytes that can be transmitted over
read or write operation is limited only
devices can handle.
a bytes have been read or written, stop conditions
to assert a stop condition. In
d it by
ninth own as No Acknowledge. The
st fore the
th e tenth clock pulse to
er
y rial
s i write
d at
h ontain either one or two
es e byte. To write data to
ress
in
address ta can be written into that register or
ains
an address that is stored in the address pointer register. If data is
written to the d a second data
byte that is written to the register selected by the address
pointer register.
This write operation is shown in Figure 14. The device address
is sent over the bus, and then R/W
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7473 is carri
using the SMBus. The ADT7473 is connected to this bus as a
slave device, under the control of a master controller, which is
usually (but not necessarily) the ICH.
The ADT7473 has a fixed 7
or 0x2E. The read/write bit must be added to get the 8-bit
address (01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge b
line must oc
remain stab
transition w
signal. The nu
the serial bus in a single
by what the master and slave
When all dat
are established. In write mode, the master pulls the data line
high during the tenth clock pulse
rea mode, the master device overrides the acknowledge b
pulling the data line high during the low period before the
clock pulse; this is kn
ma er takes the data line low during the low period be
ten clock pulse, and then high during th
ass t a stop condition.
An number of bytes of data can be transferred over the se
bu n one operation, but it is not possible to mix read and
in one operation, because the type of operation is determine
the beginning and cannot subsequently be changed without
starting a new operation.
In t e ADT7473, write operations c
byt , and read operations contain on
one of the device data registers or read data from it, the add
po ter register must be set so the correct data register is
ed, and then da
read from it. The first byte of a write operation always cont
evice, the write operation contains
is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
•If the ADT7473’s address pointer register value is unknown
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7473, but
only the data byte containing the register address is sent,
because no data is written to the register. This is shown in
Figure 15.
A read operation is then performed consisting of the serial
bus address, R/Wbit set to 1, followed by the data byte
read from the data register. This is shown in Figure 16.
•If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 16.
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7473
R/W
0SDA 10
1110
START BY
MASTER
19
1
ACK. BY
ADT7473
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7473
STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
SCL
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
04686-016
e 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected RegisterFigur

ADT7473
Rev. A | Page 12 of 76
R/W
0
SCL
S
D
A
10
1110D7 D2 D1 D0
ACK. BY STOP BY
19
ACK. BY
ADT7473
D6 D5 D4 D3
ADT7473 MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE
19
04686-017
Pointer Register OnlyFigure 15. Writing to the Address
10 1110D7
Y
R
R/W
0
SCL
SDA D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER
STOP B
MASTE
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE
119
ACK. BY
ADT7473 FRAME 2
DATA BYTE FROM ADT7473
9
04686-018
Figure 16. Reading Data from a Pre
t
t
point y at the correct value. However, it is not
he send byte and receive byte
protocols, the ADT7473 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2 for more
information; this document is available from In l.)
If several read or write operations must be performed in succes-
repeat start condition instead of a
protocols for various
d in
WRITE
viously Selected Register
It is possible to read a data byte from a data register withou
firs writing to the address pointer register, if the address
er register is alread
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
In addition to supporting t
te
sion, the master can send a
stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several
read and write operations. The ADT7473 uses the following
SMBus write protocols. The following abbreviations are use
the diagrams:
S – START
P – STOP
R – READ
W –
A – ACKNOWLEDGE
A– NO ACKNOWLEDGE
d Byte
is operation, the master device sends a single command
Sen
In th
byte to a slave device, as follows:
2.
3. s ACK on SDA.
5.
6. A and the
transaction ends.
used to write a
1. The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (active low).
The addressed slave device assert
4. The master sends a command code.
The slave asserts ACK on SDA.
The master asserts a stop condition on SD
For the ADT7473, the send byte protocol is
register address to RAM for a subsequent single-byte read from
the same address. This operation is illustrated in Figure 17.
04686-019
SLAVE
ADDRESS WASAP
REGISTER
ADDRESS
231564
Figure 17. Setting a Register Address for Subsequent Read
-
asserts a start condition on SDA.
e master sends a command code.
5. The slave asserts ACK on SDA.
6. The master
SDA, and the
en
The single byte write operation is illustrated in Figure 18.
If the master is required to read data from the register immedi
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device
2. The master sends the 7-bit slave address followed by the
write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. Th
sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on
transaction ds.
04686-020
SLAVE
ADDRESS W A DATASA
REGISTER
ADDRESS
23154
AP
678
Figure 18. Single-Byte Write to a Register

ADT7473
Rev. A | Page 13 of 76
eading a single
iste viously set up.
single byte from a
it slave address followed by the
top condition on SDA, and the
ed to read a
a register whose address has previously
tion
READ OPERATIONS
The ADT7473 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly r
register. The reg r address must have been pre
In this operation, the master device receives a
slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-b
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a s
transaction ends.
In the ADT7473, the receive byte protocol is us
single byte of data from
been set by a send byte or write byte operation. This opera
is illustrated in Figure 19.
0
4686-021
SLAVE
ADDRESS DATAARSAP
243156
Figure 19. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
events occur:
•SMBALERT is pulled low.
•The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
•The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
•If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
he alert response address,Once the ADT7473 has responded to t
the master must read the status registers, and the SMBALERT is
o
ents the device from
Bus timeout disabled
REMENT I
ADT7473 has one external vol easurement channel
an also measure its own supp ltage, VCC. Pin 14 can
ure VCCP. The VCC supply volt d
hrough the VCC pin (Pin 3). Th used to
itor a chipset supply voltage in
RTER
ltiplexed into the on-chip, successive
nverter. This has a resolu-
e is 0 V to 2.25 V, but the
easurement of VCCP
e tolerance of
f ¾ full scale
has adequate headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown in
Figure 20. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low-pass filter that gives the input immunity to high frequency
noise.
cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7473 includes an SMBus timeout feature. If there is n
umes the bus isSMBus activity for 35 ms, the ADT7473 ass
locked and releases the bus. This prev
locking or holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so it
can be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0; SMBus timeout enabled (default)
Bit 6 TODIS = 1; SM
VOLTAGE MEASU NPUT
The tage m
and c ly vo
meas age measurement is carrie
out t e VCCP input can be
mon computer systems.
ANALOG-TO-DIGITAL CONVE
All analog inputs are mu
approximation, analog-to-digital co
tion of 10 bits. The basic input rang
input has built-in attenuators to allow m
without any external components. To allow for th
the supply voltage, the ADC produces an output o
(768 decimal or 300 hex) for the nominal input voltage and thus
04686-022
V
CCP
17.5kΩ
52.5kΩ35pF
Figure 20. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Register 0x21 VCCP Reading = 0x00 default
Register 0x22 VCC Reading = 0x00 default

ADT7473
Rev. A | Page 14 of 76
ssoci th the VCCP measureme t channel is a high and
ster. Exceeding the progra high or low limit
riate status bit to b ther limit
SMBALERT
VCCP LIMIT REGISTERS
A ated wi
regi
n
low limit
causes th
mmed
e set. Exce
e approp
can also generate
eding ei
interr
PLow Limit = 0x0
PHigh Limit = 0xF
input ranges of th d output
t ADC.
unning, it samples a tage
put in 711 µs and averages 16 conv ns to reduce noise; a
asurement takes nominally 11.38 s.
ADC FUNCTIONS FOR VOLTAGE
EASUREMENTS
umber of other functions are ava le on the ADT7473 to
ffer the system designer increased f bility.
or each voltage measurement read om a value register,
eadings have actually been mad ternally and the results
being placed into th hen
ns are needed, settin tion
ister 2 (0x73) turns averaging of This effectively gives a
eading 16 times faster (711 µs), but e reading may be noisier.
Bypass Voltage Input Attenuator
ting Bit 5 of Configuration Register 2 (0x73) removes the
on circuitry from the lows the user
directly connect external sen ale the analog
oltage measurement inputs fo ions. The input
nge of the ADC without the a V to 2.25 V.
el ADC Conve
etting Bit 6 of Configuration R 3) places the
to single-channel A n mode. In this
ode, the ADT7473 can be ma gle voltage
hannel only. If the internal AD used, the selected
p t is read every 711 µs. The C channel is
lected by writing to Bits [7:5] of the TACH1 minimum high
yt egister (0x55).
gramming Single- Mode
. 0x55 Channel Selected
upts.
Register 0x46 VCC 0 default
Register 0x47 VCC F default
Table 7 shows the e analog inputs an
codes of the 10-bi
When the ADC is r nd converts a vol
in
me
ersio
m
ADDITIONAL
M
A n ilab
o lexi
Turn-Off Averaging
F fr
16 r e in
averaged before
er conversio
e value register. W
t 4 of Configura
fast
Reg
g Bi
f.
r th
Set
attenuati VCCP input. This al
to sors or to resc
v r other applicat
ra ttenuators is 0
Single-Chann rsion
S egister 2 (0x7
ADT7473 in DC conversio
m de to read a sin
c T7473 clock is
propriate AD
in u ap
se
b e r
Table 6. Pro Channel ADC
Bits [7:5] Reg
001 VCCP
010 VCC
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
C no figuration Register 2 (0
aging off.
it 5 = 1; bypass input attenuators.
it 6 = 1; single-channel conver ode.
7:5] select ADC channel f el convert mode.
x73)
Bit 4 = 1; aver
B
B t m
TACH1 Minimum High Byte Register (0x55)
Bits [ or single-chann

ADT7473
Rev. A | Page 15 of 76
. VIN
ADC Outp
Table 7. 10-Bit ADC Output Codes vs
ut
VCC (3.3 VIN)1VCCP Decimal Binary (10 Bits)
<0.0042 <0.00293 0 00000000 00
0.0042 to 0.0085 0.0293 to 0.0058 1 00000000 01
0.0085 to 0.0128 0.0058 to 0.0087 2 00000000 10
0.0128 to 0.0171 0.0087 to 0.0117 3 00000000 11
0.0171 to 0.0214 0.0117 to 0.0146 4 00000001 00
0.0214 to 0.0257 0.0146 to 0.0175 5 00000001 01
0.0257 to 0.0300 0.0175 to 0.0205 6 00000001 10
0.0300 to 0.0343 0.0205 to 0.0234 7 00000001 11
0.0343 to 0.0386 0.0234 to 0.0263 8 00000010 00
•
•
•
1.100 to 1.1042 9 256 (¼ scale) 01000000 000.7500 to 0.752
•
•
•
2.200 to 2.2042 00 to 1.5029 5 001.50 12 (½ scale) 10000000
•
•
•
3.300 to 3.3042 00 to 2.2529 72.25 68 (¾ scale) 11000000 00
•
•
•
4.3527 to 4.3570 77 to 2.9707 1012.96 3 11111101 01
4.3570 to 4.3613 07 to 2.9736 12.97 014 11111101 10
4.3613 to 4.3656 2.9736 to 2.9765 1015 11111101 11
4.3656 to 4.369 2.9765 to 2.9794 19 016 11111110 00
4.3699 to 4.3742 2.9794 to 2.9824 1017 11111110 01
4.3742 to 4.3785 2.9824 to 2.9853 1018 11111110 10
4.3785 to 4.3828 2 12.9853 to 2.988 019 11111110 11
4.3828 to 4.3871 12.9882 to 2.9912 020 11111111 00
4.3871 to 4.3914 12 to 2.9941 12.99 021 11111111 01
4.3914 to 4.3957 41 to 2.9970 12.99 022 11111111 10
>4.3957 970 1>2.9 023 11111111 11
1The VCC output codes listed a 3 V.
PERATURE MEA METHOD
ple method of meas ture is to exploit the
ve temperature coe de, measuring the base-
oltage (VBE) of a ated at constant
t. Unfortunately, t quires calibration to
t the effect of the f VBE, which varies
The t o measure the change
in VBE when the device is operated at three different currents.
Previous devices have used only two operating currents, but the
use of a third current allows automatic cancellation of resis-
tances in series with the external temperature sensor.
Figure 21 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the collec-
tor is not grounded and should be linked to the base. To prevent
ground noise from interfering with the measurem nt, the more
negativ , but
is biased above ground by an int nal diode at the D− input. C1
can opt axi-
mum value 1000 pF). However, a better option in noisy
ssume that V is 3.
CC
TEM SUREMENT
A sim uring tempera
negati fficient of a dio
emitter v transistor oper
curren his technique re
null ou absolute value o
from device to device.
echnique used in the ADT7473 is t
e
e terminal of the sensor is not referenced to ground
er
ionally be added as a noise filter (recommended m
environments is to add a filter, as described in the Noise
Filtering section.

ADT7473
Rev. A | Page 16 of 76
b in
perating temperature
Local Temperature Measurement
The ADT7473 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip 10-bit ADC.
The 8-bit MSB temperature data is stored in the local tempera-
ture register (0x26). Because both positive and negative
temperatures can e measured, the temperature data is stored
Offset 64 format or twos complement format, as shown in
Table 8 and Table 9. Theoretically, the temperature sensor and
ADC can measure temperatures from −63°C to +127°C (or
−63°C to +191°C in the extended temperature range) with a
resolution of +0.25°C. However, this exceeds the operating
temperature range of the device, so local temperature
measurements outside the ADT7473 o
range are not possible.
Table 8. Twos Complement Temperature Data Format
Temperature Digital Output (10-Bit)1
–128°C 1000 0000 00 (diode fault)
–63°C 1100 0001 00
–50°C 1100 1110 00
–25°C 1110 0111 00
–10°C 1111 0110 00
0°C 0000 0000 00
10.25°C 0000 1010 01
25.5°C 0001 1001 10
50.75°C 0011 0010 11
75°C 0100 1011 00
100°C 0110 0100 00
125°C 0111 1101 00
127°C 0111 1111 00
1 Bold numbers denote 2 LSBs of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Table 9. Extended Range, Temperature Data Format
Temperature Digital Output (10-Bit)1
–64°C 0000 0000 00 (diode fault)
–63°C 0000 0001 00
–1°C 0011 1111 00
0°C 000100 0000
1°C 0100 0001 00
10°C 0100 1010 00
25°C 0101 1001 00
50°C 0111 0010 00
75°C 1000 1001 00
100°C 1010 0100 00
125°C 1011 1101 00
191°C 1111 1111 00
1Bold numbers denote 2 LSBs of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Remote Temperature Measurement
The ADT7473 can measure the temperature of two remote
e is
ensor. This figure shows
o
diode sensors or diode-connected transistors connected to
Pin 10 and Pin 11, or Pin 12 and Pin 13.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device and individual
calibration is required to null this out, so the technique is
unsuitable for mass production. The technique used in the
ADT7473 is to measure the change in VBE when the devic
operated at three different currents. This is given by
( NnqKTV 1/ ×=∆ )
BE
where:
Kis Boltzmann’s constant.
qis the charge on the carrier.
Tis the absolute temperature in Kelvin.
Nis the ratio of the two currents.
Figure 21 shows the input signal conditioning used to measure
the output of a remote temperature s
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors. It could als
be a discrete transistor such as a 2N3904/2N3906.
04686-023
D+
V
DD
TO ADC
V
OUT+
V
OUT–
MOTE
NSING
ISTOR
D–
RE
SE
TRANS
I N1 × IN2 × I I
BIAS
LPF
f
C
= 65kHz
Figure 21. S e Sensors
If a
shou
se ected
h
conn
inpu
ADT
mea
the
not
inte
ignal Conditioning for Remote Diode Temperatur
discrete transistor is used, the collector is not grounded and
ld be linked to the base. If a PNP transistor is used, the
is connected to the D– input and the emitter is connba
to t e D+ input. If an NPN transistor is used, the emitter is
ected to the D– input and the base is connected to the D+
t. Figure 22 and Figure 23 show how to connect the
7473 to an NPN or PNP transistor for temperature
surement. To prevent ground noise from interfering with
measurement, the more negative terminal of the sensor is
referenced to ground, but is biased above ground by an
rnal diode at the D– input.

ADT7473
Rev. A | Page 17 of 76
2
N3904
NPN D+
D–
ADT7473
04686-025
Figure 22. Measuring Temperature Using an NPN Transistor
2
N3906
PNP D–
ADT7473
04686-026
nd then between I and N2 × I,
zed
e
duce
easurements are stored in
s listed in Table 8. The extra
nt,
0 pF.
t.
r
effect
ote sensor is
e result.
he ADT7473 and the remote
environments. Figure 24
e noise and
D+
Figure 23. Measuring Temperature Using a PNP Transistor
To me asure VBE, the operating current through the sensor is
switched among three related currents. N1 × I and N2 × I are
different multiples of the current I, as shown in Figure 21. The
currents through the temperature diode are switched between
I and N1 × I, giving VBE1, a
giving VBE2. The temperature can then be calculated using the
two VBE measurements. This method can also cancel the effect
of any series resistance on the temperature measurement.
The resulting ∆VBE waveforms are passed through a 65 kHz
low-pass filter to remove noise and then to a chopper-stabili
amplifier. This amplifies and rectifies the waveform to produc
a dc voltage proportional to ∆VBE. The ADC digitizes this
voltage, and a temperature measurement is produced. To re
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles.
The results of remote temperature m
10-bit, twos complement format, a
resolution for the temperature measurements is held in the
Extended Resolution Register 2 (0x77). This gives temperature
readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
the D− pin to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature measureme
leading to a recommended maximum capacitor value of 100
This capacitor reduces the noise, but does not eliminate it,
making use of the sensor difficult in a very noisy environmen
The ADT7473 has a major advantage over other devices fo
eliminating the effects of noise on the external sensor. Using the
series resistance cancellation feature, a filter can be constructed
between the external temperature sensor and the part. The
of any filter resistance seen in series with the rem
automatically canceled from the temperatur
The construction of a filter allows t
temperature sensor to operate in noisy
shows a low-pass R-C filter with the following values:
R= 100 Ω, C= 1 nF
This filtering reduces both common-mod
differential noise.
04686-024
1nF
D+
100Ω
REMOTE
T
EMPERATURE
SENSOR
D–
100Ω
Figure 24. Filter Between Remote Sensor and ADT7473
SERIES RESISTANCE CANCELLATION
Parasitic resistance to the ADT7473 D+ and D− inputs (seen in
series with the remote diode) is caused by a variety of factors
including PCB track resistance and track length. This series
resistance appears as a temperature offset in the remote sensor’s
temperature measurement. This error typically causes a 0.5°C offset
per Ω of parasitic resistance in series with the remote diode.
The ADT7473 automatically cancels out the effect of this s
resistanc
eries
e on the temperature reading, giving a more accurate
of this resis-
e Filtering section for details.
sis-
strate. Discrete types can be either PNP or NPN
to the collector).
ase are con-
to D−. If a PNP
o variations in both substrate and
e the
at a
erature, T(°C), when usin does
08. Refer to the da for the related CPU
es.
8)/1.008 × 5 K + T)
result without the need for user characterization
tance. The ADT7473 is designed to automatically cancel up to
3 kΩ of resistance, typically. This is transparent to the user by
using an advanced temperature measurement method. This
feature allows resistances to be added to the sensor path to
produce a filter, allowing the part to be used in noisy
environments. See the Nois
FACTORS AFFECTING DIODE ACCURACY
Remote Sensing Diode
The ADT7473 is designed to work with either substrate tran
tors built into processors or discrete transistors. Substrate
transistors are generally PNP types with the collector connected
to the sub
transistors connected as a diode (base-shorted
If an NPN transistor is used, the collector and b
nected to D+ and the emitter is connected
transistor is used, the collector and base are connected to D−
and the emitter is connected to D+.
To reduce the error due t
discrete transistors, a number of factors should be taken into
consideration:
•The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7473 is trimmed for an nfvalue of 1.008. Us
following equation to calculate the error introduced
temp g a transistor whose nf
not equal 1.0 ta sheet
to obtain the nfvalu
T= (nf− 1.00 (273.1

ADT7473
Rev. A | Page 18 of 76
n, the user can w ∆T value to the
dds it to
anufacturers spe h and low current
rate transisto gh current level of
IHIGH, is 96 µA a low level current,
rent levels do not match
CPU manufacturer, it
a
one
ets must be programmed to the offset register.
ined by choosing devices according to the
Base-emitter voltage gr , at the
highest operating temp
Base-emitter voltage les at the
than 100 Ω
150) that indicates
Nulling Out Temperature Errors
As CPUs run faster, it becomes more difficult to avoid high
frequency clocks when routing the D+/D– traces around a
system board. Even when recommended layout guidelines are
followed, some temperature errors can still be attributable to
noise coupled onto the D+/D– lines. Constant high frequency
noise usually attenuates or increases temperature measurements
by a linear, constant value.
The ADT7473 has temperature offset registers at Register 0x70
and Register 0x72 for the Remote 1 and Remote 2 temperature
channels. By performing a one-time calibration of the system,
the user can determine the offset caused by system board noise
and null it out using the offset registers. The offset registers
automatically add a twos complement, 8-bit reading to every
temperature measurement. The LSBs add +0.5°C offset to the
temperature reading so the 8-bit register effectively allows
temperature offsets of up to ±64°C with a resolution of +0.5°C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)
Register 0x71, Local Temperature Offset = 0x00 (0°C default)
Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)
ards-Compatible Mode
e
e
isters
Register 0x25, Remote 1 Temperature
Register 0x26, Lo
Register 0x27, Remote 2 Temperature
Register 0x77, Extended Resolution 2 = 0x00 default
Bits [7:6] TDM2, Remote 2 temperature LSBs
Bits [5:4] LTMP, local temperature LSBs
Bits [3:2] TDM1, Remote 1 temperature LSBs
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT
To factor this i rite the
offset register. Then, the ADT7473 automatically a
btracts it from the tempe
or su rature measurement.
•Some CPU m cify the hig
levels of the subst rs. The hi
the ADT7473, nd the
ILOW, is 6 µA. If the ADT7473 cur
the current levels specified by the
might be necessary to remove an offset. The CPU’s dat
sheet advises whether this offset needs to be removed and
how to calculate it. This offset can be programmed to the
offset register. It is important to note that, if more than
offset must be considered, the algebraic sum of these
offs
If a discrete transistor is used with the ADT7473, the best
accuracy is obta
following criteria:
•eater than 0.25 V at 6 µA
erature
•s than 0.95 V at 100 µA,
lowest operating temperature
•Base resistance less
•Small variation in hFE (such as 50 to
tight control of VBE characteristics
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
ADT7460/ADT7473 Backw
By setting Bit 1 of Configuration Register 5 (0x7C), all tempera-
ture measurements are stored in the zone temperature value
registers (Register 0x25, Register 0x26, and Register 0x27) in
twos complement, in the range −63°C to +127°C. (The
ADT7473 still makes calculations based on the Offset 64
extended range and clamps the results, if necessary.) The
temperature limits must be reprogrammed in twos comple-
ment. If a twos complement temperature below −63°C is
entered, the temperature is clamped to −63°C. In this mode, th
diode fault condition remains −128°C = 1000 0000, while in th
extended temperature range (−64°C to +191°C), the fault
condition is represented by −64°C = 0000 0000.
Temperature Measurement Reg
cal Temperature
interrupts.
Register 0x4E, Remote 1 Temperature Low Limit = 0x01 default
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Register 0x50, Local Temperature Low Limit = 0x01 default
Register 0x51, Local Temperature High Limit = 0x7F default
Register 0x52, Remote 2 Temperature Low Limit = 0x01 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F
default
Reading Temperature from the ADT7473
It is important to note that the temperature can be read from
the ADT7473 as an 8-bit value (with 1°C resolution) or as a
10-bit value (with 0.25°C resolution). If only 1°C resolution is
required, the temperature readings can be read back at any time
and in no particular order.
If the 10-bit measurement is required, a 2-register read for
each measurement is used. The extended resolution register
(Register 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read, and vice
versa.

ADT7473
Rev. A | Page 19 of 76
functions are available on the ADT7473 to
egister. Sometimes
ake a very fast measurement. Setting Bit 4 of
Register 2 (0x73) turns averaging off.
Measurement Time
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value r
it is necessary to t
Configuration
Table 10. Conversion Time with Averaging Disabled
Channel
Voltage Channel 0.7 ms
Remote 1 Temperature 7 ms
Remote 2 Temper ture 7 msa
Local Temperature 1.3 ms
Table 11. Conversion Time with Averaging Enabled
nt TimeChannel Measureme
Voltage Channels 11 ms
Remote Temperature 39 ms
Local Temperature 12 ms
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7473 into single-channel ADC conversion mode. In
mode, the ADT7473 can be made to read a single tempera
this
ture
writing to Bits [7:5] of the TACH1 minimum high byte register
Temperatures
channel only. The appropriate ADC channel is selected by
(0x55).
Table 12. Programming Single-Channel ADC Mode for
Bits [7:5] Register 0x55 Channel Selected
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Configuration Register 2 (0x73)
um High Byte Register (0x55)
Overtemperature Events
ts on any of the temperature channels can
eed
Bit 4 = 1, averaging off
Bit 6 = 1, single-channel convert mode
TACH1 Minim
Bits [7:5] select ADC channel for single-channel convert mode.
Overtemperature even
be detected and dealt with automatically in automatic fan sp
control mode. Register 0x6A to Register 0x6C are the THERM
limits. When a temperature exceeds its THERM limit, all PWM
t 3
running at this speed until the temperature drops below
outputs run at 100% duty cycle or the maximum PWM duty
cycle (Register 0x38, Register 0x39, and Register 0x3A) if Bi
of Configuration Register 4 (0x7D) is set. The fans remain
THERM minus hysteresis; this can be disabled by setting the
boost bit in Configuration Register 3 (0x78), Bit 2. The
hysteresis value for that THERM limit is the value programmed
).into the hysteresis registers (Register 0x6D and Register 0x6E
The default hysteresis value is 4°C.
FANS
TEMPERATURE
100%
HYSTERESIS (°C)
THERM LIMIT
0
4686-027
Figure 25. THERM Limit Operation

ADT7473
Rev. A | Page 20 of 76
UPTS
73
,
LIMITS, STATUS REGISTERS, AND INTERR
LIMIT VALUES
Associated with each measurement channel on the ADT74
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and is detected by polling the device. Alternatively
SMBALERT interrupts can be generated to flag a processor or
e ADT7473.
Register 0x49, V High Limit = 0xFF default
lt
microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on th
Voltage L i mit Registers
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
CC
Temperature Limit Registers
Register 0x4E, Remote 1 Temperature Low Limit = 0x01 defau
Register 0x4F, Remote 1 Temperature High Limit = 0xFF default
Register 0x6A, Remote 1 THERM Limit = 0xA4 default
Register 0x50, Local Temperature Low Limit = 0x01 default
Register 0x51, Local Temperature High Limit = 0xFF default
Register 0x6B, Local THERM Temperature Limit = 0xA4 default
Register 0x52, Remote 2 Temperature Low Limit = 0x01 default
Register 0x53, Remote 2 Temperature High Limit = 0xFF def
Register 0x6C, Remote 2
ault
THERM Temperature Limit = 0xA4
default
THERM Limit Register
Register 0x7A, THERM Timer Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TAC
limits are also 16
H
bits, consisting of a high byte and low byte.
e
Hs.
e fan TACH period is actually being measured,
ault
ult
lt
um Low Byte = 0xFF default
lt
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
inimum High Byte = 0xFF default
ave been programmed, the ADT7473 can be
toring. The ADT7473 measures all voltage and
d-robin format and sets the
ari-
High limit > comparison performed
Low limit ≤ comparison performed
Voltage and temperature channels use a window comparator for
error detecting and, therefore, have high and low limits. Fan
speed measurements use only a low limit. This fan limit is
needed only in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (0x40). By default,
the ADT7473 p measures
each analog in t is
completed, the result is automatically stored in the appropriate
•One dedicated supply voltage input (VCCP)
Because fans running under speed or stalled are normally th
only conditions of interest, only high limits exist for fan TAC
Because th
exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Register 0x55, TACH1 Minimum High Byte = 0xFF def
Register 0x56, TACH2 Minimum Low Byte = 0xFF defa
Register 0x57, TACH2 Minimum High Byte = 0xFF defau
Register 0x58, TACH3 Minim
Register 0x59, TACH3 Minimum High Byte = 0xFF defau
Register 0x5B, TACH4 M
Out-of-Limit Comparisons
Once all limits h
enabled for moni
temperature measurements in roun
appropriate status bit for out-of-limit conditions. TACH
measurements are not part of this round-robin cycle. Comp
sons are done differently depending on whether the measured
value is being compared to a high or low limit.
owers up with this bit set. The ADC
put in turn and, as each measuremen
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of
interest, because the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated. The total number of channels
measured is
•Supply voltage (VCC pin)
•Local temperature
•Two remote temperatures