Analog Devices ADT7473 User manual

dBCool Remote Thermal Monitor
and Fan Controller
ADT7473/ADT7473-1
Rev. C
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FEATURES
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic TMIN control mode intelligently optimizes system
acoustics
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel Pentium 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully RoHS compliant
GENERAL DESCRIPTION
The ADT7473/ADT7473-1 dBCool® controller is a thermal
monitor and multiple PWM fan controller for noise sensitive
or power sensitive applications requiring active system cooling.
The ADT7473/ADT7473-1 can drive a fan using either a low
or high frequency drive signal, monitor the temperature of up
to two remote sensor diodes plus its own internal temperature,
and measure and control the speed of up to four fans so they
operate at the lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique dynamic TMIN control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution
can be monitored using the THERM input. The ADT7473/
ADT7473-1 also provide critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
04686-001
BAND GAP
REFERENCE
10-BIT
ADC
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
GND
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
SMBus
ADDRESS
SELECTION
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANCE
MONITORING
*THERM_
L
ATCH
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
V
CC
TO ADT7473/ADT7473-1
V
CC
D1+
D1–
D2+
D2–
V
CCP
BAND GAP
TEMP SENSOR
SRC
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
SERIAL BUS
INTERFACE
SCL
*ADDR SELECT*ADDREN SDA SMBALERT
ADT7473/ADT7473-1
*PIN FUNCTION ONLYAVAILABLE ON THE ADT7473-1
Figure 1.

ADT7473/ADT7473-1
Rev. C | Page 2 of 72
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Product Description......................................................................... 9
Comparison Between ADT7467 and ADT7473/ADT7473-1 9
How to Set the Functionality of Pin 9........................................ 9
Recommended Implementation................................................. 9
Serial Bus Interface..................................................................... 10
Write Operations ........................................................................ 12
Read Operations ......................................................................... 13
SMBus Timeout .......................................................................... 13
Voltage Measurement Input...................................................... 13
Analog-to-Digital Converter .................................................... 13
Input Circuitry ............................................................................ 13
Voltage Measurement Registers................................................ 13
VCCP Limit Registers ................................................................... 13
Additional ADC Functions for Voltage Measurements ........ 14
Temperature Measurement Method ........................................ 15
Series Resistance Cancellation.................................................. 17
Factors Affecting Diode Accuracy ........................................... 17
Additional ADC Functions for Temperature Measurement 19
Limits, Status Registers, and Interrupts....................................... 20
Limit Values ................................................................................ 20
Interrupt Status Registers .......................................................... 21
THERM Timer ........................................................................... 23
Fan Drive Using PWM Control ............................................... 25
Fan Presence Detect................................................................... 30
Sleep States .................................................................................. 30
XNOR Tree Test Mode .............................................................. 30
Power-On Default ...................................................................... 31
Programming the Automatic Fan Speed Control Loop ............ 32
Automatic Fan Control Overview............................................ 32
Step 1: Hardware Configuration .............................................. 33
Step 2: Configuring the Mux .................................................... 35
Step 3: TMIN Settings for Thermal Calibration Channels ...... 37
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 38
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 38
Step 6: TRANGE for Temperature Channels................................ 39
Step 7: TTHERM for Temperature Channels ............................... 42
Step 8: THYST for Temperature Channels.................................. 43
Dynamic TMIN Control Mode ................................................... 44
Step 9: Operating Points for Temperature Channels............. 46
Step 10: High and Low Limits for Temperature Channels ... 47
Step 11: Monitoring THERM ................................................... 49
Enhancing System Acoustics .................................................... 50
Step 12: Ramp Rate for Acoustic Enhancement..................... 52
Register Tables ................................................................................ 54
Outline Dimensions ....................................................................... 72
Ordering Guide .......................................................................... 72
REVISION HISTORY
8/07—Rev. B to Rev. C
Changes to Interrupt Status Register 2 (0x42) section .............. 21
Changes to High Frequency Mode PWM Drive section .......... 29
Changes to Table 20........................................................................ 54
Changes to Table 51........................................................................ 67
Changes to Table 61........................................................................ 71
6/07—Rev. A to Rev. B
Added ADT7473-1.............................................................Universal
2/06—Rev. 0 to Rev. A.
Changes to Table 1............................................................................ 4
Change to Table 3 ..............................................................................6
Changes to Comparisons Between the ADT7467
and ADT7476 section .................................................................... 10
Changes to SMBALERT Interrupt Behavior Section ................ 21
Changes to Interrupt Mask Register 1 (0x74) Section............... 22
Changes to Fan Drive Using PWM Control ............................... 26
Changes to Reading Fan Speed from the ADT7473.................. 28
Changes to Ordering Guide.......................................................... 76
6/05—Revision 0: Initial Version

ADT7473/ADT7473-1
Rev. C | Page 3 of 72
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 3.6 V
Supply Current, ICC 1.5 3 mA Interface inactive, ADC active
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Sensor Source Current 6 μA First current
36 μA Second current
96 μΑ Third current
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENTUATORS)
Total Unadjusted Error (TUE) ±1.5 %
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
19 ms Averaging disabled
Input Resistance 70 120 kΩ For VCCP channel
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±6 % 0°C ≤ TA≤ 70°C
±10 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10,000 RPM Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA
High Level Output Current, IOH 0.1 20 μA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
DIGITAL OUTPUT LOGIC LEVELS, ADT7473-1
(THERM_LATCH) ADTL+
Output High Voltage, VOH 0.75 × VCC V
Output Low Voltage, VOL 0.4 V
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV

ADT7473/ADT7473-1
Rev. C | Page 4 of 72
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
3.6 V Maximum input voltage
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCC V
Input Low Voltage, VIL 0.4 V
Input High Voltage, VIH
Input Low Voltage, VIL ±1 μA VIN = VCC
Input Low Current, IIL ±1 μA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING See Figure 2
Clock Frequency, fSCLK 10 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 4.7 μs
SCL Low Time, tLOW 4.7 μs
SCL High Time, tHIGH 4.0 50 μs
SCL, SDA Rise Time, tr1,000 ns
SCL, SDA Fall Time, tf 300 μs
Data Setup Time, tSU; DAT 250 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
1All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA= 25°C and represent most likely parametric norm. Logic inputs accept input
high voltages up to VMAX, even whenthe device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V
for a rising edge.
TIMING DIAGRAM
Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
SDA
PS
SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
04686-002
Figure 2. Serial Bus Timing Diagram

ADT7473/ADT7473-1
Rev. C | Page 5 of 72
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 3.6 V
Voltage on Any Input or Output Pin −0.3 V to +3.6 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 260°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD Rating 1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
16-Lead QSOP 150 39 °C/W
ESD CAUTION

ADT7473/ADT7473-1
Rev. C | Page 6 of 72
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04686-003
12
11
10
9
D1–
D2+
D2–
TACH4/GPIO/THERM/SMBALERT
16
15
14
13
SDA
PWM1/XTO
V
CCP
D1+
5
6
7
8
PWM2/SMBALERT
TACH1
TACH2
PWM3
1
2
3
4
SCL
GND
V
CC
TACH3 ADT7473
TOP VIEW
(Not to Scale)
Figure 3. ADT7473 Pin Configuration
04686-081
12
11
10
9
D1–
D2+
D2–
TACH4/GPIO/THERM/SMBALERT
16
15
14
13
SDA
PWM1/XTO
VCCP
D1+
5
6
7
8
THERM_LATCH/PWM2
TACH1
TACH2
PWM3/ADDREN
1
2
3
4
SCL
GND
VCC
TACH3/ADDR SELECT
ADT7473-1
TOP VIEW
(Not to Scale)
Figure 4. ADT7473-1 Pin Configuration
Table 4. ADT7473/ADT7473-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND Ground Pin.
3 VCC Power Supply. Powered by 3.3 V.
4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
ADDR SELECT If in address select mode, the logic state of this pin defines the SMBus device address.
5 PWM2 Digital Output (Open Drain). ADT7473 default pin function is PWM2. Requires 10 kΩ typical pull-up. Pulse-width
modulated output to control Fan 2 speed. Can be configured as a high or low frequency drive.
SMBALERT On the ADT7473, this pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions.
THERM_LATCH ADT7473-1 default pin function. THERM_LATCH is a thermal event alert signal when an overtemperature
condition occurs.
6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
8 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
ADDREN If pulled low on power-up, the ADT7473-1 enters address select mode, and the state of Pin 4 (ADDR SELECT)
determines the ADT7473-1 slave address.
9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
GPIO General-Purpose Open Drain Digital I/O.
THERM Bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input as well as to assert
when an ADT7473 THERM overtemperature limit is exceeded. For example, the pin can be connected to the
PROCHOT output of an Intel® Pentium® 4 processor or to the output of a trip point temperature sensor. Can be
used as an output to signal overtemperature conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V).
15 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-
up.
XTO Also functions as the output from the XNOR tree in XNOR test mode.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

ADT7473/ADT7473-1
Rev. C | Page 7 of 72
TYPICAL PERFORMANCE CHARACTERISTICS
60
0 204060
LEAKAGE RESISTANCE (MΩ)
TEMPER
A
TURE ERROR (°C)
80 10010 30 50 70 90
–60
–40
–20
0
20
40
04686-004
D+ TO GND
D+ TO V
CC
Figure 5. Remote Temperature Error vs. PCB Resistance
0
–10
–20
–30
–40
–50
–60
0 2 4 6 8 10 12
CAPACITANCE (nF)
TEMPERATURE ERROR (°C)
14 16 18 20 22
04686-006
Figure 6. Temperature Error vs. Capacitance Between D+ and D−
30
25
20
15
10
5
0
–5
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
100mV
60mV
40mV
04686-007
Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
40mV
04686-008
–10
60mV
100mV
Figure 8. Remote Temperature Error vs. Common-Mode Noise Frequency
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0 3.1 3.2 3.3 3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5 3.6
1.00
0.98
04686-009
Figure 9. Normal IDD vs. Power Supply
100mV
250mV
15
10
5
0
–5
–10
–15
0 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
04686-010
Figure 10. Internal Temperature Error vs. Frequency

ADT7473/ADT7473-1
Rev. C | Page 8 of 72
04686-011
6
4
2
0
–2
–4
–6
0 100M 200M 300M
FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
400M 500M 600M
–8
–10
–12
100mV
250mV
Figure 11. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPE
R
A
TURE ERROR (°C)
–1.0
–1.5
105 125
04686-012
Figure 12. Internal Temperature Error vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPE
R
A
TURE ERROR (°C)
–1.0
–1.5
105 125
04686-013
–2.0
Figure 13. Remote Temperature Error vs. Temperature

ADT7473/ADT7473-1
Rev. C | Page 9 of 72
PRODUCT DESCRIPTION
The ADT7473/ADT7473-1 is a complete thermal monitor and
multiple fan controller for any system requiring thermal mon-
itoring and cooling. The device communicates with the system
via a serial system management bus. The serial bus controller
has a serial data line for reading and writing addresses and data
(Pin 16), and an input line for the serial clock (Pin 1). All con-
trol and programming functions for the ADT7473/ADT7473-1
are performed over the serial bus. Additionally, a pin can be
reconfigured as an SMBALERT output to signal out-of-limit
conditions.
Table 5 illustrates the differences between the ADT7473 and the
ADT7473-1.
Table 5. ADT7473/ADT7473-1 Device Comparison
Feature ADT7473 ADT7473-1
Pin 5 Default:
PWM2
Default: THERM_LATCH
SMBus Address Fixed address Address selectable
Remote Ch. 2
Therm. Limit
= 100°C = 136°C
Register 0x30,
0x31, 0x32
Default: 0x00 Default: 0xFF
Register 0x3F
Revision Register
Default: 0x68 Default: 0x69
Register 0x40, Bit 7 Reserved (R/W)
1 = Reset Latch
(lockable)
Register 0x42, Bit 0 Reserved (Read-only)
1 = THERM Limit
Latched
Registers 0x5C,
0x5D, 0x5E
Default: 0x82 Default: 0x62
Register 0x7C, Bit 4 Reserved THERM Output
Hysteresis
Register 0x7D, Bit 4 Reserved THERM_LATCH
Configuration
0 = Remote Channel 2
1 = Remote Channel 1
and Remote Channel 2
COMPARISON BETWEEN ADT7467 AND
ADT7473/ADT7473-1
The following list shows some comparisons between the
ADT7467 and the ADT7473/ADT7473-1:
•The ADT7473/ADT7473-1 can be powered via a 3.3 V
supply only, and does not support 5 V operation, while the
ADT7467 does. Violating this specification results in
irreversible damage to the ADT7473/ADT7473-1. See the
ADT7473/ADT7473-1 Specifications section for more
information.
•A high frequency PWM drive can be independently selected
for each PWM channel on the ADT7473/ADT7473-1. This
is not available on the ADT7467.
•The range and resolution of the temperature offset register
can be changed from a ±64°C range at 0.5°C resolution to a
±128°C range at 1°C resolution. This is not available on the
ADT7467.
•THERM overtemperature events can be disabled/enabled
individually on each temperature channel. This is not
available on the ADT7467.
•Bit 7 of Configuration Register 1 is no longer supported
because the ADT7473/ADT7473-1 cannot be powered via
a 5 V supply.
•Bit 0 of Configuration Register 1 (0x40) remains writable
after the lock bit is set. This bit enables monitoring.
•2-wire fan speed measurement is not supported on the
ADT7473/ADT7473-1.
HOW TO SET THE FUNCTIONALITY OF PIN 9
Pin 9 on the ADT7473/ADT7473-1 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 (0x7D).
Table 6. Pin 9 Settings
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7473 as shown in Figure 14 allows the
system designer to use the following features:
•Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 3.
•CPU temperature measured using Remote 1 temperature
channel.
•Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.

ADT7473/ADT7473-1
Rev. C | Page 10 of 72
04686-015
TACH2
PWM3
TACH3
D1+
D1–
GND
ADT7473
SCL
SDA
TACH1
PWM1
CPU FAN
AMBIENT
TEMPERATURE
SMBALERT
D2+
D2–
THERM
PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
CPU
ICH
Figure 14. ADT7473 Configuration
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7473/ADT7473-1 is
carried out using the SMBus. The ADT7473/ADT7473-1 is
connected to this bus as a slave device, under the control of a
master controller, which is usually (but not necessarily) the ICH.
The ADT7473 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). When the ADT7473-1 is powered up with
Pin 8 (PWM3/ADDREN) high, the ADT7473-1 has a default
SMBus address of 0101110 or 0x2E. If more than one
ADT7473-1 is used in a system, each ADT7473-1 is placed in
ADDR SELECT mode by strapping Pin 8 low on power-up. The
logic state of Pin 4 then determines the device’s SMBus address.
The logic of these pins is sampled on power-up.
The device address is sampled on power-up and latched on
the first valid SMBus transaction, more precisely on the low-to-
high transition at the beginning of the eighth SCL pulse, when
the serial bus address byte matches the selected slave address.
The selected slave address is chosen using the ADDREN pin/
ADDR SELECT pin. Any attempted change in the address
has no effect after this.
Table 7. Hardwiring the ADT7473-1 SMBus Device Address
Pin 8 State Pin 4 Address
0 Low (10 kΩ to GND) 0101100 (0x2C)
0 High (10 kΩ pull-up) 0101101 (0x2D)
1 Don’t care 0101110 (0x2E)
04686-084
ADT7473-1
4
ADDRESS = 0x2E
V
CC
ADDR SELECT
8
PWM3/ADDREN
10kΩ
Figure 15. Default SMBus Address = 0x2E
0
4686-083
ADT7473-1
4
ADDRESS = 0x2C
8
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 16. SMBus Address = 0x2C (Pin4 = 0)
04686-082
ADT7473-1
4
ADDRESS = 0x2D
8
V
CC
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 17. SMBus Address = 0x2D (Pin 4 = 1)