Analog Devices ADT7473 User manual

dBCool Remote Thermal Monitor
and Fan Controller
ADT7473/ADT7473-1
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2007 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic TMIN control mode intelligently optimizes system
acoustics
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel Pentium 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully RoHS compliant
GENERAL DESCRIPTION
The ADT7473/ADT7473-1 dBCool® controller is a thermal
monitor and multiple PWM fan controller for noise sensitive
or power sensitive applications requiring active system cooling.
The ADT7473/ADT7473-1 can drive a fan using either a low
or high frequency drive signal, monitor the temperature of up
to two remote sensor diodes plus its own internal temperature,
and measure and control the speed of up to four fans so they
operate at the lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique dynamic TMIN control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution
can be monitored using the THERM input. The ADT7473/
ADT7473-1 also provide critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
04686-001
BAND GAP
REFERENCE
10-BIT
ADC
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
GND
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
SMBus
ADDRESS
SELECTION
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANCE
MONITORING
*THERM_
L
ATCH
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
V
CC
TO ADT7473/ADT7473-1
V
CC
D1+
D1–
D2+
D2–
V
CCP
BAND GAP
TEMP SENSOR
SRC
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
SERIAL BUS
INTERFACE
SCL
*ADDR SELECT*ADDREN SDA SMBALERT
ADT7473/ADT7473-1
*PIN FUNCTION ONLYAVAILABLE ON THE ADT7473-1
Figure 1.

ADT7473/ADT7473-1
Rev. C | Page 2 of 72
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Product Description......................................................................... 9
Comparison Between ADT7467 and ADT7473/ADT7473-1 9
How to Set the Functionality of Pin 9........................................ 9
Recommended Implementation................................................. 9
Serial Bus Interface..................................................................... 10
Write Operations ........................................................................ 12
Read Operations ......................................................................... 13
SMBus Timeout .......................................................................... 13
Voltage Measurement Input...................................................... 13
Analog-to-Digital Converter .................................................... 13
Input Circuitry ............................................................................ 13
Voltage Measurement Registers................................................ 13
VCCP Limit Registers ................................................................... 13
Additional ADC Functions for Voltage Measurements ........ 14
Temperature Measurement Method ........................................ 15
Series Resistance Cancellation.................................................. 17
Factors Affecting Diode Accuracy ........................................... 17
Additional ADC Functions for Temperature Measurement 19
Limits, Status Registers, and Interrupts....................................... 20
Limit Values ................................................................................ 20
Interrupt Status Registers .......................................................... 21
THERM Timer ........................................................................... 23
Fan Drive Using PWM Control ............................................... 25
Fan Presence Detect................................................................... 30
Sleep States .................................................................................. 30
XNOR Tree Test Mode .............................................................. 30
Power-On Default ...................................................................... 31
Programming the Automatic Fan Speed Control Loop ............ 32
Automatic Fan Control Overview............................................ 32
Step 1: Hardware Configuration .............................................. 33
Step 2: Configuring the Mux .................................................... 35
Step 3: TMIN Settings for Thermal Calibration Channels ...... 37
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 38
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 38
Step 6: TRANGE for Temperature Channels................................ 39
Step 7: TTHERM for Temperature Channels ............................... 42
Step 8: THYST for Temperature Channels.................................. 43
Dynamic TMIN Control Mode ................................................... 44
Step 9: Operating Points for Temperature Channels............. 46
Step 10: High and Low Limits for Temperature Channels ... 47
Step 11: Monitoring THERM ................................................... 49
Enhancing System Acoustics .................................................... 50
Step 12: Ramp Rate for Acoustic Enhancement..................... 52
Register Tables ................................................................................ 54
Outline Dimensions ....................................................................... 72
Ordering Guide .......................................................................... 72
REVISION HISTORY
8/07—Rev. B to Rev. C
Changes to Interrupt Status Register 2 (0x42) section .............. 21
Changes to High Frequency Mode PWM Drive section .......... 29
Changes to Table 20........................................................................ 54
Changes to Table 51........................................................................ 67
Changes to Table 61........................................................................ 71
6/07—Rev. A to Rev. B
Added ADT7473-1.............................................................Universal
2/06—Rev. 0 to Rev. A.
Changes to Table 1............................................................................ 4
Change to Table 3 ..............................................................................6
Changes to Comparisons Between the ADT7467
and ADT7476 section .................................................................... 10
Changes to SMBALERT Interrupt Behavior Section ................ 21
Changes to Interrupt Mask Register 1 (0x74) Section............... 22
Changes to Fan Drive Using PWM Control ............................... 26
Changes to Reading Fan Speed from the ADT7473.................. 28
Changes to Ordering Guide.......................................................... 76
6/05—Revision 0: Initial Version

ADT7473/ADT7473-1
Rev. C | Page 3 of 72
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 3.6 V
Supply Current, ICC 1.5 3 mA Interface inactive, ADC active
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Sensor Source Current 6 μA First current
36 μA Second current
96 μΑ Third current
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENTUATORS)
Total Unadjusted Error (TUE) ±1.5 %
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
19 ms Averaging disabled
Input Resistance 70 120 kΩ For VCCP channel
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±6 % 0°C ≤ TA≤ 70°C
±10 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10,000 RPM Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA
High Level Output Current, IOH 0.1 20 μA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
DIGITAL OUTPUT LOGIC LEVELS, ADT7473-1
(THERM_LATCH) ADTL+
Output High Voltage, VOH 0.75 × VCC V
Output Low Voltage, VOL 0.4 V
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV

ADT7473/ADT7473-1
Rev. C | Page 4 of 72
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
3.6 V Maximum input voltage
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCC V
Input Low Voltage, VIL 0.4 V
Input High Voltage, VIH
Input Low Voltage, VIL ±1 μA VIN = VCC
Input Low Current, IIL ±1 μA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING See Figure 2
Clock Frequency, fSCLK 10 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 4.7 μs
SCL Low Time, tLOW 4.7 μs
SCL High Time, tHIGH 4.0 50 μs
SCL, SDA Rise Time, tr1,000 ns
SCL, SDA Fall Time, tf 300 μs
Data Setup Time, tSU; DAT 250 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
1All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA= 25°C and represent most likely parametric norm. Logic inputs accept input
high voltages up to VMAX, even whenthe device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V
for a rising edge.
TIMING DIAGRAM
Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
SDA
PS
SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
04686-002
Figure 2. Serial Bus Timing Diagram

ADT7473/ADT7473-1
Rev. C | Page 5 of 72
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 3.6 V
Voltage on Any Input or Output Pin −0.3 V to +3.6 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 260°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD Rating 1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
16-Lead QSOP 150 39 °C/W
ESD CAUTION

ADT7473/ADT7473-1
Rev. C | Page 6 of 72
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04686-003
12
11
10
9
D1–
D2+
D2–
TACH4/GPIO/THERM/SMBALERT
16
15
14
13
SDA
PWM1/XTO
V
CCP
D1+
5
6
7
8
PWM2/SMBALERT
TACH1
TACH2
PWM3
1
2
3
4
SCL
GND
V
CC
TACH3 ADT7473
TOP VIEW
(Not to Scale)
Figure 3. ADT7473 Pin Configuration
04686-081
12
11
10
9
D1–
D2+
D2–
TACH4/GPIO/THERM/SMBALERT
16
15
14
13
SDA
PWM1/XTO
VCCP
D1+
5
6
7
8
THERM_LATCH/PWM2
TACH1
TACH2
PWM3/ADDREN
1
2
3
4
SCL
GND
VCC
TACH3/ADDR SELECT
ADT7473-1
TOP VIEW
(Not to Scale)
Figure 4. ADT7473-1 Pin Configuration
Table 4. ADT7473/ADT7473-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND Ground Pin.
3 VCC Power Supply. Powered by 3.3 V.
4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
ADDR SELECT If in address select mode, the logic state of this pin defines the SMBus device address.
5 PWM2 Digital Output (Open Drain). ADT7473 default pin function is PWM2. Requires 10 kΩ typical pull-up. Pulse-width
modulated output to control Fan 2 speed. Can be configured as a high or low frequency drive.
SMBALERT On the ADT7473, this pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions.
THERM_LATCH ADT7473-1 default pin function. THERM_LATCH is a thermal event alert signal when an overtemperature
condition occurs.
6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
8 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
ADDREN If pulled low on power-up, the ADT7473-1 enters address select mode, and the state of Pin 4 (ADDR SELECT)
determines the ADT7473-1 slave address.
9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
GPIO General-Purpose Open Drain Digital I/O.
THERM Bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input as well as to assert
when an ADT7473 THERM overtemperature limit is exceeded. For example, the pin can be connected to the
PROCHOT output of an Intel® Pentium® 4 processor or to the output of a trip point temperature sensor. Can be
used as an output to signal overtemperature conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V).
15 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-
up.
XTO Also functions as the output from the XNOR tree in XNOR test mode.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

ADT7473/ADT7473-1
Rev. C | Page 7 of 72
TYPICAL PERFORMANCE CHARACTERISTICS
60
0 204060
LEAKAGE RESISTANCE (MΩ)
TEMPER
A
TURE ERROR (°C)
80 10010 30 50 70 90
–60
–40
–20
0
20
40
04686-004
D+ TO GND
D+ TO V
CC
Figure 5. Remote Temperature Error vs. PCB Resistance
0
–10
–20
–30
–40
–50
–60
0 2 4 6 8 10 12
CAPACITANCE (nF)
TEMPERATURE ERROR (°C)
14 16 18 20 22
04686-006
Figure 6. Temperature Error vs. Capacitance Between D+ and D−
30
25
20
15
10
5
0
–5
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
100mV
60mV
40mV
04686-007
Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
40mV
04686-008
–10
60mV
100mV
Figure 8. Remote Temperature Error vs. Common-Mode Noise Frequency
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0 3.1 3.2 3.3 3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5 3.6
1.00
0.98
04686-009
Figure 9. Normal IDD vs. Power Supply
100mV
250mV
15
10
5
0
–5
–10
–15
0 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
04686-010
Figure 10. Internal Temperature Error vs. Frequency

ADT7473/ADT7473-1
Rev. C | Page 8 of 72
04686-011
6
4
2
0
–2
–4
–6
0 100M 200M 300M
FREQUENCY (Hz)
TEMPER
A
TURE ERROR (°C)
400M 500M 600M
–8
–10
–12
100mV
250mV
Figure 11. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPE
R
A
TURE ERROR (°C)
–1.0
–1.5
105 125
04686-012
Figure 12. Internal Temperature Error vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPE
R
A
TURE ERROR (°C)
–1.0
–1.5
105 125
04686-013
–2.0
Figure 13. Remote Temperature Error vs. Temperature

ADT7473/ADT7473-1
Rev. C | Page 9 of 72
PRODUCT DESCRIPTION
The ADT7473/ADT7473-1 is a complete thermal monitor and
multiple fan controller for any system requiring thermal mon-
itoring and cooling. The device communicates with the system
via a serial system management bus. The serial bus controller
has a serial data line for reading and writing addresses and data
(Pin 16), and an input line for the serial clock (Pin 1). All con-
trol and programming functions for the ADT7473/ADT7473-1
are performed over the serial bus. Additionally, a pin can be
reconfigured as an SMBALERT output to signal out-of-limit
conditions.
Table 5 illustrates the differences between the ADT7473 and the
ADT7473-1.
Table 5. ADT7473/ADT7473-1 Device Comparison
Feature ADT7473 ADT7473-1
Pin 5 Default:
PWM2
Default: THERM_LATCH
SMBus Address Fixed address Address selectable
Remote Ch. 2
Therm. Limit
= 100°C = 136°C
Register 0x30,
0x31, 0x32
Default: 0x00 Default: 0xFF
Register 0x3F
Revision Register
Default: 0x68 Default: 0x69
Register 0x40, Bit 7 Reserved (R/W)
1 = Reset Latch
(lockable)
Register 0x42, Bit 0 Reserved (Read-only)
1 = THERM Limit
Latched
Registers 0x5C,
0x5D, 0x5E
Default: 0x82 Default: 0x62
Register 0x7C, Bit 4 Reserved THERM Output
Hysteresis
Register 0x7D, Bit 4 Reserved THERM_LATCH
Configuration
0 = Remote Channel 2
1 = Remote Channel 1
and Remote Channel 2
COMPARISON BETWEEN ADT7467 AND
ADT7473/ADT7473-1
The following list shows some comparisons between the
ADT7467 and the ADT7473/ADT7473-1:
•The ADT7473/ADT7473-1 can be powered via a 3.3 V
supply only, and does not support 5 V operation, while the
ADT7467 does. Violating this specification results in
irreversible damage to the ADT7473/ADT7473-1. See the
ADT7473/ADT7473-1 Specifications section for more
information.
•A high frequency PWM drive can be independently selected
for each PWM channel on the ADT7473/ADT7473-1. This
is not available on the ADT7467.
•The range and resolution of the temperature offset register
can be changed from a ±64°C range at 0.5°C resolution to a
±128°C range at 1°C resolution. This is not available on the
ADT7467.
•THERM overtemperature events can be disabled/enabled
individually on each temperature channel. This is not
available on the ADT7467.
•Bit 7 of Configuration Register 1 is no longer supported
because the ADT7473/ADT7473-1 cannot be powered via
a 5 V supply.
•Bit 0 of Configuration Register 1 (0x40) remains writable
after the lock bit is set. This bit enables monitoring.
•2-wire fan speed measurement is not supported on the
ADT7473/ADT7473-1.
HOW TO SET THE FUNCTIONALITY OF PIN 9
Pin 9 on the ADT7473/ADT7473-1 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 (0x7D).
Table 6. Pin 9 Settings
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7473 as shown in Figure 14 allows the
system designer to use the following features:
•Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 3.
•CPU temperature measured using Remote 1 temperature
channel.
•Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.

ADT7473/ADT7473-1
Rev. C | Page 10 of 72
04686-015
TACH2
PWM3
TACH3
D1+
D1–
GND
ADT7473
SCL
SDA
TACH1
PWM1
CPU FAN
AMBIENT
TEMPERATURE
SMBALERT
D2+
D2–
THERM
PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
CPU
ICH
Figure 14. ADT7473 Configuration
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7473/ADT7473-1 is
carried out using the SMBus. The ADT7473/ADT7473-1 is
connected to this bus as a slave device, under the control of a
master controller, which is usually (but not necessarily) the ICH.
The ADT7473 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). When the ADT7473-1 is powered up with
Pin 8 (PWM3/ADDREN) high, the ADT7473-1 has a default
SMBus address of 0101110 or 0x2E. If more than one
ADT7473-1 is used in a system, each ADT7473-1 is placed in
ADDR SELECT mode by strapping Pin 8 low on power-up. The
logic state of Pin 4 then determines the device’s SMBus address.
The logic of these pins is sampled on power-up.
The device address is sampled on power-up and latched on
the first valid SMBus transaction, more precisely on the low-to-
high transition at the beginning of the eighth SCL pulse, when
the serial bus address byte matches the selected slave address.
The selected slave address is chosen using the ADDREN pin/
ADDR SELECT pin. Any attempted change in the address
has no effect after this.
Table 7. Hardwiring the ADT7473-1 SMBus Device Address
Pin 8 State Pin 4 Address
0 Low (10 kΩ to GND) 0101100 (0x2C)
0 High (10 kΩ pull-up) 0101101 (0x2D)
1 Don’t care 0101110 (0x2E)
04686-084
ADT7473-1
4
ADDRESS = 0x2E
V
CC
ADDR SELECT
8
PWM3/ADDREN
10kΩ
Figure 15. Default SMBus Address = 0x2E
0
4686-083
ADT7473-1
4
ADDRESS = 0x2C
8
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 16. SMBus Address = 0x2C (Pin4 = 0)
04686-082
ADT7473-1
4
ADDRESS = 0x2D
8
V
CC
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 17. SMBus Address = 0x2D (Pin 4 = 1)

ADT7473/ADT7473-1
Rev. C | Page 11 of 72
04686-086
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
ADT7473-1
4
8NC
V
CC
10kΩ
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN
8
FLOATING COULD CAUSE THE ADT7473-1 TO POWER UP WITH
A
N UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7473-1 IS PLACED INTO ADDR SELECT
MODE, PINS 8 AND 4 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
ADDR SELECT
PWM3/ADDREN
Figure 18. Unpredictable SMBus Address if Pin 8 is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7473-1 is used in a system.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period because a low-to-high transition when the clock is
high might be interpreted as a stop signal. The number of data
bytes that can be transmitted over the serial bus in a single read
or write operation is limited only by what the master and slave
devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before the
tenth clock pulse, and then high during the tenth clock pulse to
assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7473/ADT7473-1, write operations contain either
one or two bytes, and read operations contain one byte. To write
data to one of the device data registers or read data from it, the
address pointer register must be set so the correct data register
is addressed, and then data can be written into that register or
read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data is
written to the device, the write operation contains a second data
byte that is written to the register selected by the address
pointer register.
This write operation is shown in Figure 19. The device address
is sent over the bus, and then R/Wis set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
•If the ADT7473/ADT7473-1’s address pointer register
value is unknown or not the desired value, it must first be
set to the correct value before data can be read from the
desired data register. This is done by performing a write to
the ADT7473/ADT7473-1, but only the data byte contain-
ing the register address is sent, because no data is written
to the register. This is shown in Figure 20.
A read operation is then performed consisting of the serial
bus address, R/Wbit set to 1, followed by the data byte
read from the data register. This is shown in Figure 21.
•If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 21.
R/W
0
SCL
S
DA 10
1110D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7473/ADT7473-1
START BY
MASTER
19
1
ACK. BY
ADT7473/ADT7473-1
9
D7 D6 D5 D4 D3 D2 D1 D0
STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
0
4686-016
ACK. BY
ADT7473/ADT7473-1
Figure 19. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

ADT7473/ADT7473-1
Rev. C | Page 12 of 72
R/W
0
SCL
SDA 10
1110D7 D6 D5 D4 D3 D2 D1 D0
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
119
ACK. BY
ADT7473/ADT7473-1
9
04686-017
ACK. BY
ADT7473/ADT7473-1
Figure 20. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA 10 1110D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADT7473
119
ACK. BY
ADT7473/ADT7473-1
9
04686-018
Figure 21. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7473/ADT7473-1 also supports the read
byte protocol. (See System Management Bus (SMBus)
Specifications Version 2 for more information; this document is
available from Intel.)
If several read or write operations must be performed in succes-
sion, the master can send a repeat start condition instead of a
stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for various
read and write operations. The ADT7473/ADT7473-1 uses the
following SMBus write protocols. The following abbreviations
are used in the diagrams:
S—Start
P—Stop
R—Read
W—Write
A—Acknowledge
A—No Acknowledge
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7473/ADT7473-1, the send byte protocol is used to
write a register address to RAM for a subsequent single-byte read
from the same address. This operation is illustrated in Figure 22.
04686-019
SLAVE
ADDRESS WASA
REGISTER
ADDRESS
23154
P
6
Figure 22. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA, and the
transaction ends.
The single byte write operation is illustrated in Figure 23.
04686-020
SLAVE
ADDRESS WA DATASA
REGISTER
ADDRESS
23154
AP
678
Figure 23. Single-Byte Write to a Register

ADT7473/ADT7473-1
Rev. C | Page 13 of 72
READ OPERATIONS
The ADT7473/ADT7473-1 uses the following SMBus read
protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been previously set up.
In this operation, the master device receives a single byte from a
slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7473/ADT7473-1, the receive byte protocol is used
to read a single byte of data from a register whose address has
previously been set by a send byte or write byte operation. This
operation is illustrated in Figure 24.
0
4686-021
SLAVE
ADDRESS DATAARSA
24315
P
6
Figure 24. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
events occur:
•SMBALERT is pulled low.
•The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
•The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
•If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
Once the ADT7473/ADT7473-1 has responded to the alert
response address, the master must read the status registers, and
the SMBALERT is cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7473/ADT7473-1 includes an SMBus timeout
feature. If there is no SMBus activity for 35 ms, the ADT7473/
ADT7473-1 assumes the bus is locked and releases the bus.
This prevents the device from locking or holding the SMBus
expecting data. Some SMBus controllers cannot work with the
SMBus timeout feature, so it can be disabled.
Configuration Register 1 (0x40)
Bit 6, TODIS = 0; SMBus timeout enabled (default)
Bit 6, TODIS = 1; SMBus timeout disabled
VOLTAGE MEASUREMENT INPUT
The ADT7473/ADT7473-1 has one external voltage measure-
ment channel and can also measure its own supply voltage, VCC.
Pin 14 can measure VCCP. The VCC supply voltage measurement
is carried out through the VCC pin (Pin 3). The VCCP input can
be used to monitor a chipset supply voltage in computer
systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. (ADC) This has a
resolution of 10 bits. The basic input range is 0 V to 2.25 V, but
the input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of ¾ full scale
(768 decimal or 300 hexadecimal) for the nominal input voltage
and thus has adequate headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown
in Figure 25. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low-pass filter that provides the input immunity to high
frequency noise.
04686-022
V
CCP
17.5kΩ
52.5kΩ35pF
Figure 25. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Register 0x21, VCCP Reading = 0x00 default
Register 0x22, VCC Reading = 0x00 default
VCCP LIMIT REGISTERS
Associated with the VCCP measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default

ADT7473/ADT7473-1
Rev. C | Page 14 of 72
Table 9 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7473/
ADT7473-1 to offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. When
faster conversions are needed, setting Bit 4 of Configuration
Register 2 (0x73) turns averaging off. This effectively gives a
reading 16 times faster (711 µs), but the reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (0x73) removes the
attenuation circuitry from the VCCP input. This allows the user
to directly connect external sensors or to rescale the analog
voltage measurement inputs for other applications. The input
range of the ADC without the attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7473/ADT7473-1 into single-channel ADC conversion
mode. In this mode, the ADT7473/ADT7473-1 can be made to
read a single voltage channel only. If the internal ADT7473/
ADT7473-1 clock is used, the selected input is read every
711 µs. The appropriate ADC channel is selected by writing to
Bits [7:5] of the TACH1 minimum high byte register (0x55).
Table 8. Programming Single-Channel ADC Mode
Bits [7:5] Register 0x55 Channel Selected
001 VCCP
010 VCC
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Configuration Register 2 (0x73)
Bit 4 = 1; averaging off.
Bit 5 = 1; bypass input attenuators.
Bit 6 = 1; single-channel convert mode.
TACH1 Minimum High Byte Register (0x55)
Bits [7:5] select ADC channel for single-channel convert mode.

ADT7473/ADT7473-1
Rev. C | Page 15 of 72
Table 9. 10-Bit ADC Output Codes vs. VIN
ADC Output
VCC (3.3 VIN)1VCCP Decimal Binary (10 Bits)
<0.0042 <0.00293 0 00000000 00
0.0042 to 0.0085 0.0293 to 0.0058 1 00000000 01
0.0085 to 0.0128 0.0058 to 0.0087 2 00000000 10
0.0128 to 0.0171 0.0087 to 0.0117 3 00000000 11
0.0171 to 0.0214 0.0117 to 0.0146 4 00000001 00
0.0214 to 0.0257 0.0146 to 0.0175 5 00000001 01
0.0257 to 0.0300 0.0175 to 0.0205 6 00000001 10
0.0300 to 0.0343 0.0205 to 0.0234 7 00000001 11
0.0343 to 0.0386 0.0234 to 0.0263 8 00000010 00
…… … …
1.100 to 1.1042 0.7500 to 0.7529 256 (¼ scale) 01000000 00
…… … …
2.200 to 2.2042 1.5000 to 1.5029 512 (½ scale) 10000000 00
… … … …
3.300 to 3.3042 2.2500 to 2.2529 768 (¾ scale) 11000000 00
… … … …
4.3527 to 4.3570 2.9677 to 2.9707 1013 11111101 01
4.3570 to 4.3613 2.9707 to 2.9736 1014 11111101 10
4.3613 to 4.3656 2.9736 to 2.9765 1015 11111101 11
4.3656 to 4.3699 2.9765 to 2.9794 1016 11111110 00
4.3699 to 4.3742 2.9794 to 2.9824 1017 11111110 01
4.3742 to 4.3785 2.9824 to 2.9853 1018 11111110 10
4.3785 to 4.3828 2.9853 to 2.9882 1019 11111110 11
4.3828 to 4.3871 2.9882 to 2.9912 1020 11111111 00
4.3871 to 4.3914 2.9912 to 2.9941 1021 11111111 01
4.3914 to 4.3957 2.9941 to 2.9970 1022 11111111 10
>4.3957 >2.9970 1023 11111111 11
1The VCC output codes listed assume that VCC is 3.3 V.
TEMPERATURE MEASUREMENT METHOD
A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the base-
emitter voltage (VBE) of a transistor operated at constant
current. Unfortunately, this technique requires calibration to
null out the effect of the absolute value of VBE, which varies
from device to device.
The technique used in the ADT7473/ADT7473-1 measures
the change in VBE when the device is operated at three different
currents. Previous devices have used only two operating currents,
but the use of a third current allows automatic cancellation of
resistances in series with the external temperature sensor.
Figure 26 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the collec-
tor is not grounded and should be linked to the base. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D− input.
C1 can optionally be added as a noise filter (recommended
maximum value 1000 pF). However, a better option in noisy
environments is to add a filter, as described in the Noise
Filtering section.
Local Temperature Measurement
The ADT7473/ADT7473-1 contains an on-chip band gap
temperature sensor whose output is digitized by the on-chip
10-bit ADC. The 8-bit MSB temperature data is stored in the
local temperature register (0x26). Because both positive and
negative temperatures can be measured, the temperature data is
stored in Offset 64 format or twos complement format, as
shown in Tabl e 10 and Table 11 . Theoretically, the temperature
sensor and ADC can measure temperatures from −63°C to
+127°C (or −63°C to +191°C in the extended temperature
range) with a resolution of +0.25°C. However, this exceeds the
operating temperature range of the device, so local temperature
measurements outside the ADT7473/ADT7473-1 operating
temperature range are not possible.

ADT7473/ADT7473-1
Rev. C | Page 16 of 72
Table 10. Twos Complement, Temperature Data Format
Temperature Digital Output (10-Bit)1
–128°C 1000 0000 00 (diode fault)
–63°C 1100 0001 00
–50°C 1100 1110 00
–25°C 1110 0111 00
–10°C 1111 0110 00
0°C 0000 0000 00
10.25°C 0000 1010 01
25.5°C 0001 1001 10
50.75°C 0011 0010 11
75°C 0100 1011 00
100°C 0110 0100 00
125°C 0111 1101 00
127°C 0111 1111 00
1 Bold numbers denote 2 LSBs of measurement in the Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Table 11. Extended Range, Temperature Data Format
Temperature Digital Output (10-Bit)1
–64°C 0000 0000 00 (diode fault)
–63°C 0000 0001 00
–1°C 0011 1111 00
0°C 0100 0000 00
1°C 0100 0001 00
10°C 0100 1010 00
25°C 0101 1001 00
50°C 0111 0010 00
75°C 1000 1001 00
100°C 1010 0100 00
125°C 1011 1101 00
191°C 1111 1111 00
1Bold numbers denote 2 LSBs of measurement in the Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Remote Temperature Measurement
The ADT7473/ADT7473-1 can measure the temperature of two
remote diode sensors or diode-connected transistors connected
to Pin 10 and Pin 11 or to Pin 12 and Pin 13.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device and individual calibra-
tion is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7473/
ADT7473-1 is to measure the change in VBE when the device
is operated at three different currents. This is given by
VBE = kT/q× ln(N)
where:
k is Boltzmann’s constant.
Tis the absolute temperature in Kelvin.
qis the charge on the carrier.
Nis the ratio of the two currents.
Figure 26 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for temp-
erature monitoring on some microprocessors. It could also be a
discrete transistor such as a 2N3904/2N3906.
04686-023
D+
V
DD
TO ADC
V
OUT+
V
OUT–
REMOTE
SENSING
TRANSISTOR
D–
IN1 × IN2 × I I
BIAS
LPF
fC = 65kHz
Figure 26. Signal Conditioning for Remote Diode Temperature Sensors

ADT7473/ADT7473-1
Rev. C | Page 17 of 72
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter is connected
to the D+ input. If an NPN transistor is used, the emitter is
connected to the D– input and the base is connected to the D+
input. Figure 27 and Figure 28 show how to connect the
ADT7473/ADT7473-1 to an NPN or PNP transistor for
temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal
of the sensor is not referenced to ground, but is biased above
ground by an internal diode at the D– input.
2
N3904
NPN D+
D–
04686-025
ADT7473/
ADT7473-1
Figure 27. Measuring Temperature Using an NPN Transistor
2
N3906
PNP
ADT7473/
ADT7473-1
D+
D–
04686-026
Figure 28. Measuring Temperature Using a PNP Transistor
To me asure VBE, the operating current through the sensor is
switched among three related currents. N1 × I and N2 × I are
different multiples of the current I, as shown in Figure 26. The
currents through the temperature diode are switched between
I and N1 × I, giving ∆VBE1, and then between I and N2 × I,
giving ∆VBE2. The temperature can then be calculated using the
two ∆VBE measurements. This method can also cancel the effect
of any series resistance on the temperature measurement.
The resulting ∆VBE waveforms are passed through a 65 kHz
low-pass filter to remove noise and then to a chopper-stabilized
amplifier. This amplifies and rectifies the waveform to produce
a dc voltage proportional to ∆VBE. The ADC digitizes this
voltage, and a temperature measurement is produced. To reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles.
The results of remote temperature measurements are stored in
10-bit, twos complement format, as listed in Table 10. The extra
resolution for the temperature measurements is held in the
Extended Resolution Register 2 (0x77). This gives temperature
readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
the D− pin to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
This capacitor reduces the noise, but does not eliminate it,
making use of the sensor difficult in a very noisy environment.
The ADT7473/ADT7473-1 has a major advantage over other
devices for eliminating the effects of noise on the external
sensor. Using the series resistance cancellation feature, a filter
can be constructed between the external temperature sensor
and the part. The effect of any filter resistance seen in series with
the remote sensor is automatically canceled from the tempera-
ture result.
The construction of a filter allows the ADT7473/ADT7473-1
and the remote temperature sensor to operate in noisy
environments. Figure 29 shows a low-pass R-C filter with the
following values:
R= 100 Ω, C= 1 nF
This filtering reduces both common-mode noise and
differential noise.
0
4686-024
D+
1nF
100
Ω
REMOTE
TEMPERATURE
SENSOR
D–
100Ω
Figure 29. Filter Between Remote Sensor and ADT7473/ADT7473-1
SERIES RESISTANCE CANCELLATION
Parasitic resistance to the ADT7473/ADT7473-1 D+ and D−
inputs (seen in series with the remote diode) is caused by a
variety of factors including PCB track resistance and track
length. This series resistance appears as a temperature offset
in the remote sensor’s temperature measurement. This error
typically causes a 0.5°C offset per Ω of parasitic resistance in
series with the remote diode.
The ADT7473/ADT7473-1 automatically cancels out the effect
of this series resistance on the temperature reading, giving a
more accurate result without the need for user characterization
of this resistance. The ADT7473/ADT7473-1 is designed to
automatically cancel up to 3 kΩ of resistance, typically. This is
transparent to the user by using an advanced temperature
measurement method. This feature allows resistances to be
added to the sensor path to produce a filter, allowing the part to
be used in noisy environments. See the Noise Filtering section
for details.
FACTORS AFFECTING DIODE ACCURACY
Remote Sensing Diode
The ADT7473/ADT7473-1 is designed to work with either
substrate transistors built into processors or discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP or
NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+ and the emitter is connected to D−. If a
PNP transistor is used, the collector and base are connected to
D− and the emitter is connected to D+.

ADT7473/ADT7473-1
Rev. C | Page 18 of 72
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7473/ADT7473-1 is trimmed for an nfvalue of 1.008.
Use the following equation to calculate the error intro-
duced at a temperature, T(°C), when using a transistor
whose nfdoes not equal 1.008. Refer to the data sheet for
the related CPU to obtain the nfvalues.
T= (nf− 1.008)/1.008 × (273.15 K + T)
To factor this in, the user can write the ∆T value to the
offset register. Then, the ADT7473/ADT7473-1 auto-
matically adds it to or subtracts it from the temperature
measurement.
•Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7473/ADT7473-1, IHIGH, is 96 µA and the low level
current, ILOW, is 6 µA. If the ADT7473/ADT7473-1 current
levels do not match the current levels specified by the CPU
manufacturer, it might be necessary to remove an offset.
The CPU’s data sheet advises whether this offset needs to
be removed and how to calculate it. This offset can be
programmed to the offset register. It is important to note
that, if more than one offset must be considered, the
algebraic sum of these offsets must be programmed to the
offset register.
If a discrete transistor is used with the ADT7473/ADT7473-1,
the best accuracy is obtained by choosing devices according to
the following criteria:
•Base-emitter voltage greater than 0.25 V at 6 µA, at the
highest operating temperature
•Base-emitter voltage less than 0.95 V at 100 µA, at the
lowest operating temperature
•Base resistance less than 100 Ω
•Small variation in hFE (such as 50 to 150) that indicates
tight control of VBE characteristics
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Nulling Out Temperature Errors
As CPUs run faster, it becomes more difficult to avoid high
frequency clocks when routing the D+/D– traces around a
system board. Even when recommended layout guidelines are
followed, some temperature errors can still be attributable to
noise coupled onto the D+/D– lines. Constant high frequency
noise usually attenuates or increases temperature measurements
by a linear, constant value.
The ADT7473/ADT7473-1 has temperature offset registers at
Register 0x70 and Register 0x72 for the Remote 1 and Remote 2
temperature channels. By performing a one-time calibration of
the system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement, 8-bit reading to
every temperature measurement. The LSBs add +0.5°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to ±64°C with a resolution of +0.5°C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)
Register 0x71, Local Temperature Offset = 0x00 (0°C default)
Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)
ADT7460/ADT7473/ADT7473-1 Backwards-Compatible
Mode
By setting Bit 1 of Configuration Register 5 (0x7C), all tempera-
ture measurements are stored in the zone temperature value
registers (Register 0x25, Register 0x26, and Register 0x27) in
twos complement, in the range −63°C to +127°C. (The
ADT7473/ADT7473-1 still makes calculations based on the
Offset 64 extended range and clamps the results, if necessary.)
The temperature limits must be reprogrammed in twos
complement. If a twos complement temperature below −63°C is
entered, the temperature is clamped to −63°C. In this mode, the
diode fault condition remains −128°C = 1000 0000, while in the
extended temperature range (−64°C to +191°C), the fault condi-
tion is represented by −64°C = 0000 0000.
Temperature Measurement Registers
Register 0x25, Remote 1 Temperature
Register 0x26, Local Temperature
Register 0x27, Remote 2 Temperature
Register 0x77, Extended Resolution 2 = 0x00 default
Bits [7:6] TDM2, Remote 2 Temperature LSBs
Bits [5:4] LTMP, Local Temperature LSBs
Bits [3:2] TDM1, Remote 1 Temperature LSBs
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Register 0x4E, Remote 1 Temperature Low Limit = 0x01 default
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Register 0x50, Local Temperature Low Limit = 0x01 default
Register 0x51, Local Temperature High Limit = 0x7F default
Register 0x52, Remote 2 Temperature Low Limit = 0x01 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F default

ADT7473/ADT7473-1
Rev. C | Page 19 of 72
Reading Temperature from the ADT7473/ADT7473-1
It is important to note that the temperature can be read from
the ADT7473/ADT7473-1 as an 8-bit value (with 1°C
resolution) or as a 10-bit value (with 0.25°C resolution). If only
1°C resolution is required, the temperature readings can be read
back at any time and in no particular order.
If the 10-bit measurement is required, a 2-register read for each
measurement is used. The extended resolution register (Register
0x77) should be read first. This causes all temperature reading
registers to be frozen until all temperature reading registers
have been read from. This prevents an MSB reading from being
updated while its two LSBs are being read, and vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7473/
ADT7473-1 to offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (0x73) turns averaging off.
Table 12. Conversion Time with Averaging Disabled
Channel Measurement Time
Voltage Channel 0.7 ms
Remote 1 Temperature 7 ms
Remote 2 Temperature 7 ms
Local Temperature 1.3 ms
Table 13. Conversion Time with Averaging Enabled
Channel Measurement Time
Voltage Channels 11 ms
Remote Temperature 39 ms
Local Temperature 12 ms
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7473/ADT7473-1 into single-channel ADC conversion
mode. In this mode, the ADT7473/ADT7473-1 can be made to
read a single temperature channel only. The appropriate ADC
channel is selected by writing to Bits [7:5] of the TACH1
minimum high byte register (0x55).
Table 14. Programming Single-Channel ADC Mode for
Temperatures
Bits [7:5] Register 0x55 Channel Selected
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Configuration Register 2 (0x73)
Bit 4 = 1, averaging off.
Bit 6 = 1, single-channel convert mode.
TACH1 Minimum High Byte Register (0x55)
Bits [7:5] select the ADC channel for single-channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
limits. When a temperature exceeds its THERM limit, all PWM
outputs run at 100% duty cycle or the maximum PWM duty
cycle (Register 0x38, Register 0x39, and Register 0x3A) if Bit 3
of Configuration Register 4 (0x7D) is set. The fans remain
running at this speed until the temperature drops below
THERM minus hysteresis; this can be disabled by setting the
boost bit in Configuration Register 3 (0x78), Bit 2. The
hysteresis value for that THERM limit is the value programmed
into the hysteresis registers (Register 0x6D and Register 0x6E).
The default hysteresis value is 4°C.
FANS
TEMPERATURE
100%
HYSTERESIS (°C)
THERM LIMIT
04686-027
Figure 30. THERM Limit Operation

ADT7473/ADT7473-1
Rev. C | Page 20 of 72
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Associated with each measurement channel on the ADT7473/
ADT7473-1 are high and low limits. These can form the basis of
system status monitoring; a status bit can be set for any out-of-
limit condition and is detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7473/ADT7473-1.
Voltage L imit Re g isters
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
Register 0x49, VCC High Limit = 0xFF default
Temperature Limit Registers
Register 0x4E, Remote 1 Temperature Low Limit = 0x01 default
Register 0x4F, Remote 1 Temperature High Limit = 0xFF default
Register 0x6A, Remote 1 THERM Limit = 0xA4 default
Register 0x50, Local Temperature Low Limit = 0x01 default
Register 0x51, Local Temperature High Limit = 0xFF default
Register 0x6B, Local THERM Temperature Limit = 0xA4 default
Register 0x52, Remote 2 Temperature Low Limit = 0x01 default
Register 0x53, Remote 2 Temperature High Limit = 0xFF default
Register 0x6C, Remote 2 THERM Temperature Limit = 0xA4
default
THERM Limit Register
Register 0x7A, THERM Timer Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
Register 0x57, TACH2 Minimum High Byte = 0xFF default
Register 0x58, TACH3 Minimum Low Byte = 0xFF default
Register 0x59, TACH3 Minimum High Byte = 0xFF default
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7473/
ADT7473-1 can be enabled for monitoring. The ADT7473/
ADT7473-1 measures all voltage and temperature measure-
ments in round-robin format and sets the appropriate status bit
for out-of-limit conditions. TACH measurements are not part
of this round-robin cycle. Comparisons are done differently
depending on whether the measured value is being compared
to a high or low limit.
High limit > comparison performed
Low limit ≤ comparison performed
Voltage and temperature channels use a window comparator for
error detecting and, therefore, have high and low limits. Fan
speed measurements use only a low limit. This fan limit is
needed only in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (0x40). By default,
the ADT7473/ADT7473-1 powers up with this bit set. The
ADC measures each analog input in turn and, as each measure-
ment is completed, the result is automatically stored in the
appropriate value register. This round-robin monitoring cycle
continues unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of
interest, because the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated. The total number of channels
measured is
•One dedicated supply voltage input (VCCP)
•Supply voltage (VCC pin)
•Local temperature
•Two remote temperatures
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged voltage
and temperature monitoring is 146 ms. The total monitoring cycle
time for voltage and temperature monitoring with averaging
disabled is 19 ms. The ADT7473/ADT7473-1 is a derivative of the
ADT7467. As a result, the total conversion time in the ADT7473/
ADT7473-1 is the same as the total conversion time of the
ADT7467, even though the ADT7473/ADT7473-1 has fewer
monitored channels.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.