Analog Devices dBCool ADT7475 User manual

dBCool®Remote Thermal
Monitor and Fan Controller
ADT7475
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Extended temperature measurement range, up to 191°C
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium® 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully ROHS compliant
GENERAL DESCRIPTION
The ADT7475 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive or power-
sensitive applications requiring active system cooling. The
ADT7475 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s
thermal solution can be monitored using the THERM input.
The ADT7475 also provides critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
05381-001
BAND GAP
REFERENCE
10-BIT
ADC
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
GND
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANCE
MONITORING
THERM
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
VCCTO ADT7475
VCC
D1+
D1–
D2+
D2–
VCCP BAND GAP
TEMP. SENSOR
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
SERIAL BUS
INTERFACE
SCL SDA SMBALERT
ADT7475
Figure 1.

ADT7475
Rev. 0 | Page 2 of 64
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Product Description......................................................................... 9
Quick Comparison Between ADT7473 and ADT7475 .......... 9
Recommended Implementation................................................. 9
Serial Bus Interface..................................................................... 10
Write Operations ........................................................................ 11
Read Operations ......................................................................... 12
SMBus Timeout .......................................................................... 12
Virus Protection.......................................................................... 12
Voltage Measurement Input...................................................... 12
Analog-to-Digital Converter .................................................... 12
Input Circuitry ............................................................................ 13
Voltage Measurement Registers................................................ 13
VCCP Limit Registers ................................................................... 13
Extended Resolution Registers ................................................. 13
Additional ADC Functions for Voltage Measurements ........ 13
Temperature Measurement Method ........................................ 15
Factors Affecting Diode Accuracy ........................................... 17
Additional ADC Functions for Temperature
Measurement............................................................................... 18
Limits, Status Registers, and Interrupts....................................... 20
Limit Values ................................................................................ 20
Status Registers ........................................................................... 21
THERM Timer ........................................................................... 23
Fan Drive Using PWM Control ............................................... 26
Operating from 3.3 V Standby ................................................. 31
Standby Mode ............................................................................. 31
XNOR Tree Test Mode .............................................................. 31
Power-On Default ...................................................................... 31
Programming the Automatic Fan Speed Control Loop ............ 32
Automatic Fan Control Overview............................................ 32
Step 1: Hardware Configuration .............................................. 33
Recommended Implementation 1 ........................................... 34
Recommended Implementation 2 ........................................... 35
Step 2: Configuring the Mux .................................................... 36
Step 3: TMIN Settings for Thermal Calibration Channels ...... 38
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 39
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 39
Step 6: TRANGE for Temperature Channels................................ 40
Step 7: TTHERM for Temperature Channels ............................... 43
Step 8: THYST for Temperature Channels.................................. 44
Register Tables ................................................................................ 47
Outline Dimensions ....................................................................... 64
Ordering Guide .......................................................................... 64
REVISION HISTORY
7/05—Revision 0: Initial Version

ADT7475
Rev. 0 | Page 3 of 64
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA= 25°C and represent most likely parametric
norm. Logic inputs accept input high voltages up to VMAX even when device is operating down to VMIN. Timing specifications are tested at
logic levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and
are not production tested.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 3.6 V
Supply Current, ICC 1.5 3 mA Interface inactive, ADC active
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±0.5 1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±0.5 1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C −40°C ≤ TA≤ +125°C
Resolution 0.25 °C
Remote Sensor Source Current 180 μA High Level
11 μΑ Low Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENTUATORS)
Total Unadjusted Error (TUE) ±1.5 %
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
19 ms Averaging disabled
Input Resistance 90 120 kΩ For VCCP channel
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±6 % 0°C ≤ TA≤ 70°C
±10 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5,000 RPM Fan count = 0x0438
10,000 RPM Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS (PWM1 TO
PWM3, XTO)
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA
High Level Output Current, IOH 0.1 20 μA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV

ADT7475
Rev. 0 | Page 4 of 64
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
3.6 V Maximum input voltage
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCC V
Input Low Voltage, VIL 0.4 V
DIGITAL INPUT CURRENT
Input High Current, IIH ±1 μA VIN = VCC
Input Low Current, IIL ±1 μA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING See Figure 2
Clock Frequency, fSCLK 10 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 4.7 μs
SCL Low Time, tLOW 4.7 μs
SCL High Time, tHIGH 4.0 50 μs
SCL, SDA Rise Time, tr1,000 ns
SCL, SDA Fall Time, tf 300 μs
Data Setup Time, tSU;DAT 250 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
SCL
SD
A
PS SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
05381-002
Figure 2. Serial Bus Timing Diagram

ADT7475
Rev. 0 | Page 5 of 64
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 3.6 V
Voltage on Any Input or Output Pin −0.3 V to +3.6 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 260°C
Lead Temperature (Soldering 10 sec) 300°C
ESD rating 1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-lead QSOP package:
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADT7475
Rev. 0 | Page 6 of 64
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05381-003
12
11
10
9
D1–
D2+
D2–
TACH4/THERM/GPIO/
SMBALERT
16
15
14
13
SDA
PWM1/XTO
V
CCP
D1+
5
6
7
8
PWM2/SMBALERT
TACH1
TACH2
PWM3
1
2
3
4
SCL
GND
V
CC
TACH3
ADT7475
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND Ground Pin for the ADT7475.
3 VCC Power Supply. VCC is also monitored through this pin.
4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
5 PWM2/
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2
speed. Can be configured as a high or low frequency drive.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
8 PWM3
Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
THERM Digital I/O (Open Drain). Alternatively, the pin can be reconfigured as a bidirectional THERM pin, which can be
used to time and monitor assertions on the THERM input. For example, the pin can be connected to the
PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. This pin can
be used as an output to signal overtemperature conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
GPIO General-Purpose Open Drain Digital I/O.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 VCCP Analog Input. Monitors processor core voltage (0 V − 3 V).
15 PWM1
Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical
pull-up.
XTO Also functions as the output from the XNOR tree in XNOR test mode.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

ADT7475
Rev. 0 | Page 7 of 64
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60 0 2 4 6 8 10 12
CAPACITANCE (nF)
TEMPERATURE ERROR (°C)
14 16 18 20 22
05381-004
Figure 4. Temperature Error vs. Capacitance between D+ and D−
30
20
10
0
–10
–20
–30
0204060
LEAKAGE RESISTANCE (MΩ)
TEMPERATURE ERROR (°C)
80 100
–40
05381-005
D+ TO V
CC
D+ TO GND
Figure 5. Temperature Error vs. PCB Resistance
30
25
20
15
10
5
0
–5 0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
100mV
60mV
40mV
05381-006
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
40mV
05381-007
–10
60mV
100mV
Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0 3.1 3.2 3.3 3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5 3.6
1.00
0.98
05381-008
Figure 8. Normal IDD vs. Power Supply
100mV
250mV
15
10
5
0
–5
–10
–15 0 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
TEMPERATURE ERROR (
°
C)
05381-009
Figure 9. Internal Temperature Error vs. Power Supply

ADT7475
Rev. 0 | Page 8 of 64
05381-010
6
4
2
0
–2
–4
–6
0 100M 200M 300M
FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
400M 500M 600M
–8
–10
–12
100mV
250mV
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (
° C)
TEMPERATURE ERROR (°C)
–1.0
–1.5 105 125
05381-011
Figure 11. Internal Temperature Error vs. ADT7475 Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (
° C)
TEMPERATURE ERROR (°C)
–1.0
–1.5
105 125
05381-012
–2.0
Figure 12. Remote Temperature Error vs. ADT7475 Temperature

ADT7475
Rev. 0 | Page 9 of 64
PRODUCT DESCRIPTION
The ADT7475 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 16),
and an input line for the serial clock (Pin 1). All control and
programming functions for the ADT7475 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
QUICK COMPARISON BETWEEN ADT7473 AND
ADT7475
•The ADT7473 supports Advanced Dynamic TMIN features
while the ADT7475 does not.
•Acoustic smoothing is improved on the ADT7475.
•THERM can be selected as an output only on the
ADT7475.
•The ADT7475 has two additional configuration registers.
•The ADT7475 has other minor register changes.
RECOMMENDED IMPLEMENTATION
•Configuring the ADT7475 as in Figure 13 allows the
system designer to use the following features:
•Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 3.
•CPU temperature measured using Remote 1 temperature
channel.
•Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as
an overtemperature THERM output. The THERM pin
can alternatively be programmed as an SMBALERT system
interrupt output.
05381-015
TACH2
PWM3
TACH3
D1+
D1–
GND
ADT7475
SCL
SDA
TACH1
PWM1
AMBIENT
TEMPERATURE
SMBALERT
D2+
D2–
THERM PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
Figure 13. ADT7475 Configuration

ADT7475
Rev. 0 | Page 10 of 64
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7475 is carried out
using the SMBus. The ADT7475 is connected to this bus as
a slave device, under the control of a master controller, which
is usually (but not necessarily) the ICH.
The ADT7475 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in sequences
of nine clock pulses: eight bits of data followed by an acknowl-
edge bit from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high transition
when the clock is high might be interpreted as a stop signal. The
number of data bytes that can be transmitted over the serial bus
in a single read or write operation is limited only by what the
master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition.
In read mode, the master device overrides the acknowledge bit
by pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before
the tenth clock pulse, and then high during the tenth clock
pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined
at the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7475, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so that the correct data register is
addressed, and then data can be written into that register or
read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data is
to be written to the device, the write operation contains a
second data byte that is written to the register selected by the
address pointer register.
This write operation is shown in Figure 14. The device address
is sent over the bus, and then R/Wis set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
•If the ADT7475’s address pointer register value is unknown
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7475 as
before, but only the data byte containing the register
address is sent, because no data is written to the register.
This is shown in Figure 15.
A read operation is then performed consisting of the serial
bus address, R/Wbit set to 1, followed by the data byte
read from the data register. This is shown in Figure 16.
•If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 16.
R/W
0
SCL
SDA 101110D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7475
START BY
MASTER
19
1
ACK. BY
ADT7475
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7475 STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
05381-016
Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

ADT7475
Rev. 0 | Page 11 of 64
R/W
0
SCL
S
D
A
101110D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7475 STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE
119
ACK. BY
ADT7475
9
05381-017
Figure 15. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA 101110D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT745
119
ACK. BY
ADT7475
9
05381-018
Figure 16. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
In addition to supporting the send byte and receive byte pro-
tocols, the ADT7475 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2 for more
information; this document is available from Intel.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for differ-
ent types of read and write operations. The ones used in the
ADT7475 are discussed below. The following abbreviations
are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
The ADT7475 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7475, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is illustrated in Figure 17.
05381-019
SLAVE
ADDRESS WASA
REGISTER
ADDRESS
23154
P
6
Figure 17. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA, and the
transaction ends.

ADT7475
Rev. 0 | Page 12 of 64
The byte write operation is shown in Figure 18.
05381-020
SLAVE
ADDRESS W A DATASA
REGISTER
ADDRESS
23154
AP
678
Figure 18. Single Byte Write to a Register
READ OPERATIONS
The ADT7475 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up previously.
In this operation, the master device receives a single byte from
a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7475, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is shown in Figure 19.
05381-021
SLAVE
ADDRESS DATAARSA
24315
P
6
Figure 19. Single Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be con-
nected to a common SMBALERT line connected to the master.
If a device’s SMBALERT line goes low, the following events
occur:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7475 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7475 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7475 assumes that the
bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some
SMBus controllers cannot handle the SMBus timeout feature,
so it can be disabled.
Configuration Register 1 (Reg. 0x40)
<6> TODIS = 0, SMBus timeout enabled (default).
<6> TODIS = 1, SMBus timeout disabled.
VIRUS PROTECTION
To prevent rogue programs or viruses from accessing critical
ADT7475 register settings, the lock bit can be set. Setting Bit 1
of Configuration Register 1 (0x40) sets the lock bit and locks
critical registers. In this mode, certain registers can no longer be
written to until the ADT7475 is powered down and powered up
again. For more information on which registers are locked,
please see the ADT7475 Registers.
VOLTAGE MEASUREMENT INPUT
The ADT7475 has one external voltage measurement channel.
It can also measure its own supply voltage, VCC. Pin 14 can
measure VCCP. The VCC supply voltage measurement is carried
out through the VCC pin (Pin 3). The VCCP input can be used to
monitor a chipset supply voltage in computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full scale
(decimal 768 or 300 hex) for the nominal input voltage and so
has adequate headroom to deal with overvoltages.

ADT7475
Rev. 0 | Page 13 of 64
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown in
Figure 20. The input circuit consists of an input protection
diode, an attenuator, and a capacitor, to form a first-order
low-pass filter that gives the input immunity to high fre-
quency noise.
05381-022
V
CCP
17.5kΩ
52.5kΩ35pF
Figure 20. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x21 VCCP Reading = 0x00 default
Reg. 0x22 VCC Reading = 0x00 default
VCCP LIMIT REGISTERS
Associated with the VCCP measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x46 VCCP Low Limit = 0x00 default
Reg. 0x47 VCCP High Limit = 0xFF default
Table 5 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
EXTENDED RESOLUTION REGISTERS
Voltage measurements can be made with higher accuracy using
the extended resolution registers (0x76 and 0x77). Whenever
the extended resolution registers are read, the corresponding
data in the voltage measurement registers (0x20 to 0x 24) is
locked until their data is read. That is, if extended resolution is
required, then the extended resolution register must be read
first, immediately followed by the appropriate voltage
measurement register.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally, and the
results averaged, before being placed into the value register.
For instances where faster conversions are needed, setting Bit 4
of Configuration Register 2 (Reg. 0x73) turns averaging off.
This effectively gives a reading 16 times faster (711 µs), but the
reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the VCCP input. This allows
the user to directly connect external sensors, or to rescale the
analog voltage measurement inputs for other applications. The
input range of the ADC without the attenuators is 0 V to 2.25 V.
Single Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single voltage chan-
nel only. If the internal ADT7475 clock is used, the selected
input is read every 711 µs. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 minimum high
byte register (0x55).
Table 4. Single Channel ADC Conversion
Bits <7:5> Reg. 0x55 Channel Selected
001 VCCP
010 VCC
101 Remote 1 Temperature
110 Local Temperature
111 Remote 2 Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<5> = 1, bypass input attenuators.
<6> = 1, single channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> selects ADC channel for single channel convert mode.

ADT7475
Rev. 0 | Page 14 of 64
Table 5. 10-Bit A/D Output Code vs. VIN
A/D Output
VCC (3.3 VIN)1VCCP Decimal Binary (10 Bits)
<0.0042 <0.00293 0 00000000 00
0.0042–0.0085 0.0293–0.0058 1 00000000 01
0.0085–0.0128 0.0058–0.0087 2 00000000 10
0.0128–0.0171 0.0087–0.0117 3 00000000 11
0.0171–0.0214 0.0117–0.0146 4 00000001 00
0.0214–0.0257 0.0146–0.0175 5 00000001 01
0.0257–0.0300 0.0175–0.0205 6 00000001 10
0.0300–0.0343 0.0205–0.0234 7 00000001 11
0.0343–0.0386 0.0234–0.0263 8 00000010 00
•
•
•
1.100–1.1042 0.7500–0.7529 256 (1/4-scale) 01000000 00
•
•
•
2.200–2.2042 1.5000–1.5029 512 (1/2-scale) 10000000 00
•
•
•
3.300–3.3042 2.2500–2.2529 768 (3/4 scale) 11000000 00
•
•
•
4.3527–4.3570 2.9677–2.9707 1013 11111101 01
4.3570–4.3613 2.9707–2.9736 1014 11111101 10
4.3613–4.3656 2.9736–2.9765 1015 11111101 11
4.3656–4.3699 2.9765–2.9794 1016 11111110 00
4.3699–4.3742 2.9794–2.9824 1017 11111110 01
4.3742–4.3785 2.9824–2.9853 1018 11111110 10
4.3785–4.3828 2.9853–2.9882 1019 11111110 11
4.3828–4.3871 2.9882–2.9912 1020 11111111 00
4.3871–4.3914 2.9912–2.9941 1021 11111111 01
4.3914–4.3957 2.9941–2.9970 1022 11111111 10
>4.3957 >2.9970 1023 11111111 11
1 The VCC output codes listed assume that VCC is 3.3 V, and VCC should never exceed 3.6 V.

ADT7475
Rev. 0 | Page 15 of 64
TEMPERATURE MEASUREMENT METHOD
Local Temperature Measurement
The ADT7475 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip, 10-bit ADC. The 8-bit
MSB temperature data is stored in the temperature registers
(Address 0x25, 0x26, and 0x27). Because both positive and
negative temperatures can be measured, the temperature data is
stored in Offset 64 format or twos complement format, as shown
in Table 6 and Table 7.
Theoretically, the temperature sensor and ADC can measure
temperatures from −63°C to +127°C (or −61°C to +191°C in
the extended temperature range) with a resolution of 0.25°C.
However, this exceeds the operating temperature range of
the device, so local temperature measurements outside the
ADT7475 operating temperature range are not possible.
Remote Temperature Measurement
The ADT7475 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pin 10 and
Pin 11, or Pin 12 and Pin 13.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device and individual calibration is
required to null this out, so the technique is unsuitable for mass
production.
05381-023
D+
BIAS
DIODE
V
DD
TO ADC
V
OUT+
V
OUT–
REMOTE
SENSING
TRANSISTOR D–
THERMDA
THERMDC
I N × I I
BIAS
LOW-PASS FILTER
f
C
= 65kHz
CPU
Figure 21. Signal Conditioning for Remote Diode Temperature Sensors

ADT7475
Rev. 0 | Page 16 of 64
The technique used in the ADT7475 is to measure the change
in VBE when the device is operated at two different currents.
This is given by
VBE = KT/q× 1n(N)
where:
Kis Boltzmann’s constant.
qis the charge on the carrier.
Tis the absolute temperature in Kelvin.
Nis the ratio of the two currents.
Figure 21 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could also be a discrete
transistor such as a 2N3904/2N3906.
If a discrete transistor is used, the collector is not grounded
and should be linked to the base. If a PNP transistor is used,
the base is connected to the D− input and the emitter to the
D+ input. If an NPN transistor is used, the emitter is connected
to the D− input and the base to the D+ input. Figure 22 and
Figure 23 show how to connect the ADT7475 to an NPN
or PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D− input.
To measure VBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a dc voltage proportional to VBE. This voltage is measured
by the ADC to give a temperature output in 10-bit, twos
complement format. To further reduce the effects of noise,
digital filtering is performed by averaging the results of
16 measurement cycles.
A remote temperature measurement takes nominally 38 ms. The
results of remote temperature measurements are stored in 10-bit,
twos complement format, as shown in Table 6. The extra resolu-
tion for the temperature measurements is held in the Extended
Resolution Register 2 (Reg. 0x77). This gives temperature
readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
D− pin to help combat the effects of noise. However, large capaci-
tances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
This capacitor reduces the noise, but does not eliminate it.
Sometimes, this sensor noise is a problem in a very noisy
environment. In most cases, a capacitor is not required as
differential inputs, by their very nature, have a high immunity
to noise.
2
N3904
NPN
ADT7475
D+
D–
05381-025
Figure 22. Measuring Temperature Using an NPN Transistor
2
N3906
PNP
ADT7475
D+
D–
05381-026
Figure 23. Measuring Temperature Using a PNP Transistor

ADT7475
Rev. 0 | Page 17 of 64
FACTORS AFFECTING DIODE ACCURACY
Remote Sensing Diode
The ADT7475 is designed to work with either substrate
transistors built into processors or with discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP
or NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+ and the emitter to D−. If a PNP transistor
is used, the collector and base are connected to D− and the
emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7475 is trimmed for an nfvalue of 1.008. Use the
following equation to calculate the error introduced at a
temperature T(°C), when using a transistor whose nf
does not equal 1.008. See the processor data sheet for the
nfvalues.
ΔT= (nf− 1.008) × (273.15 K + T)
To factor this in, the user can write the ∆Tvalue to the
offset register. The ADT7475 then automatically adds it
to or subtracts it from the temperature measurement.
•Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7475, IHIGH, is 180 µA and the low level current,
ILOW, is 11 µA. If the ADT7475 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU’s data
sheet advises whether this offset needs to be removed and
how to calculate it. This offset can be programmed to the
offset register. If more than one offset must be considered,
the algebraic sum of these offsets must be programmed to
the offset register.
If a discrete transistor is used with the ADT7475, the best
accuracy is obtained by choosing devices according to the
following criteria:
•Base-emitter voltage greater than 0.25 V at 11 µA, at the
highest operating temperature.
•Base-emitter voltage less than 0.95 V at 180 µA, at the
lowest operating temperature.
•Base resistance less than 100 Ω.
•Small variation in hFE (approximately 50 to 150) that
indicates tight control of VBE characteristics.
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Table 6. Twos Complement Temperature Data Format
Temperature Digital Output (10-Bit)1
–128°C 1000 0000 00 (diode fault)
–50°C 1100 1110 00
–25°C 1110 0111 00
–10°C 1111 0110 00
0°C 0000 0000 00
10.25°C 0000 1010 01
25.5°C 0001 1001 10
50.75°C 0011 0010 11
75°C 0100 1011 00
100°C 0110 0100 00
125°C 0111 1101 00
127°C 0111 1111 00
1Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
Table 7. Extended Range, Temperature Data Format
Temperature Digital Output (10-Bit)1
–64°C 0000 0000 00 (diode fault)
–1°C 0011 1111 00
0°C 0100 0000 00
1°C 0100 0001 00
10°C 0100 1010 00
25°C 0101 1001 00
50°C 0111 0010 00
75°C 1000 1001 00
100°C 1010 0100 00
125°C 1011 1101 00
191°C 1111 1111 00
1Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
Nulling Out Temperature Errors
As CPUs run faster, it is more difficult to avoid high frequency
clocks when routing the D+/D– traces around a system board.
Even when recommended layout guidelines are followed, some
temperature errors may still be attributable to noise coupled
onto the D+/D– lines. Constant high frequency noise usually
attenuates, or increases, temperature measurements by a linear,
constant value.
The ADT7475 has temperature offset registers at
Addresses 0x70, 0x72 for the Remote 1 and Remote 2
temperature channels. By doing a one-time calibration of
the system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement.

ADT7475
Rev. 0 | Page 18 of 64
Changing Bit 1 of Configuration Register 5 (0x7C) changes the
resolution and therefore the range of the temperature offset as
either having a range of –63°C to +127°C, with a resolution of
1°C, or having a range of -63°C to +64°C, with a resolution of
0.5°C. This temperature offset can be used to compensate for
linear temperature errors introduced by noise.
Temperature Offset Registers
Reg. 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)
Reg. 0x71, Local Temperature Offset = 0x00 (0°C default)
Reg. 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)
ADT7463/ADT7475 Backwards Compatible Mode
By setting Bit 0 of Configuration Register 5 (0x7C), all tempera-
ture measurements are stored in the zone temp value registers
(0x25, 0x26, and 0x27) in twos complement in the range −63°C
to +127°C. The temperature limits must be reprogrammed in
twos complement.
If a twos complement temperature below −63°C is entered, the
temperature is clamped to −63°C. In this mode, the diode fault
condition remains −128°C = 1000 0000, while in the extended
temperature range (−63°C to +191°C), the fault condition is
represented by −64°C = 0000 0000.
Temperature Measurement Registers
Reg. 0x25, Remote 1 Temperature
Reg. 0x26, Local Temperature
Reg. 0x27, Remote 2 Temperature
Reg. 0x77, Extended Resolution 2 = 0x00 default
<7:6> TDM2, Remote 2 Temperature LSBs.
<5:4> LTMP, Local Temperature LSBs.
<3:2> TDM1, Remote 1 Temperature LSBs.
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts (depending on the
way the interrupt mask register is programmed and assuming
that SMBALERT is set as an output on the appropriate pin).
Reg. 0x4E, Remote 1 Temperature Low Limit = 0x81 default
Reg. 0x4F, Remote 1 Temperature High Limit = 0x7F default
Reg. 0x50, Local Temperature Low Limit = 0x81 default
Reg. 0x51, Local Temperature High Limit = 0x7F default
Reg. 0x52, Remote 2 Temperature Low Limit = 0x81 default
Reg. 0x53, Remote 2 Temperature High Limit = 0x7F default
Reading Temperature from the ADT7475
It is important to note that temperature can be read from the
ADT7475 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read and
vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally, and the results
averaged, before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off. The
default round-robin cycle time takes 146.5 ms.
Table 8. Conversion Time with Averaging Disabled
Channel Measurement Time (ms)
Voltage Channels 0.7
Remote Temperature 1 7
Remote Temperature 2 7
Local Temperature 1.3
When bit 7 of configuration register 6 (0x10) is set, the default
round-robin cycle time increases to 240 ms.
Table 9. Conversion Time with Averaging Enabled
Channel Measurement Time (ms)
Voltage Channels 11
Remote Temperature 39
Local Temperature 12

ADT7475
Rev. 0 | Page 19 of 64
Single Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single temperature
channel only. The appropriate ADC channel is selected by
writing to Bits <7:5> of the TACH1 minimum high byte
register (0x55).
Table 10. Programming Single Channel ADC Mode
for Temperatures
Bits <7:5> Reg. 0x55 Channel Selected
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<6> = 1, single channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> selects ADC channel for single channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
temperature limits. When a temperature exceeds its THERM
temperature limit, all PWM outputs run at the maximum
PWM duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A).
This effectively runs the fans at the fastest allowed speed.
The fans run at this speed until the temperature drops below
THERM minus hysteresis. This can be disabled by setting the
boost bit in Configuration Register 3, Bit 2, Reg. 0x78. The
hysteresis value for the THERM temperature limit is the value
programmed into Reg. 0x6D and Reg. 0x6E (hysteresis
registers). The default hysteresis value is 4°C.
FANS
TEMPERATURE
100%
HYSTERESIS (°C)
THERM LIMIT
05381-027
Figure 24. THERM Temperature Limit Operation
THERM can be disabled on specific temperature channels using
bits <7:5> of configuration register 5 (0x7C). THERM can also
be disabled by:
•In offset 64 mode, writing −64°C to the appropriate THERM
temperature limit.
•In twos complement mode, writing −128°C to the
appropriate THERM temperature limit.

ADT7475
Rev. 0 | Page 20 of 64
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Associated with each measurement channel on the ADT7475
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor
or microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7475.
Voltage Limit Registers
Reg. 0x46 VCCP Low Limit = 0x00 default
Reg. 0x47 VCCP High Limit = 0xFF default
Reg. 0x48 VCC Low Limit = 0x00 default
Reg. 0x49 VCC High Limit = 0xFF default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default
Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default
Reg. 0x6A Remote 1 THERM Limit = 0x64 default
Reg. 0x50 Local Temperature Low Limit = 0x01 default
Reg. 0x51 Local Temperature High Limit = 0x7F default
Reg. 0x6B Local THERM Limit = 0x64 default
Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default
Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default
Reg. 0x6C Remote 2 THERM Limit = 0x64 default
THERM Limit Register
Reg. 0x7A THERM Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Reg. 0x54 TACH1 Minimum L ow Byte = 0x00 default
Reg. 0x55 TACH1 Minimum High Byte = 0x00 default
Reg. 0x56 TACH2 Minimum L ow Byte = 0x00 default
Reg. 0x57 TACH2 Minimum High Byte = 0x00 default
Reg. 0x58 TACH3 Minimum L ow Byte = 0x00 default
Reg. 0x59 TACH3 Minimum High Byte = 0x00 default
Reg. 0x5A TACH4 Minimum L ow Byte = 0x00 default
Reg. 0x5B TACH4 Minimum High Byte = 0x00 default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7475 can
be enabled for monitoring. The ADT7475 measures all voltage
and temperature measurements in round-robin format and
sets the appropriate status bit for out-of-limit conditions.
TACH measurements are not part of this round-robin cycle.
Comparisons are done differently, depending on whether
the measured value is being compared to a high or low limit.
High Limit: > Comparison Performed
Low Limit: ≤ Comparison Performed
Voltage and temperature channels use a window comparator
for error detecting and, therefore, have high and low limits.
Fan speed measurements use only a low limit. This fan limit
is needed only in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40).
By default, the ADT7463 powers up with this bit set. The ADC
measures each analog input in turn and, as each measurement
is completed, the result is automatically stored in the appropri-
ate value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of inter-
est, because the most recently measured value of any input can
be read out at any time.
For applications where the monitoring cycle time is impor-
tant, it can easily be calculated. The total number of channels
measured is
•One dedicated supply voltage input (VCCP)
•Supply voltage (VCC pin)
•Local temperature
•Two remote temperatures