Analog Devices LINEAR LT8491 User manual

LT8491
1
Rev. 0
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
High Voltage Buck-Boost Battery Charge
Controller with Maximum Power Point
Tracking (MPPT) and I2C
The LT
®
8491 is a buck-boost switching regulator battery
charger that implements a constant-current constant-
voltage (CCCV) charging profile used for most battery
types, including sealed lead-acid (SLA), flooded, gel and
lithium-ion.
The device operates from input voltages above, below or
equal to the output voltage and can be powered by a solar
panel or a DC power supply. On-chip logic provides auto-
matic maximum power point tracking (MPPT) for solar
powered applications. The LT8491 can perform automatic
temperature compensation by sensing an external therm-
istor thermally coupled to the battery. The STATUS pin
can be used to drive an LED indicator lamp. The device is
available in a low profile (0.75mm) 7mm × 11mm 64-lead
QFN package.
Simplified Solar Powered Battery Charger Schematic
Maximum Power
Point Tracking
APPLICATIONS
n VIN Range: 6V to 80V
n VBAT Range: 1.3V to 80V
n Single Inductor Allows VIN Above, Below, or Equal
to VBAT
n Automatic MPPT for Solar Powered Charging
n Automatic Temperature Compensation
n I2C Telemetry and Configuration
n Internal EEPROM for Configuration Storage
n Operation from Solar Panel or DC Supply
n Four Integrated Feedback Loops
n Synchronizable Fixed Frequency: 100kHz to 400kHz
n 64-Lead (7mm × 11mm × 0.75mm) QFN Package
n Solar Powered Battery Chargers
n Multiple Types of Lead-Acid Battery Charging
n Li-Ion Battery Charger
n Battery Equipped Industrial or Portable Military
Equipment
All registered trademarks and trademarks are the property of their respective owners.
LT8491
SOLAR PANEL
TG1 BOOST1
CSNIN
CSPIN
VIN
CSPOUT
CSNOUT
EXTVCC
AVDD
TEMPSENSE
GATEVCC
INTVCC
SDA
SCL
SW1 BG1 CSP CSN
STATUS CA
AVDD
BG2 SW2 BOOST2 TG2
GND
RECHARGABLE
BATTERY
LOAD
THERMISTOR
+ –
8491 TA01a
AVDD
GATEVCC´
I2C INTERFACE
TELEMETRY
STATUS CONTROL
CONFIGURATION
GATEVCC´ GATEVCC´
VBAT
8491 TA01b
0.5s/DIV
VPANEL
6V/DIV
IMON_IN
0.2V/DIV
PERTURB
AND
OBSERVE
PERTURB AND
OBSERVE
FULL PANEL SCAN

LT8491
2
Rev. 0
For more information www.analog.com
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics ................................. 5
Typical Performance Characteristics ................... 8
Pin Functions .............................................. 10
Block Diagram............................................. 13
Operation................................................... 14
Overview................................................................. 14
I2C Serial Interface.................................................. 14
I2C: START and STOP Conditions...............................14
I2C: ACKnowledge .......................................................14
I2C: Chip Addressing ...................................................15
I2C: Clock Stretching ...................................................15
I2C: Data Transfer Transactions ..................................15
I2C: Powering the Interface.........................................15
I2C Data .................................................................. 16
Data:Memory Regions ...............................................16
Data:Bytes, Words and Long Words.........................17
Data:Min/Max Register Values ..................................17
Data:Access Permissions...........................................17
Startup Sequence ................................................... 18
Battery Charging Algorithm ....................................20
Stage0:Trickle Charging ........................................... 20
Stage1:Full Constant Current ................................... 20
Stage2:Constant Voltage.......................................... 21
Stage3:(Optional) Reduced Constant Voltage......... 21
Done Charging............................................................ 21
Charging Faults........................................................... 21
Maximum Power Point Tracking.............................23
Telemetry Operation ...............................................23
Telemetry:Configuration Settings ..............................24
Telemetry:Acquisition.................................................24
CRC Operation ........................................................ 24
EEPROM Operation.................................................25
EEPROM:Startup ....................................................... 25
EEPROM:Reading...................................................... 25
EEPROM:Writing ....................................................... 25
I2C Register Map.......................................... 27
I2C Register Descriptions................................ 30
Telemetry Registers................................................30
TELE_TBAT ................................................................. 30
TELE_POUT.................................................................31
TELE_PIN.....................................................................31
TELE_EFF.....................................................................31
TELE_IOUT ................................................................. 32
TELE_IIN..................................................................... 32
TELE_VBAT................................................................. 32
TELE_VIN.................................................................... 33
TELE_VINR ................................................................. 33
Status Registers .....................................................34
STAT_CHARGER......................................................... 34
STAT_SYSTEM ........................................................... 35
STAT_SUPPLY ............................................................ 36
STAT_TSx_REMAIN ................................................... 36
STAT_CHRG_FAULTS ................................................ 37
STAT_VERSION .......................................................... 38
STAT_BOOT_CRC ....................................................... 38
STAT_CFG_CRC.......................................................... 38
Control The EEPROM..............................................39
CTRL_WRT_TO_BOOT .............................................. 39
CTRL_EE_WRT_EN ................................................... 39
Control Other Functions..........................................40
CTRL_HALT_STARTUP ............................................. 40
CTRL_CHRG_EN........................................................ 40
CTRL_RESTART_CHIP ...............................................41
CTRL_RESET_FLAG ...................................................41
CTRL_UPDATE_TELEM..............................................41
Configure The Telemetry.........................................42
CFG_RSENSE1........................................................... 42
CFG_RIMON_OUT ..................................................... 43
CFG_RSENSE2........................................................... 43
CFG_RDACO............................................................... 43
CFG_RFBOUT1........................................................... 44
CFG_RFBOUT2........................................................... 44
CFG_RDACI ................................................................ 44
CFG_RFBIN2............................................................... 45
CFG_RFBIN1............................................................... 45
Configure Initial Charger Enable .............................45
CFG_INIT_CHRG_EN ................................................. 45

LT8491
3
Rev. 0
For more information www.analog.com
Configure VBAT for Stages 0, 1 and 3......................46
CFG_VS3_25C............................................................ 46
CFG_UV_S0.................................................................47
CFG_S0_UV ................................................................47
CFG_S0_S1 ................................................................ 48
CFG_S1_S0 ................................................................ 49
Configure Temperature Fault Limits........................50
CFG_TBAT_MIN.......................................................... 50
CFG_TBAT_MAX ........................................................ 50
Configure Stage Timeout Limits ............................. 51
CFG_TMR_S0..............................................................51
CFG_TMR_S1..............................................................51
CFG_TMR_S2..............................................................51
CFG_TMR_S3..............................................................51
Configure Automatic Restart ..................................52
CFG_RSTRT_IN_FLT.................................................. 52
CFG_RSTRT_IN_DONEA ........................................... 54
CFG_RSTRT_IN_DONEB ........................................... 55
CFG_RSTRT_IN_S3................................................... 55
Configure Charge Termination ................................55
CFG_TERMINATE ....................................................... 55
Configure Misc. ......................................................56
CFG_SCAN_RATE_LP ............................................... 56
CFG_SCAN_RATE...................................................... 56
CFG_CHRG_MISC...................................................... 57
Configure Temperature Compensation....................58
CFG_TC3, CFG_TC2, CFG_TC1.................................. 59
Configure User Code...............................................59
CFG_USER_CODE...................................................... 59
Manufacturer Data..................................................60
MFR_DATA1 ............................................................... 60
MFR_DATA2............................................................... 60
MFR_DATA3............................................................... 60
Applications Information ................................ 61
Hardware Configuration..........................................61
HW Config:Input Voltage Sensing and Modulation.. 61
HW Config:VINR Pin Connections............................ 61
HW Config:Solar Panel Powered Charging .............. 62
HW Config:DC Supply Powered Charging................ 63
HW Config:VBAT in Stage 2 (VS2)............................. 63
HW Config:Input Current Sense and Limit ............... 64
HW Config:Output Current Sense and Limit ............ 65
HW Config:Current Sense Filtering........................... 66
HW Config:Battery Temperature and Disconnect
Sensing....................................................................... 67
HW Config: SHDN Pin Connections .......................... 67
HW Config:MODE Pin –Current Conduction Mode. 67
HW Config:Driving an LED with the STATUS Pin..... 68
HW Config:I2C Chip Address Pin.............................. 69
In-Situ Battery Charging .........................................69
Hot-Plugging Considerations .................................. 70
STATUS Indicator Pin..............................................70
Lithium-Ion Battery Charging .................................70
Lead-Acid Battery Charging....................................71
Optional Features....................................................72
Optional:Low Power Mode........................................ 72
Optional:Output Feedback Resistor Disconnect....... 72
Optional:EXTVCC Disconnect.................................... 73
Optional:Remote Battery Voltage Sensing ................74
Optional:DC Supply Detection Circuit ....................... 76
Board Layout Considerations..................................76
Design Example......................................................76
Typical Applications ...................................... 79
Package Description ..................................... 81
Typical Application ....................................... 82
Related Parts .............................................. 82

LT8491
4
Rev. 0
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VCSP – VCSN, VCSPIN – VCSNIN,
VCSPOUT – VCSNOUT................................... –0.3V to 0.3V
SS, CLKOUT, CSP, CSN Voltage ................... –0.3V to 3V
VCVoltage (Note 2)................................... –0.3V to 2.2V
LDO33, VDD, AVDD, Voltage.......................... –0.3V to 5V
RT, FBOUT Voltage....................................... –0.3V to 5V
IMON_IN, IMON_OUT Voltage ..................... –0.3V to 5V
SYNC Voltage............................................ –0.3V to 5.5V
INTVCC, GATEVCC Voltage............................ –0.3V to 7V
VBOOST1 – VSW1, VBOOST2 – VSW2................ –0.3V to 7V
SWEN, MODE Voltage.................................. –0.3V to 7V
SRVO_FBIN, SRVO_FBOUT Voltage........... –0.3V to 30V
SRVO_IIN, SRVO_IOUT Voltage................. –0.3V to 30V
FBIN, SHDN Voltage................................... –0.3V to 30V
CSNIN, CSPIN, CSPOUT,
CSNOUT Voltage........................................ –0.3V to 80V
VIN, EXTVCC Voltage .................................. –0.3V to 80V
SW1, SW2 Voltage......................................81V (Note 5)
BOOST1, BOOST2 Voltage ......................... –0.3V to 87V
BG1, BG2, TG1, TG2........................................... (Note 4)
IOW, ECON, CLKDET Voltage.......... –0.3V to VDD + 0.5V
SWENO, STATUS Voltage................ –0.3V to VDD + 0.5V
FBOW, FBIW, Voltage...................... –0.3V to VDD + 0.5V
VINR, FBOR, IIR, IOR Voltage ......... –0.3V to VDD + 0.5V
TEMPSENSE Voltage....................... –0.3V to VDD + 0.5V
SDA, SCL, CA Voltage..................... –0.3V to VDD + 0.5V
Operating Junction Temperature Range
LT8491E (Notes 1, 3) ......................... –40°C to 125°C
LT8491I (Notes 1, 3) .......................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
TOP VIEW
UKJ PACKAGE
64-LEAD (7mm × 11mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
65
GND
FBIR 1
CA 2
TEMPSENSE 3
VDD 4
FBOW 5
FBIW 6
INTVCC 7
SWEN 8
MODE 9
IMON_IN 10
SHDN 11
CSN 12
CSP 13
LDO33 14
FBIN 15
FBOUT 16
IMON_OUT 17
VC18
SS 19
CLKOUT 20
52 NC
51 STATUS
50 IOW
49 SWENO
48 ECON
46 VIN
45 CSPIN
44 CSNIN
42 CSPOUT
41 CSNOUT
40 EXTVCC
38
SRVO_FBOUT
37 SRVO_IOUT
36 SRVO_IIN
35 SRVO_FBIN
33 BOOST1
64 IOR 63 SCL 62 GND 61 SDA 60 NC 59 GND 58 AVDD 57 FBOR 56 CLKDET 55 GND 54 VINR 53 IIR
SYNC 21
RT 22
BG1 23
GATEVCC 24
BG2 25
BOOST2 27
TG2 28
SW2 29 SW1 31
TG1 32
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8491EUKJ#PBF LT8491EUKJ#TRPBF LT8491UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C
LT8491IUKJ#PBF LT8491IUKJ#TRPBF LT8491UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

LT8491
5
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Supply and Regulators
VIN Operating Voltage Range (Note 7) l6 80 V
VIN Quiescent Current Not Switching, VEXTVCC = 0, VDD = AVDD = Float 2.65 4.2 mA
VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA
VDD Quiescent Current IAVDD + IVDD, VDD = AVDD = 3.3V l2.5 4 6.5 mA
EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l6.15 6.4 6.6 V
EXTVCC Switchover Hysteresis 0.18 V
LDO33 Pin Voltage 5mA from LDO33 Pin l3.23 3.295 3.35 V
LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 %
LDO33 Pin Current Limit l12 17.25 22 mA
LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V
LDO33 Pin Undervoltage Lockout Hysteresis 35 mV
Switching Regulator Control
SHDN Input Voltage High SHDN Rising to Enable the Device l1.184 1.234 1.284 V
SHDN Input Voltage High Hysteresis 50 mV
SHDN Input Voltage Low Device Disabled, Low Quiescent Current l0.35 V
SHDN Pin Bias Current VSHDN = 3V
VSHDN = 12V
0
11
1
22
µA
µA
SWEN Rising Threshold Voltage l1.156 1.206 1.256 V
SWEN Threshold Voltage Hysteresis 22 mV
MODE Pin Thresholds Discontinuous Mode
Automatic DCM/CCM Mode
l
l
0.4
2.3 V
V
IMON_OUT Rising threshold for CCM Operation MODE = 0V 168 195 224 mV
IMON_OUT Falling threshold for DCM MODE = 0V 95 122 150 mV
Voltage Regulation
Regulation Voltage for FBOUT VC= 1.2V, EXTVCC = 0 l1.193 1.207 1.222 V
Regulation Voltage for FBIN VC= 1.2V, EXTVCC = 0 l1.184 1.205 1.226 V
FBOUT Pin Bias Current Current Out of Pin 15 nA
FBIN Pin Bias Current Current Out of Pin 10 nA
Current Regulation
Regulation Voltage for IMON_IN and IMON_OUT VC = 1.2V, EXTVCC = 0 l1.187 1.208 1.229 V
IMON_IN Output Current VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V
VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V
VCSPIN – VCSNIN = 0mV, VCSPIN = 5V
l
l
54
53
2.5
57
57
7
60
61
11.5
µA
µA
µA
IMON_IN Overvoltage Threshold l1.55 1.61 1.67 V
IMON_OUT Output Current VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V
VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V
l
l
47.5
47
3.25
2.75
50
50
5
5
52.5
54.25
6.75
8
µA
µA
µA
µA
IMON_OUT Overvoltage Threshold l1.55 1.61 1.67 V
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

LT8491
6
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Oscillator (OSC1)
Switch Frequency Range Syncing or Free Running 100 400 kHz
Switching Frequency, fOSC RT= 365kΩ
RT= 215kΩ
RT= 124kΩ
l
l
l
102
170
310
120
202
350
142
235
400
kHz
kHz
kHz
SYNC High Level for Synchronization l1.3 V
SYNC Low Level for Synchronization l0.5 V
SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 %
Recommended Min SYNC Ratio, fSYNC/fOSC ¾ f/f
CLKOUT Output Voltage HIGH 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V
CLKOUT Output Voltage LOW 1mA into CKLKOUT Pin 25 100 mV
CLKOUT Duty Cycle TJ= –40°C
TJ= 25°C
TJ= 125°C
22.7
44.1
77
%
%
%
Charging Control
STATUS, FBOW, FBIW, SWENO, IOW, ECON Output
Low Voltage
IOL = 5mA l0.22 0.5 V
STATUS, FBOW, FBIW, SWENO, IOW, ECON Output
High Voltage
IOH = –5mA l2.7 3 V
Power Supply Mode Detection Threshold (Note 6) VINR Pin Falling l155 174 mV
Power Supply Mode Detection Threshold Hysteresis
(Note 6)
29 mV
Minimum VINR Voltage for Startup (Note 6) Not in Power Supply Mode
Low Power Mode Enabled
Low Power Mode Disabled
l
l
380
213
395
225
410
237
mV
mV
High Charging Current Threshold on IOR (Note 6) IOR Rising →ECON Rising l168 195 224 mV
Low Charging Current Threshold on IOR (Note 6) IOR Falling →ECON Falling l95 122 150 mV
Minimum TEMPSENSE % of AVDD to Detect Battery
Disconnected (Note 6)
l94.5 96 97.5 %
VCSPOUT – VCSNOUT Threshold for C/5 Detection
(Note 6)
VCSxOUT Common Mode = 5.0V, RTOTAL from
IMON_OUT to Ground = 24.3kΩ
9 10 11 mV
VCSPOUT – VCSNOUT Threshold for C/10 Detection
(Note 6)
VCSxOUT Common Mode = 5.0V, IOR Falling, RTOTAL
from IMON_OUT to Ground = 24.3kΩ
4.25 5 5.75 mV
FBIW, FBOW PWM Frequency (OSC2) 31.25 kHz
FBIW, FBOW PWM Resolution 8 bits
Internal A/D Resolution 10 bits
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

LT8491
7
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not force voltage on the VCpin.
Note 3: The LT8491E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8491I is guaranteed over the full –40°C to 125°C junction temperature
range.
Note 4: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only; otherwise permanent damage may
occur.
Note 5: Negative voltages on the SW1 and SW2 pins are limited in the
applications by the body diodes of the external NMOS devices M2 and
M3 or parallel Schottky diodes when present. The SW1 and SW2 pins
are tolerant of these negative voltages more than one diode drop below
ground, guaranteed by design.
Note 6: These thresholds are measured by the internal A/D converter. The
A/D reference voltage is AVDD. AVDD, VDD and an additional 2.8mA load are
regulated by LDO33 to create the AVDD reference for these measurements.
The absolute threshold voltages will shift with corresponding changes in
the AVDD voltage.
Note 7: 10V minimum VIN required for solar powered start-up if low power
mode is enabled.
Note 8: The EEPROM has an endurance of at least 100,000 write/erase
cycles. Data retention of 20 years at 85°C, 100 years at 25°C. These
statements are based on published information from vendor.
Note 9: A master device must provide a hold time of at least 300ns for the
SDA signal (referred to the minimum VIH of the SCL signal) to bridge the
undefined region of the SCL falling edge.
PARAMETER CONDITIONS MIN TYP MAX UNITS
EEPROM Characteristics
Endurance (Note 8) 0°C < TJ< 85°C During EEPROM Write Operations 100,000 Cycles
Digital Input/Output SCL, SDA
SDA Input Voltage High (VSDA_VIH)l2.25 V
SDA Input Voltage Low (VSDA_VIL)l0.65 V
SCL Input Voltage High (VSCL_VIH)l2.25 V
SCL Input Voltage Low (VSCL_VIL)l0.65 V
SDA Input Leakage Current (ILEAK_SDA) SDA = 0V and 3.3V l<0.05 ±1 µA
SCL Input Leakage Current (ILEAK_SCL) SCL = 0V and 3.3V l<0.05 ±1 µA
SDA Output Low Voltage (VSDA_OL) 3mA into SDA Pin l0.4 V
I2C Timing Characteristics
Serial Clock Frequency (fSCL)l100 kHz
Serial Clock Low Period (tLOW)l4.7 µs
Serial Clock High Period (tHIGH)l4 µs
Bus Free Time Between Stop and Start (tBUF)l4.7 µs
Start Condition Hold Time (tHD,STA)l4 µs
Start Condition Setup Time (tSU,STA)l4.7 µs
Stop Condition Setup Time (tSU,STO)l4 µs
Data Hold Time (tHD,DAT) (Note 9) l0 ns
Data Setup Time (tSU,DAT)l250 ns
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

LT8491
8
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Solar Powered Charging
Lead-Acid Battery
Solar Powered Charging
Lithium-Ion Battery
Solar Powered Charging Lithium-
Ion Battery – C/10 Termination
Power Supply Mode Charging
Lead-Acid Battery
STATUS, SDA, SCL VOH and VOL
(VDD = AVDD = 3.3V)
LDO33 Load Regulation (Not
Connected to AVDD and VDD)
IMON Output Currents
FBOUT, FBIN, IMONIN, IMONOUT
Voltage Rise vs Power
PARTLY CLOUDY
SUNSET
VBAT
IBAT
TIME OF DAY
9AM
8PM
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
0
3
VBAT (V) AND IBAT
CHARGING STAGE
8491 G01
|IPIN| (mA)
0
V
STATUS
(V)
1
3
2
015
8491 G05
20
5 10
–40°C
125°C 25°C
–40°C
125°C
VOH
VOL
25°C
STATUS
ONLY
LOAD CURRENT (mA)
0
LDO33 (V)
3.1
3.3
3.4
3.2
38
8491 G06
20
4 12 16
25°C
–40°C
125°C
CSxIN-CSxOUT (mV)
–100
PIN CURRENT (µA)
0
175
200
125
150
100
50
75
25
–25 0 50
8491 G07
200
–50 100 150
IMON_OUT
IMON_IN
INTVCC REGULATOR POWER (W)
0
VOLTAGE RISE (%)
0.2
1.0
0.6
0.8
0.4
00.5
8491 G08
2
1 1.5
INTVCC REGULATED
FROM VIN
INTVCC REGULATED
FROM EXTVCC
PARTLY CLOUDY
STAGE 1
STAGE 2
VBAT
IBAT
TIME OF DAY
10AM
12PM
14
17
20
23
26
29
0
2
4
6
8
10
VBAT (V)
IBAT (A)
8491 G02
STATUS
INDICATE
< C/10
PARTLY CLOUDY
STAGE 1
STAGE 2
VBAT
IBAT
TIME OF DAY
9AM
12PM
20
22
24
26
28
30
0
2
4
6
8
10
VBAT (V)
IBAT (A)
8491 G03
STATUS
INDICATES
< C/10
VBAT
IBAT
VIN = 36V
CHARGING TIME (HOURS)
0
12
0
2.5
5.0
7.5
10.0
12.5
15.0
0
3
VBAT (V) AND IBAT
CHARGING STAGE
8491 G04

LT8491
9
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Max Power Point Tracking Perturb and Observe Perturb and Observe
Perturb and Observe Max Power
Point Tracking
Full Panel Scan Single
Power Peak
Full Panel Scan – Partially
Shaded with Dual Power Peaks
Panel Voltage in Low
Power Mode
Panel Voltage in Low
Power Mode
8491 G09
30s/DIV
VPANEL
5V/DIV
IMON_OUT
500mV/DIV
PERTURB AND OBSERVE
FIGURE 37 APPLICATION
8491 G10
0.5s/DIV
VPANEL
5V/DIV
IMON_OUT
200mV/DIV
FIGURE 37 APPLICATION
8491 G11
0.5s/DIV
VPANEL
5V/DIV
IMON_OUT
100mV/DIV
FIGURE 37 APPLICATION
8491 G12
5s/DIV
VPANEL
10V/DIV
IMON_OUT
500mV/DIV
ROTATE PANEL TOWARDS THE SUN
PANEL VOLTAGE
AND CURRENT ARE
AUTOMATICALLY
ADJUSTED TO NEW
MAX POWER POINT
FIGURE 37 APPLICATION
8491 G13
0.5s/DIV
VPANEL
10V/DIV
IMON_OUT
500mV/DIV
IMON_IN
500mV/DIV
FIGURE 37 APPLICATION
POWER PEAK
8491 G15
60ms/DIV
VPANEL
5V/DIV
IMON_OUT
50mV/DIV
SWEN
5V/DIV
29.4V
17.75V
3.3V
FIGURE 37 APPLICATION
8491 G14
0.5s/DIV
VPANEL
10V/DIV
IMON_OUT
500mV/DIV
IMON_IN
500mV/DIV
LOWER POWER PEAK
MAX POWER PEAK
FIGURE 37 APPLICATION
8491 G16
60ms/DIV
VPANEL
5V/DIV
IMON_OUT
50mV/DIV
SWEN
5V/DIV
16.0V
3.3V
FIGURE 37 APPLICATION

LT8491
10
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
FBIR (Pin 1):A/D Input Pin. Connects to FBIN pin to mea-
sure input voltage.
CA (Pin 2):A/D Input Pin. Connects to a resistor divider
to program the I2C address. This pin is measured during
the power up sequence.
TEMPSENSE (Pin 3):A/D Input Pin. Connects to a therm-
istor divider network for sensing battery temperature or a
resistor divider if unused. This pin is frequently monitored
for temperature compensation and enforcing temperature
limits.
VDD (Pin 4):I2C and Control Logic Power Supply Pin.
Connect this pin to LDO33 and AVDD.
FBOW (Pin 5):PWM Digital Output Pin. Connects to
FBOUT through an RCR network to temperature com-
pensate the battery voltage.
FBIW (Pin 6):PWM Digital Output Pin. Connects to FBIN
through an RCR network to adjust the solar panel voltage
for MPPT.
INTVCC (Pin 7):Internal 6.35V Regulator Output Pin.
Connects to the GATEV
CC
pin. INTV
CC
is powered from
EXTVCC when the EXTVCC voltage is higher than 6.4V,
otherwise INTVCC is powered from VIN. Bypass this pin
to ground with a minimum 4.7µF ceramic capacitor. See
HW Config:MODE Pin - Current Conduction Mode for
additional details.
SWEN (Pin 8):Switch Enable Pin. Tie to the SWENO pin.
MODE (Pin 9):Mode Pin. The voltage applied to this pin
sets the operating mode of the switching regulator. Tie
this pin to INTVCC to make discontinuous current mode
active. Tie this pin to ground to operate in discontinuous
current mode for low battery charging currents and con-
tinuous current mode for high battery charging currents.
Do not float this pin. See HW Config:MODE Pin - Current
Conduction Mode for additional details.
IMON_IN (Pin 10):Input Current Monitor and Limit Pin.
The current out of this pin is proportional to the input cur-
rent. See the Applications Information section for more
information.
SHDN (Pin 11):Shutdown Pin. In conjunction with the
UVLO (undervoltage lockout) circuit, this pin is used to
enable/disable the chip. Do not float this pin.
CSN (Pin 12):The (–) Input to the Inductor Current Sense
and Reverse Current Detect Amplifier.
CSP (Pin 13):The (+) Input to the Inductor Current Sense
and Reverse Current Detect Amplifier. The VCpin voltage
and built-in offsets between the CSP and CSN pins set the
inductor current trip threshold.
LDO33 (Pin 14):3.3V Regulator Output. This pin pro-
vides power to the VDD and AVDD pins. Bypass this pin to
ground with a minimum 4.7µF ceramic capacitor.
FBIN (Pin 15):Input Feedback Pin. This pin is connected
to the input error amplifier input.
FBOUT (Pin 16):Output Feedback Pin. This pin connects
the error amplifier input to an external resistor divider
from the output.
IMON_OUT (Pin 17):Output Current Monitor and Limit
Pin. The current out of this pin is proportional to the aver-
age output current. See the Applications Information sec-
tion for more information.
VC(Pin 18):Error Amplifier Output Pin. Tie the external
compensation network to this pin.
SS (Pin 19):Soft-Start Pin. Place 100nF of capacitance
from this pin to ground. Upon start-up, this pin will be
charged by an internal resistor to 2.5V.
CLKOUT (Pin 20):Switching Regulator Clock Output Pin.
CLKOUT will toggle at the same frequency as the switch-
ing regulator oscillator (OSC1 on the Block Diagram) or
as the SYNC pin but is approximately 180° out-of-phase.
CLKOUT can also be used as a temperature monitor of the
switching regulator since the CLKOUT duty cycle varies
linearly with the junction temperature of the switching
regulator. It is connected to the CLKDET pin through an
RC filter. The CLKOUT pin can drive capacitive loads up
to 200pF.

LT8491
11
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
SYNC (Pin 21):To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock. The
high voltage level of the clock needs to exceed 1.3V, and
the low level should be less than 0.5V. Drive this pin to
less than 0.5V to revert to the internal free-running clock
(OSC1 in the Block Diagram).
RT (Pin 22):Timing Resistor Pin. Adjusts the switching
regulator frequency (OSC1) when SYNC is not driven by
a clock. Place a resistor from this pin to ground to set
the free-running frequency of OSC1. Do not float this pin.
BG1, BG2 (Pin 23/Pin 25):Bottom Gate Drive. Drives the
gates of the bottom N-channel MOSFETs between ground
and GATEVCC.
GATEVCC (Pin 24):Power Supply for Gate Drivers. Must
be connected to the INTVCC pin. Do not power from any
other supply. Locally bypass to ground.
BOOST1, BOOST2 (Pin 33/Pin 27):Boosted Floating
Driver Supply. The (+) terminal of the bootstrap capacitor
connects here. The BOOST1 pin swings from a diode volt-
age below GATEVCC up to VIN + GATEVCC. The BOOST2
pin swings from a diode voltage below GATEV
CC
up to
VBAT + GATEVCC.
SW1, SW2 (Pin 31/Pin 29):Switch Nodes. The (–) termi-
nal of the bootstrap capacitors connect here.
TG1, TG2 (Pin 32/Pin 28):Top Gate Drive. Drives the
top N-channel MOSFETs with voltage swings equal to
GATEVCC superimposed on the switch node voltages.
SRVO_FBIN (Pin 35):Open-Drain Logic Output. This pin
is pulled to ground when the input voltage feedback loop
is active. This pin is unused for most LT8491 applications
and can be floated.
SRVO_IIN (Pin 36):Open-Drain Logic Output. This pin is
pulled to ground when the input current feedback loop is
active. This pin is unused for most LT8491 applications
and can be floated.
SRVO_IOUT (Pin 37):Open-Drain Logic Output. This pin
is pulled to ground when the output current feedback loop
is active. This pin is unused for most LT8491 applications
and can be floated.
SRVO_FBOUT (Pin 38):Open-Drain Logic Output. This
pin is pulled to ground when the output voltage feedback
loop is active. This pin is unused for most LT8491 applica-
tions and can be floated.
EXTVCC (Pin 40):External VCC Input. When EXTVCC
exceeds 6.4V (typical), INTVCC will be powered from this
pin. When EXTVCC is lower than 6.22V (typical), INTVCC
will be powered from VIN. See HW Config:MODE Pin -
Current Conduction Mode for additional details.
CSNOUT (Pin 41):The (–) Input to the Output Current
Sense Amplifier.
CSPOUT (Pin 42):The (+) Input to the Output Current
Sense Amplifier. This pin and the CSNOUT pin measure
the voltage across the sense resistor to provide the output
current signals.
CSNIN (Pin 44):The (–) Input to the Input Current Sense
Amplifier. This pin and the CSPIN pin measure the voltage
across the sense resistor to provide the instantaneous
input current signals.
CSPIN (Pin 45):The (+) Input to the Input Current Sense
Amplifier.
VIN (Pin 46):Main Input Supply Pin. Must be bypassed
to local ground plane.
ECON (Pin 48):Digital Output Pin. Optional control output
signal used to disconnect EXTVCC from the battery when
the average charge current drops below a predetermined
threshold.
SWENO (Pin 49):Digital Output Pin. Connect to SWEN.
Enables the switching regulator. A 200k pull-down resistor
is required from this pin to ground.
IOW (Pin 50):Digital Output Pin. Connects to IMON_OUT
through a resistor. By switching the pin between logic low
and high impedance, the total RIMON_OUT changes, which
changes the output current limit.
STATUS (Pin 51):Digital Output Pin. When used with an
LED, this signal provides a visual indication of the prog-
ress of the charging algorithm.

LT8491
12
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
NC (Pins 52, 60): Not connected.
IIR (Pin 53):A/D Input Pin. Connects to IMON_IN to read
input current. Used to manage MPPT and for telemetry.
VINR (Pin 54):A/D Input Pin. Connects to resistive divider
on VIN to measure input voltage. Used for telemetry and
to manage MPPT and startup.
CLKDET (Pin 56):A/D Input Pin. Connects to CLKOUT
through an RC filter to detect the duty cycle of CLKOUT.
Used to manage startup.
FBOR (Pin 57):A/D Input Pin. Connects to FBOUT pin to
read charger output voltage. Used to manage the charg-
ing algorithm.
AVDD (Pin 58):A/D Positive Reference Pin. Tie this pin to
VDD and LDO33.
SDA (Pin 61): I2C Bidirectional Data Pin.
SCL (Pin 63): I2C Clock Input Pin (100kHz Maximum).
IOR (Pin 64):A/D Input Pin. Connects to IMON_OUT pin
to read the charger output current. Used for telemetry and
to manage the charging algorithm.
GND (Pins 55, 59, 62, Exposed Pad 65):Ground. Tie
directly to local ground plane.

LT8491
13
Rev. 0
For more information www.analog.com
BLOCK DIAGRAM
+
–
10
8491 BD
33
BOOST1
32
TG1
31
SW1
24
GATEVCC
A8
23
BG1
9MODE
13 CSP
12 CSN
16 VIN
20 CLKOUT
56 CLKDET
22 RT
21 SYNC
15 SS
11 SHDN
25
BG2
29
SW2
28
TG2
18
VC
7
INTVCC
14
58
LDO33
40
EXTVCC
4
VDD
48
ECON
37
SRVO_IOUT
42
CSPOUT
41
CSNOUT
NC
NC
AVDD
27
BOOST2
+
–A9
+
–
A5
44 CSNIN
45 CSPIN
BUCK-BOOST
LOGIC
START-UP AND
FAULT LOGIC
OSC1
OI_OUT
CI_IN
ADC
AVDD
01UV_INTVCC
UV_GATEVCC UV_VIN UV_LD033
+
–
1.234V
2.5V
8SWEN
49 SWENO
36 SRVO_IIN NC
+
–
6.4V
305k
6.35V REG6.35V REG
3.3V REGFEC
I2C INTERFACE
(100kHz
COMPATIBLE),
TELEMETRY,
CONFIG,
CONTROL,
CHARGING,
MPPT LOGIC
INTERNAL
SUPPLY1
INTERNAL
SUPPLY2
VIN
+
–
A7
+
–
EA2
1.208V
1.205V
1.208V
1.207V
10 IMON_IN
53 IIR
54 VINR
+
–
EA3
15 FBIN
+
–
A6
17
IMON_OUT
50
IOW
64
IOR
AVDD
10
+
–
EA1
5
FBOW
57
FBOR
16
FBOUT
+
–
+
–
+
–
EA4
38
SRVO_FBOUT
ADC
AVDD
10
1FBIR
6FBIW
ADC
AVDD
10
3TEMPSENSE ADC
PWM
PWM
AVDD
AVDD
VDD VDD
10
ADC
AVDD
10
ADC
AVDD
10
ADC
AVDD
AVDD
EEPROM
VDD
35 SRVO_FBIN NC
ADC
OSC2
61 SDA
51
STATUS
59
GND
2
CA
VDD VDD
AVDD
63 SCL
SOLAR
PANEL
REGHARGABLE
BATTERY
NTC
Figure1. Block Diagram

LT8491
14
Rev. 0
For more information www.analog.com
OPERATION
OVERVIEW
The LT8491 is a powerful and easy to use battery charging
controller with automatic maximum power point track-
ing (MPPT), temperature compensation and an I2C inter-
face for telemetry, status, control and configuration. The
LT8491 is based on the LT8705 buck-boost controller
with additional battery charging and MPPT control func-
tions. Refer to the LT8705 data sheet for more detailed
information about the switching regulator portions of the
LT8491.
Several reference applications are included in this data
sheet to simplify system design. Many battery-charging
applications can be implemented using one of the refer-
ence applications with little or no modification required.
Various charging parameters can be configured via the
digital I2C interface and can be made permanent in the
on-chip EEPROM. Since the battery charging and MPPT
are controlled by the LT8491, no firmware development
is required. Interfacing to the I2C pins is only required
to configure and/or monitor the charger. For reference,
factory default I2C configuration settings are listed in the
I2C Register Map section.
The LT8491 includes four different forms of regulation:
output current, input current, input voltage and output
voltage (EA1 - EA4 respectively as shown in Figure1). The
commanded inductor current is limited by whichever form
of regulation requires the lowest voltage on the VCpin.
When powered by a solar panel, the MPPT function uses
input voltage regulation to locate and track the maximum
power point of the solar panel. Input current regulation is
used to limit the maximum current drawn from the input
supply to safe levels. The output current regulation sets
the maximum battery charging current, and the output
voltage regulation is used to set the maximum battery
charging voltage.
The LT8491 offers user configurable charge timers. If a
timer has been set and subsequently expires, the LT8491
will halt charging and communicate this through the I2C
interface and the STATUS pin. Options for automatic
restart of the charging cycle are discussed later in the
Configure Automatic Restart section.
The LT8491 also includes a TEMPSENSE pin, which can
be connected to an NTC resistor divider network ther-
mally coupled to the battery pack. The TEMPSENSE pin
can facilitate several functions including temperature
compensated charging, battery temperature telemetry,
and charging disable when the battery is outside of safe
temperature limits. Detection of the NTC resistor can also
give an indication to the charger if the battery is connected
or not.
The LT8491 also provides charging telemetry and status
through the I2C interface and the STATUS pin. Refer to
the Telemetry Registers and Status Registers sections
for the I2C indicators. The behavior of the STATUS pin is
described in the STATUS Indicator Pin section.
I2C SERIAL INTERFACE
The LT8491 includes a slave I2C compatible interface
facilitating digital control of the charger settings and digi-
tal readouts of telemetry and status. The following sub-
sections explain how to read and write data to the LT8491.
The I2C Register Map and I2C Register Descriptions sec-
tions provide detailed descriptions of all the I2C registers
and their functions.
I2C: START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a
START (S) condition by transitioning SDA from high to
low while SCL is high, as shown in Figure2. When the
master has finished communicating with the slave, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission.
I2C: ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between the transmitter and receiver to indicate that the
most recent byte of data was received. When the slave is
the receiver, it pulls down the SDA line so that it remains
LOW during this pulse to acknowledge receipt of the data.
If the slave fails to acknowledge, by leaving SDA high,
then the master may abort the transmission by generat-
ing a STOP condition. When the master is receiving data

LT8491
15
Rev. 0
For more information www.analog.com
OPERATION
from the slave, the master pulls down the SDA line during
the clock pulse to indicate receipt of the data. After the
last byte has been received the master leaves the SDA
line HIGH (NACK) and issues a STOP (P) condition to
terminate the transmission.
I2C: Chip Addressing
The CA pin is used to select one of four 7-bit chip
addresses (A6:A0). This address is sent by the master
to identify which IC it is transferring data with. The CA
pin can be tied to ground, AVDD or connected to a resis-
tor divider to select the desired chip address. See the
HW Config:I2C Chip Address section for more detailed
information.
I2C: Clock Stretching
The charger supports clock speeds up to 100kHz for the
I2C interface. The master is required to support I2C clock
stretching to properly communicate with this charger
(slave).
I2C: Data Transfer Transactions
The LT8491 supports byte-writes, byte-reads, and word-
reads using the transaction formats shown in Figure3 to
Figure5 respectively. Figure3 shows the required for-
mat for writing a byte of data to the LT8491. Again, the
required chip address (A6:A0) depends on the CA pin.
A single byte of data is read from the LT8491 using the
byte-read transaction shown in Figure 4. The register
address selects the data byte that is returned. This trans-
action requires four I2C bytes to read one byte of chip data.
The word-read transaction, shown in Figure5, should be
used to read telemetry such as power, volts and amps
that is stored in 16-bit formats. The word-read transac-
tion ensures that both bytes of data are properly paired
together and can be combined into a valid word. Due
to the time latency between I2C transactions, combining
bytes from two byte-read transactions may not result in
valid 16-bit telemetry data.
Referring again to Figure5, the register address selects
the first byte of data (DATA0) that is returned. Data from
the next higher byte address is returned in the second byte
(DATA1). When reading Word or Long Word data, note
that the least significant byte is at the lowest address loca-
tion (little-endian). B0 of the register address should typi -
cally be set to 0 since all words in the LT8491 are aligned
to even register addresses. This transaction requires five
I2C bytes to read two bytes of chip data and must be
repeated for each subsequent word of data that is read.
I2C: Powering the Interface
The I2C control logic and I/O are powered from the VDD
pin. VDD is ultimately supplied from either VIN or EXTVCC
when the SHDN pin is high. This can be seen in the block
diagram which shows that VIN and EXTVCC supply the
INTVCC regulator that, in turn, supplies the LDO33 regula-
tor which is finally connected to VDD. After SHDN and VDD
rise, I2C communication is enabled after a delay of 10ms
(typical). Note that the LT8491 contains diodes from the
SDA and SCL pins to the VDD pin (see Figure8). These
diodes are normally reverse biased and have no effect on
the I2C bus. However, when the LT8491 is unpowered, the
VDD pin voltage will drop and may pull down on the SDA
and SCL pins, thus effecting communication on the bus.
Figure2. Data Transfer Over I2C Bus
A6 - A0 B7 - B0 B7 - B0
9
ACK
8491 F02
ACKACKCHIP
ADDRESS
START
CONDITION
STOP
CONDITION
R/WDATADATA
89898
S
SDA
SCL 1 - 71 - 71 - 7
P

LT8491
16
Rev. 0
For more information www.analog.com
OPERATION
Figure3. I2C Byte-Write Transaction
Figure4. I2C Byte-Read Transaction
Figure5. I2C Word-Read Transaction
CHIP ADDR
A6:A0
FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW)
A
: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
FROM SLAVE TO MASTER
b7:b0 b7:b0 8491 F03
REG ADDR DATAS
0 0 0 0
A A A PW
CHIP ADDR
A6:A0
CHIP ADDR
A6:A0b7:b0 b7:b0
8491 F04
REG ADDR D ATAS S R
0 0 0 1
A A A
01
A PW
CHIP ADDR
A6:A0
CHIP ADDR
A6:A0b7:b0 b7:b0
8491 F05
REG ADDR DATA0S S R
0 0 0 1
A A A
1
A PW
b7:b0
DATA1
0
A
I2C DATA
Data: Memory Regions
Data in the LT8491 is arranged into six regions as shown
in Table1.
Table1. LT8491 I2C Addressable Memory Regions
REGION TYPE
I2C REG
ADDR RANGE DESCRIPTION
Telemetry Registers 0x00-0x11 Charging telemetry.
Status Registers 0x12-0x1F Charging and system status.
Control Registers 0x20-0x27 Control charging on/off and
EEPROM access.
Configuration Registers 0x28-0x5B Charger configuration settings.
Manufacturer Registers 0x5C-0x61 Manufacturer Data.
Boot EEPROM 0x88-0xBD Non-volatile storage of start-up
configuration.
Telemetry Region:These read-only registers indicate
telemetry such as temperature, voltage, current, power
and efficiency. These word-sized values must be read
using the I
2
C word-read transaction to avoid retrieving
mismatched bytes (see I2C: Data Transfer Transactions).
See the Telemetry Operation and Telemetry Registers sec-
tions for further telemetry information.
Status Region:These read-only registers indicate status
such as charging state, solar panel state, faults, timers
and others. Detailed status register descriptions are pro-
vided in the Status Registers section.
Control Region:These read-write registers are used to
start and stop the charger, write to the EEPROM, reset the
chip and other related functions. The contents of these
registers revert to their default values, as listed in the
I2C Register Map, after power is cycled or the CTRL_
RESTART_CHIP register is written to 0x99. Detailed con-
trol register descriptions are provided in the I2C Register
Descriptions section.
Configuration Region:These read-write registers deter-
mine the charger settings such as timer limits, restart
options, VBAT stage voltages, and many others. After
power-up or reset, the configuration registers are auto-
matically loaded with data from the EEPROM (see the
Startup Sequence section). Factory default EEPROM val-
ues are provided in the I2C Register Map. Detailed con-
figuration register descriptions are provided in the I
2
C
Register Descriptions section.
Manufacturer Region:These read-only registers indicate
manufacturer data that is determined at the factory.

LT8491
17
Rev. 0
For more information www.analog.com
OPERATION
Boot Region:The boot data is stored in non-volatile
EEPROM and is copied into the configuration registers
during startup or after the CTRL_RESTART_CHIP register
is written to 0x99, as described in the Startup Sequence
section.
Each EEPROM location in the boot region corresponds
to a register in the configuration region. As such, the
boot region data is arranged in the exact same order and
format as in the configuration region but is read from
an I2C address 0x60 higher than the corresponding con-
figuration register address. Reading of the boot data is
described in the EEPROM: Reading section.
Writing directly to the EEPROM is prohibited. Instead,
data can be copied from the configuration registers into
the EEPROM by writing to appropriate control registers.
Further information about writing the EEPROM is in the
EEPROM: Writing section.
Data: Bytes, Words and Long Words
LT8491 data is stored in three sizes:bytes, words (2
bytes) and long words (4 bytes). Tables are provided
throughout this data sheet indicating the sizes for each
piece of data. Since the I2C bus addresses one byte at a
time, word and long word data is spread across multiple
I2C register address locations.
Words and long words are stored in an arrangement com-
monly referred to as little endian. The least significant byte
(LSB) is stored at the lower I2C register address location.
The next most significant byte (MSB) is stored at the next
higher I2C register address and so on.
As an example, suppose the TELE_IOUT register is indi-
cating output current of 5.274 Amps (see Telemetry
Registers). This 16-bit register, starting at I2C address
0x08 will contain the value 0x149A. The two bytes com-
prising TELE_IOUT are stored as shown:
Table2. Example of TELE_IOUT Word Storage
I2C REG ADDRESS BYTE VALUE
0x08 0x9A
0x09 0x14
Reading TELE_IOUT with the word-read transaction from
register address 0x08 returns two bytes, DATA0 (0x9A)
and then DATA1 (0x14) indicating 5.274 Amps.
The temperature compensation coefficients, in the con-
figuration region, are the only data stored as long words.
For example, suppose CFG_TC1 has the value 1.54e-3
stored as the 32-bit floating point value 0xBAC9D9D3.
This data is stored as follows in Table3:
Table3. Example of CFG_TC1 Long Word Storage
I2C REG ADDRESS BYTE VALUE
0x56 0xD3
0x57 0xD9
0x58 0xC9
0x59 0xBA
Reading the entire long word requires four byte-read
transactions, or two word-read transactions. Writing the
entire long word requires four byte-write transactions at
addresses 0x56 through 0x59.
Data: Min/Max Register Values
Some configuration registers have minimum and maxi-
mum acceptable values (i.e. CFG_VS3_25C). The value
limits for each register (if any) are listed in the I
2
C Register
Descriptions section. If a configuration register is written
to a value outside of the min/max limits, the LT8491 will
automatically modify the register contents to the factory
default register value.
Data: Access Permissions
I2C read and/or write access to various regions is con-
ditional. Table 4 and Table 5 illustrate the conditions
required to access the various regions. When writing to
a register, while write access permission is denied, the
data is ignored and not written to the addressed location.
When reading from a location while read access permis-
sion is denied, the returned data is all zeros.
As shown in Table4 and Table5, most address loca-
tions can be read unconditionally after startup is com-
plete. However, the boot region is also unreadable while
EEPROM writing is ongoing and will return 0x00 during
that time.

LT8491
18
Rev. 0
For more information www.analog.com
OPERATION
Table4. Register Access Permissions (Except Control Region)
MEMORY REGION REGISTER NAME I2C REG ADDRESS RANGE READ ACCESS WRITE ACCESS
Telemetry All 0x00-0x11 Always1Never
Status All 0x12-0x1F Always1Never
Configuration All 0x28-0x5B Always1Only when
CHRG_LOGIC_ON=03and
CTRL_EE_WRT_EN≠0xCC and
SYSTEM_BUSY=b003.
Manufacturer All 0x5D-0x61 Always1Never
Boot All 0x88-0xBD Always1, 2 Never
See EEPROM: Writing section.
1. Except when chip is powered down or the I2C interface has not been activated yet during the startup sequence.
2. Except when EEPROM write operation is occurring. This is indicated by a read of 10b from STAT_SYSTEM→SYSTEM_BUSY, or a read of 1 from
CTRL_WRT_TO_BOOT→RDY_BUSY.
3. CHRG_LOGIC_ON is a read-only bit in the STAT_CHARGER register. It is cleared shortly after CTRL_CHRG_EN is written 0x00. SYSTEM_BUSY are
read-only bits in the STAT_SYSTEM register.
Table5. Control Region Access Permissions
REGISTER NAME
I2C
REG
ADDR
READ
ACCESS
WRITE REQUIRES…
CHRG_LOGIC_ON3= 0
CTRL_EE_WRT_EN ≠
0xCC
CTRL_EE_WRT_EN =
0xCC SYSTEM_BUSY3= 00b
CTRL_WRT_TO_BOOT 0x20 Always1✓ ✓ ✓
CTRL_EE_WRT_EN 0x21 ✓ ✓
CTRL_HALT_STARTUP 0x22
CTRL_CHRG_EN 0x23 ✓4✓ ✓
CTRL_RESTART_CHIP 0x24 ✓ ✓
CTRL_RESET_FLAG 0x25 ✓
CTRL_UPDATE_TELEM 0x26 ✓ ✓ ✓
Reserved 0x27 Writes to this reserved register always ignored.
4. Only required when writing 1 to CHRG_EN bit.
All I2C byte-write registers have conditions under which
the data is accepted. These conditions prevent changes to
the charger configuration while the charging is ongoing
and to help prevent inadvertent changes to the configura-
tion and/or EEPROM.
STARTUP SEQUENCE
Figure6 illustrates the startup sequence for the LT8491.
Not all details are shown. The sequence is initiated when
the V
DD
pin rises above 2.7V (typical). If the device is
already powered on and CTRL_CHRG_EN=0, the startup
sequence can be re-initiated by writing CTRL_RESTART_
CHIP to 0x99.
At the beginning of the startup sequence the I2C interface
is disabled and the default values for the telemetry, sta-
tus and control registers are set as indicated in the I2C
Register Map section.
Next, a CRC check of the EEPROM boot region and fac-
tory settings is performed. If the boot region fails the
CRC check, the LT8491 recalculates the CRC indefinitely
until the CRC check passes, or the process is interrupted
by writing CTRL_HALT_STARTUP to 0x5A. If startup
is halted then the configuration registers revert to their
factory default values, as listed in the I2C Register Map,
before completing startup. If the factory settings fail the
CRC check, the LT8491 recalculates the CRC indefinitely

LT8491
19
Rev. 0
For more information www.analog.com
OPERATION
until the CRC check passes. More information about the
CRC checking is discussed in the CRC Operation section.
When the boot CRC and the factory CRC check passes,
the STAT_SYSTEM→BOOT_SUCCESS bit is set to 1.
Subsequently, CTRL_CHRG_EN is preset with the value
read from BOOT_MISC in the EEPROM. This determines
if the charging starts automatically, at the end of the
sequence, or not.
Figure6. Startup Sequence
8491 F06
VDD RISES ABOVE 2.7V (TYPICAL)
STARTUP
STARTUP COMPLETE
• ENABLE I2C READ COMMANDS
• ENABLE I2C WRITE TO CTRL_HALT_STARTUP REGISTER
CTRL_HALT_STARTUP=0X5A
&
CRC_ERR_FACTORY=0
?
NO
NOYES
• I2C INTERFACE IS DISABLED
• SET ALL TELEMETRY AND CONTROL REGISTERS TO DEFAULT VALUES
• SET ALL STATUS REGISTERS TO THEIR APPROPRIATE VALUES
• SET BOOT_SUCCESS TO 1
• COPY BOOT_INIT_CHRG_EN TO CTRL_CHRG_EN
SET CONFIGURATION REGION TO
FACTORY DEFAULT VALUES
• COPY EEPROM BOOT REGION TO CONFIGURATION REGION AND CALCULATE CRC OF CONFIGURATATION REGION
• COMPARE CRC OF CONFIGURATION REGION TO BOOT_CRC
• UPDATE STAT_BOOT_CRC VALUE
• UPDATE CRC_ERR_BOOT BIT
• COMPARE CRC OF FACTORY SETTINGS TO MFR_DATA3
• UPDATE CRC_ERR_FACTORY BIT
YES
SET SYSTEM_BUSY TO 00b
START BATTERY CHARGING
SEE FIGURE 8
YES NO
CRC_ERR = 0
?
CHRG_EN = 1
?

LT8491
20
Rev. 0
For more information www.analog.com
OPERATION
BATTERY CHARGING ALGORITHM
The LT8491 implements a CCCV charging algorithm.
The idealized charging profile is shown in Figure7 and
assumes constant temperature and adequate input power.
As battery temperature and illumination conditions on the
panel change, the actual current and voltage seen by the
battery will vary accordingly.
Figure8 illustrates a flow chart for the charging algorithm.
Many options are available to configure the algorithm as
needed. Options include…
• Stage3 is enabled or not
• Stop charging when IOUT < C/10 or not
• Timer expiration indicates a fault or not
• Various automatic restart options
Footnotes at the bottom of Figure8 indicate configurable
aspects of the algorithm and the related thresholds.
Stage0: Trickle Charging
In Stage0 the LT8491 charges the battery with a reduced
constant current that is hardware configurable (see HW
Config:Output Current Sense and Limit section). This
stage typically occurs for battery voltages between 35%
to 70% of the Stage2 battery voltage limit (VS2). However,
the Stage0 battery thresholds are I
2
C configurable as
discussed in the Configure VBAT for Stages 0, 1 and 3 sec-
tion. Stage0 charging is indicated in the STAT_CHARGER
register when the CHRG_STAGE bits are 000b and the
CHRG_LOGIC_ON bit is 1.
Stage1: Full Constant Current
At higher battery voltage, the LT8491 enters Stage1 and
charges the battery with full constant current (see HW
Config: Output Current Sense and Limit section). Stage1
typically occurs for battery voltages between 70% to 98%
of the Stage2 battery voltage limit. The threshold for
entering Stage1 is I2C configurable as discussed in the
Figure7. Typical Battery Charging Cycle
STAGE 0
TRICKLE CHARGE
STAGE 1
CONSTANT CURRENT
STAGE 2
CONSTANT VOLTAGE
STAGE 3
FLOAT VOLTAGE
STAGE 2 VOLTAGE
REGULATION
STAGE 1 OUTPUT
CURRENT LIMIT
C/10
C/5
VBAT
VS1_S2
VS2_S1
VS0_S1
V
S0_UV
VS3_S0
VS1_S0
V
UV_S0
IOUT
STAGE 3 VOLTAGE
REGULATION
8491 F07
STAGE 2 LOWER OUTPUT
CURRENT LIMIT
VBAT DROP CAUSES TRANSITION TO STAGE 0
VBAT DROP CAUSES TRANSITION TO UNDERVOLTAGE
VBAT DROP CAUSES TRANSITION TO STAGE 1
VOLTAGES BELOW OR
CURRENTS ABOVE PRESET
LEVELS DURING STAGE 3 CAUSES
TRANSITION TO STAGE 0