Analog devices Aducm355 Quick user guide

ADuCM355 Hardware Reference Manual

UG-1262

One Technology Way •P.O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

ADuCM355 Hardware Reference Manual

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 312

SCOPE

This manual provides a detailed description of the ADuCM355 functionality and features. See the ADuCM355 data sheet for the

functional block diagram.

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 2 of 312

TABLE OF CONTENTS

Scope .................................................................................................. 1

Revision History ............................................................................... 9

Using the ADuCM355 Reference Manual.................................. 11

Introduction to the ADuCM355 .................................................. 12

Main Features of the ADuCM355 ........................................... 12

Clocking Architecture.................................................................... 14

Clocking Architecture Operation ............................................ 14

Required Clock Ratio Between Digital Die and Analog Die

System Clocks ............................................................................. 14

Digital Die Clock Features ........................................................ 14

Analog Die Clock Features ....................................................... 14

Clock Gating ............................................................................... 15

Connecting AFE Die Clock to Digital Die Clock Input ....... 15

Key Protection for CTL Register.............................................. 18

Oscillator Control Register ....................................................... 18

Clock Control 0 Register ........................................................... 18

Clock Dividers Register ............................................................. 19

User Clock Gating Control Register........................................ 19

Clocking Status Register............................................................ 20

Clock Divider Configuration Register .................................... 21

Clock Gate Enable Register....................................................... 21

Clock Select Register.................................................................. 22

GPIO Clock Mux Select to GPIO1 Pin Register .................... 22

Key Protection for CLKCON0 Register .................................. 22

Clock Control of Low Power TIA Chop, Watchdog, and

Wake-Up Timers Register ........................................................ 23

Key Protection for OSCCON Register .................................... 23

Oscillator Control Register ....................................................... 23

High Power Oscillator Configuration Register...................... 24

Power Mode Configuration Register....................................... 24

Power Management Unit .............................................................. 25

Power Management Unit Features .......................................... 25

Power Management Unit Operation....................................... 26

Code Examples ........................................................................... 27

Monitor Voltage Control .......................................................... 28

Power Supply Monitor Interrupt Enable Register................. 30

Power Supply Monitor Status Register ................................... 30

Power Mode Register................................................................. 31

Key Protection for PWRMOD and SRAMRET Register ..... 31

Control for Retention SRAM During Hibernate Mode

HPBUCK Control Register....................................................... 32

Control for SRAM Parity and Instruction SRAM Register.. 32

Initialization Status Register..................................................... 33

Power Modes Register ............................................................... 34

Key Protection for PWRMOD Register.................................. 34

Arm Cortex-M3 Processor............................................................ 35

Arm Cortex-M3 Processor Features ....................................... 35

Arm Cortex-M3 Processor Operation .................................... 36

Arm Cortex-M3 Processor Related Documents.................... 36

System Resets .................................................................................. 37

Digital Die Reset Operation...................................................... 37

Digital Die Reset Status Register.............................................. 40

Always On Reset Status Register.............................................. 40

Analog Die Status Register........................................................ 40

Programming, Protection, and Debug........................................ 41

Booting ........................................................................................ 41

Security Features ........................................................................ 41

Safety Features ............................................................................ 41

System Exceptions and Peripheral Interrupts............................ 42

Cortex-M3 and Fault Management......................................... 42

Interrupt Sources from the Analog Die .................................. 44

Clearing Analog Die Interrupt Sources .................................. 45

Cortex-M3 NVIC Register List ................................................ 46

External Interrupt Configuration ............................................ 47

Interrupts......................................................................................... 48

........................................................................................................... 49

External Interrupt Configuration 0 Register.......................... 49

External Wake-Up Interrupt Status Register ......................... 50

External Interrupt Clear Register............................................. 50

Nonmaskable Interrupt Clear Register................................... 50

Analog Die Interrupt Enable Register..................................... 51

Analog Die Circuitry Summary ................................................... 52

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ADC, High Speed DAC, and Associated Amplifiers

Operating Mode Configuration................................................52

System Bandwidth Configuration ............................................52

AFE Configuration Register ......................................................55

ADC Circuit.....................................................................................57

ADC Circuit Overview...............................................................57

ADC Circuit Features.................................................................57

ADC Circuit Operation..............................................................58

ADC Transfer Function.............................................................58

ADC Low Power Current Input Channels..............................59

ADC Input Circuit......................................................................60

ADC Postprocessing Filter Options.........................................60

Averaging, Statistics, and Outlier Detection Options............61

Internal Temperature Sensor Channels...................................62

ADC Initialization ......................................................................63

ADC Calibration .........................................................................64

ADC Digital Signal Processor (DSP) Built In Self Test.........65

Voltage Reference Options........................................................66

ADC Configuration Register.....................................................69

ADC Output Filters Configuration Register...........................70

Raw Result Register ....................................................................71

DFT Result, Real Part Register..................................................71

DFT Result, Imaginary Part Register .......................................72

Sinc2 and Supply Rejection Filter Result Register .................72

Temperature Sensor 0 Result Register .....................................72

Analog Capture Interrupt Enable Register..............................72

Analog Capture Interrupt Register...........................................73

AFE DSP Configuration Register .............................................74

Temperature Sensor 0 Configuration Register.......................75

High Power and Low Power Buffer Control Register ...........75

Number of Repeat ADC Conversions Register ......................76

Buffer Configuration Register...................................................76

Calibration Lock Register ..........................................................76

Offset Calibration LPTIA0 Channel Register .........................77

Gain Calibration for LPTIA0 Channel Register.....................77

Offset Calibration LPTIA1 Channel Register .........................77

Gain Calibration for LPTIA1 Channel Register.....................77

Offset Calibration High Speed TIA Channel Register ..........78

Gain Calibration for High Speed TIA Channel Register ......78

Offset Calibration Voltage Channel (PGA Gain = 1) Register

.......................................................................................................78

Gain Calibration Voltage Input Channel (PGA Gain = 1)

Offset Calibration Voltage Channel (PGA Gain = 1.5)

Gain Calibration Voltage Input Channel (PGA Gain = 1.5)

Offset Calibration Voltage Input Channel (PGA Gain = 2)

Gain Calibration Voltage Input Channel (PGA Gain = 2)

Offset Calibration Voltage Input Channel (PGA Gain = 4)

Gain Calibration Voltage Input Channel (PGA Gain = 4)

Offset Calibration Voltage Input Channel (PGA Gain = 9)

Gain Calibration Voltage Input Channel (PGA Gain = 9)

Offset Calibration Temperature Sensor Channel 0 Register 82

Gain Calibration Temperature Sensor Channel 0 Register ..82

Minimum Value Check Register ..............................................82

Minimum Slow Moving Value Register ..................................82

Maximum Value Check Register..............................................83

Maximum Slow Moving Register.............................................83

Delta Check Register ..................................................................83

Statistics Module Configuration Register ...............................83

Mean Output Register................................................................84

Key Access for DSPUPDATEEN Register ..............................84

Digital Logic Test Enable Register............................................84

Temperature Sensor 1 Control Register ..................................84

Low Power Potentiostat Amplifiers and Low Power TIAs.......85

Low Power Potentiostat Amplifiers .........................................85

Low Power TIAs .........................................................................85

Low Power DACs........................................................................88

Circuits .............................................................................................92

Circuits .............................................................................................93

Low Power TIA Control Bits Channel 0 Register ..................93

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Low Power TIA Switch Configuration for Channel 0 Register

....................................................................................................... 94

Low Power TIA Control Bits Channel 1 Register.................. 95

Low Power TIA Switch Configuration for Channel 1 Register

....................................................................................................... 97

LPDAC0 Data Out Register...................................................... 98

LPDAC0 Switch Control Register............................................ 98

LPDAC0 Control Register ........................................................ 99

LPDAC1 Data Out Register...................................................... 99

LPDAC1 Switch Control Register.......................................... 100

LPDAC1 Control Register ...................................................... 100

Low Power Reference Control Register ................................ 101

High Speed TIA Circuits ............................................................. 102

Key Features.............................................................................. 102

Using DE0 and DE1 Inputs with the High Speed TIA ....... 104

External RTIA Selection............................................................. 104

High Speed RTIA Configuration Register............................... 106

DE1 High Speed TIA Resistor Configuration Register ...... 106

DE0 High Speed TIA Resistor Configuration Register ...... 107

High Speed TIA Amplifier Configuration Register ............ 107

High Speed DAC Circuits ........................................................... 108

High Speed DAC Output Signal Generation .......................108

High Speed DAC Core Power Modes ................................... 108

Recommended Configuration in Hibernate Mode ............. 109

High Speed DAC Filter Options ............................................ 109

High Speed DAC Output Attenuation Options .................. 109

Coupling an AC Signal from High Speed DAC onto the DC

Level Set by Low Power DAC................................................. 109

Avoiding Incoherency Errors Between Excitation and

Measurement Frequencies During Impedance Measurements

..................................................................................................... 110

Calibrating the High Speed DAC........................................... 110

High Speed DAC Configuration Register............................. 113

Direct Write to DAC Output Control Value Register ........ 113

DAC DC Buffer Configuration Register............................... 113

DAC Gain Register................................................................... 114

DAC Offset with Attenuator Enabled (Low Power Mode)

DAC Offset with Attenuator Disabled (Low Power Mode)

DAC Offset with Attenuator Enabled (High Power Mode)

DAC Offset with Attenuator Disabled (High Power Mode)

Waveform Generator Configuration Register ..................... 115

Waveform Generator for Sinusoid Frequency Control Word

Waveform Generator for Sinusoid Phase Offset Register.. 116

Waveform Generator for Sinusoid Offset Register............. 116

Waveform Generator for Sinusoid Amplitude Register..... 116

Programmable Switches Connecting the External Sensor to the

High Speed DAC and High Speed TIA..................................... 117

Dx Switches............................................................................... 117

Px Switches................................................................................ 117

Nx Switches............................................................................... 117

Tx Switches ............................................................................... 117

Options for Controlling All Switches.................................... 117

Switch Matrix Configuration Register .................................. 121

Dx Switch Matrix Full Configuration Register.................... 122

Nx Switch Matrix Full Configuration Register.................... 123

Px Switch Matrix Full Configuration Register..................... 124

Tx Switch Matrix Full Configuration Register .................... 125

Dx Switch Matrix Status Register .......................................... 126

Px Switch Matrix Status Register ........................................... 126

Nx Switch Matrix Status Register .......................................... 127

Tx Switch Matrix Status Register........................................... 128

Sequencer....................................................................................... 130

Sequencer Features .................................................................. 130

Sequencer Overview ................................................................ 130

Sequencer Commands............................................................. 130

Sequencer Operation ............................................................... 131

Sequencer and FIFO Registers ............................................... 134

AFE Interrupts.............................................................................. 139

Interrupt Controller Interupts ............................................... 139

Configuring the Interrupts ..................................................... 139

Custom Interrupts ................................................................... 139

Interrupt Registers ................................................................... 140

Sleep and Wake-Up Timer ......................................................... 145

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Sleep and Wake-Up Timer Features ..................................... 145

Sleep and Wake-Up Timer Overview ................................... 145

Configuring a Defined Sequence Order ............................... 145

Recommended Sleep and Wake-Up Timer Operation ...... 146

Sleep and Wake-Up Timer Registers .................................... 146

Use Case Configurations............................................................. 150

Hibernate Mode While Maintaining a DC Bias to the Sensor

.................................................................................................... 150

Measuring a DC Current Output .......................................... 152

Pulse Test (Chronoamperometry)......................................... 153

Cyclic Voltammetry................................................................. 154

AC Impedance Measurement While Maintaining DC Bias to

the Sensor .................................................................................. 157

DMA Controller........................................................................... 163

DMA Features .......................................................................... 163

DMA Overview ........................................................................ 163

DMA Analog Die ..................................................................... 163

DMA Architectural Concepts ................................................ 164

DMA Operating Modes .......................................................... 164

Channel Control Data Structure............................................ 164

Source Data End Pointer......................................................... 165

Destination Data End Pointer................................................ 165

Control Data Configuration................................................... 166

DMA Priority ........................................................................... 167

DMA Transfer Types............................................................... 167

DMA Interrupts and Exceptions ........................................... 173

Endian Operation .................................................................... 174

DMA Channel Enable and Disable ....................................... 174

DMA Master Enable................................................................ 175

Power-Down Considerations................................................. 175

Status Register .......................................................................... 177

Configuration Register............................................................ 177

Channel Primary Control Data Base Pointer Register ....... 177

Channel Alternate Control Data Base Pointer Register ..... 177

Channel Software Request Register....................................... 178

Channel Request Mask Set Register ...................................... 178

Channel Request Mask Clear Register .................................. 178

Channel Enable Set Register................................................... 179

Channel Enable Clear Register............................................... 179

Channel Primary Alternate Set Register............................... 179

Channel Primary Alternate Clear Register ...........................180

Channel Priority Set Register..................................................180

Channel Priority Clear Register..............................................180

Bus Error Clear Register ..........................................................181

Per Channel Bus Error Register..............................................181

Per Channel Invalid Descriptor Clear Register ....................181

Channel Bytes Swap Enable Set Register...............................182

Channel Bytes Swap Enable Clear Register...........................182

Channel Source Address Decrement Enable Set Register ..182

Channel Source Address Decrement Enable Clear Register

.....................................................................................................183

Channel Destination Address Decrement Enable Set Register

.....................................................................................................183

Channel Destination Address Decrement Enable Clear

FIFO Configuration Register ..................................................184

Data FIFO Read Register .........................................................184

Flash Controller ............................................................................185

Flash Controller Features ........................................................185

Flash Controller Overview ......................................................185

Supported Commands .............................................................185

Protection and Integrity Features...........................................185

Flash Controller Operation .....................................................185

Flash Memory Structure ..........................................................186

Flash Access...............................................................................188

Reading Flash ............................................................................188

Erasing Flash..............................................................................188

Writing Flash.............................................................................188

Keyhole Writes..........................................................................189

Burst Writes...............................................................................189

DMA Writes ..............................................................................190

Protection and Integrity...........................................................190

Key Register ...............................................................................192

Clock and Timings ...................................................................193

Flash Operating Modes............................................................194

Status Register ...........................................................................196

Interrupt Enable Register ........................................................198

Command Register...................................................................199

Write Address Register ............................................................200

Write Lower Data Register ......................................................200

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Write Upper Data Register ..................................................... 200

Lower Page Address Register.................................................. 200

Upper Page Address Register ................................................. 201

Key Register............................................................................... 201

Write Abort Address Register ................................................ 201

Write Protection Register........................................................ 201

Signature Register..................................................................... 202

User Configuration Register................................................... 202

IRQ Abort Enable (Lower Bits) Register .............................. 203

IRQ Abort Enable (Upper Bits) Register .............................. 203

ECC Configuration Register................................................... 203

ECC Status (Address) Register............................................... 203

Analog Devices Flash Security Register ................................ 204

SRAM ............................................................................................. 205

SRAM Features ......................................................................... 205

Instruction vs. Data SRAM ..................................................... 206

SRAM Retention in Hibernate Mode.................................... 206

SRAM Initialization ................................................................. 206

Cache.............................................................................................. 208

Initialization in Cache and Instruction SRAM .................... 208

Programming Guidelines........................................................ 208

Cache Status Register............................................................... 210

Cache Setup Register................................................................ 210

Cache Key Register................................................................... 210

Silicon Identification.................................................................... 211

Analog Devices Identification (Digital Die) Register.......... 213

Chip Identifier (Digital Die) Register.................................... 213

Serial Wire Debug Enable Register........................................ 213

Analog Devices Identification (Analog Die) Register......... 213

Chip Identification (Analog Die) Register ........................... 213

16-Bit Scratch Register to Test Interdie Communications

Digital Inputs and Outputs ......................................................... 214

Digital Inputs and Outputs Features ..................................... 214

Digital Inputs and Outputs Overview ................................... 214

Digital Inputs and Outputs Operation.................................. 215

Interrupts................................................................................... 215

Digital Die Port Mux ............................................................... 217

AFE Die Digital Port Mux ...................................................... 217

GPIO Port Configuration Registers ...................................... 220

GPIO Port Output Enable Registers...................................... 220

GPIO Port Input/Output Pull-Up Enable Registers ........... 220

GPIO Port Input Path Enable Registers ............................... 221

GPIO Port Registered Data Input Registers......................... 221

GPIO Port Data Output Registers ......................................... 221

GPIO Port Data Output Set Registers................................... 221

GPIO Port Data Output Clear Registers............................... 222

GPIO Port Pin Toggle Registers ............................................ 222

GPIO Port Interrupt Polarity Registers ................................ 222

GPIO Port Interrupt A Enable Registers .............................. 222

GPIO Port Interrupt B Enable Registers .............................. 223

GPIO Port Interrupt Status Registers ................................... 223

GPIO Port Drive Strength Select Registers .......................... 223

AFE GPIO Port Configuration Register ............................... 223

AFE GPIO Port Output Enable Register .............................. 224

AFE GPIO Port Output Pull-Up and Pull-Down Enable

AFE GPIO Port Input Path Enable Register ........................ 224

AFE GPIO Port Registered Data Input................................. 224

AFE GPIO Port Data Output Register.................................. 224

AFE GPIO Port Data Output Set Register............................ 225

AFE GPIO Port Data Output Clear Register ....................... 225

AFE GPIO Port Pin Toggle Register ..................................... 225

I2C Serial Interface........................................................................ 226

I2C Features............................................................................... 226

I2C Overview............................................................................. 226

I2C Operation............................................................................ 226

I2C Operating Modes............................................................... 228

Master Control Register .......................................................... 232

Master Status Register ............................................................. 232

Master Receive Data Register ................................................. 233

Master Transmit Data Register .............................................. 234

Master Receive Data Count Register..................................... 234

Master Current Receive Data Count Register...................... 234

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First Master Address Byte Register ....................................... 234

Second Master Address Byte Register................................... 234

Serial Clock Period Divisor Register ..................................... 235

Slave Control Register ............................................................. 235

Slave I2C Status, Error, and IRQ Register............................. 236

Slave Receive Register.............................................................. 237

Slave Transmit Register........................................................... 237

Hardware General Call ID Register....................................... 237

First Slave Address Device ID Register................................. 237

Second Slave Address Device ID Register ............................ 238

Third Slave Address Device ID Register............................... 238

Fourth Slave Address Device ID Register............................. 238

Master and Slave FIFO Status Register ................................. 238

Master and Slave Shared Control Register........................... 239

Automatic Stretch Control for Master and Slave Mode

Serial Peripheral Interfaces ......................................................... 241

SPI Features .............................................................................. 241

SPI Overview ............................................................................ 241

SPI Operation ........................................................................... 241

SPI Transfer Initiation ............................................................ 242

SPI Interrupts ........................................................................... 244

SPI Wire-OR’ed Mode ............................................................ 245

SPI CSERR Condition ............................................................. 245

SPI DMA ................................................................................... 245

SPI and Power-Down Modes ................................................. 246

Status Registers......................................................................... 248

Receive Registers...................................................................... 249

Transmit Registers ................................................................... 249

Baud Rate Selection Registers ................................................ 249

Configuration Registers .......................................................... 250

Interrupt Configuration Registers......................................... 251

Transfer Byte Count Registers ............................................... 252

DMA Enable Registers ............................................................ 252

FIFO Status Registers .............................................................. 253

Read Control Registers............................................................ 254

Flow Control Registers............................................................ 255

Wait Timer for Flow Control Registers................................ 255

Chip Select Override Registers............................................... 255

UART Serial Interface ..................................................................256

UART Overview........................................................................256

UART Features..........................................................................256

UART Operation ......................................................................256

Transmit Holding Register......................................................260

Receive Buffer Register ............................................................260

Interrupt Enable Register ........................................................260

Interrupt Identification Register ............................................261

Line Control Register ...............................................................261

Modem Control Register .........................................................262

Line Status Register ..................................................................262

Modem Status Register ............................................................263

Scratch Buffer Register.............................................................263

FIFO Control Register..............................................................263

Fractional Baud Rate Register.................................................264

Baud Rate Divider Register .....................................................264

Second Line Control Register .................................................264

UART Control Register ...........................................................265

Receive FIFO Count Register..................................................265

Transmit FIFO Count Register...............................................265

RS485 Half-Duplex Control Register.....................................265

Autobaud Control Register .....................................................266

Autobaud Status (Low) Register.............................................266

Autobaud Status (High) Register ...........................................266

Digital Die General-Purpose Timers .........................................267

Digital Die General-Purpose Timers Features .....................267

General-Purpose Timers Overview........................................267

General-Purpose Timer Operations ......................................267

16-Bit Synchronous Load Value Registers............................271

16-Bit Timer Synchronous Value Registers..........................271

Control Registers ......................................................................271

Clear Interrupt Registers .........................................................272

Capture Registers......................................................................272

16-Bit Asynchronous Load Value Registers .........................273

16-Bit Timer Asynchronous Value Registers .......................273

Status Registers..........................................................................273

Analog Die General-Purpose Timers.........................................274

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Analog Die General-Purpose Timers Features .................... 274

AFE PWM ................................................................................. 274

16-Bit Load Value Register .....................................................276

16-Bit Timer Value Register ................................................... 276

Control Register ....................................................................... 276

Clear Interrupt Register........................................................... 277

16-Bit Load Value, Asynchronous Register.......................... 277

16-Bit Timer Value, Asynchronous Register ....................... 277

Status Register........................................................................... 278

PWM Control Register............................................................ 278

PWM Match Value Register ................................................... 278

Interrupt Enable Register ........................................................ 279

16-Bit Load Value Register .....................................................279

16-Bit Timer Value Register ................................................... 279

Control Register ....................................................................... 279

Clear Interrupt Register........................................................... 280

16-Bit Load Value, Asynchronous Register.......................... 280

16-Bit Timer Value, Asynchronous Register ....................... 281

Status Register........................................................................... 281

PWM Control Register............................................................ 281

PWM Match Value Register ................................................... 281

AFE Watchdog Timer.................................................................. 282

Watchdog Timer Features and Block Diagram ................... 282

Watchdog Timer Operation ................................................... 282

Windowed Watchdog Feature ............................................... 282

Interrupt Mode......................................................................... 282

Watchdog Timer Load Value Register.................................. 284

Current Count Value Register................................................ 284

Watchdog Timer Control Register ........................................ 284

Refresh Watchdog Register..................................................... 285

Timer Status Register............................................................... 285

Minimum Load Value Register .............................................. 286

Digital Die Wake-Up Timer ....................................................... 287

Overview.................................................................................... 287

Features...................................................................................... 287

Regular and Periodic Modulo 60 Interrupts ........................ 287

Timer Matching Alarm Value Interrupts ............................. 287

WUT Functional Description ................................................ 287

WUT Operating Modes .......................................................... 288

WUT Recommendations: Clock and Power........................ 288

Control 0 Register .................................................................... 291

Status 0 Register ....................................................................... 292

Status 1 Register ....................................................................... 294

Count 0 Register....................................................................... 295

Count 1 Register....................................................................... 295

Alarm 0 Register....................................................................... 296

Alarm 1 Register....................................................................... 296

Gateway Register ...................................................................... 296

Control 1 Register .................................................................... 297

Status 2 Register ....................................................................... 298

Snapshot 0 Register.................................................................. 299

Snapshot 1 Register.................................................................. 300

Snapshot 2 Register.................................................................. 300

Modulo Register ....................................................................... 300

Count 2 Register....................................................................... 301

Alarm 2 Register....................................................................... 301

Status 6 Register ....................................................................... 302

Cyclic Redundancy Check .......................................................... 303

CRC Features ............................................................................ 303

CRC Functional Description.................................................. 303

CRC Data Transfer .................................................................. 306

CRC Interrupts and Exceptions............................................. 306

CRC Programming Model...................................................... 306

CRC Control Register.............................................................. 309

Input Data Word Register ...................................................... 309

CRC Result Register................................................................. 309

Programmable CRC Polynomial Register ............................ 309

Input Data Bits Register .......................................................... 310

Input Data Byte Register ......................................................... 310

Hardware Design Considerations.............................................. 311

Typical System Configuration................................................ 311

Serial Wire Debug Interface ................................................... 312

ADuCM355 Hardware Reference Manual UG-1262

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REVISION HISTORY

2/2020—Rev. A to Rev. B

Changed PLCC_CACHE to PLCC............................. Throughout

Changes to Table 9..........................................................................20

Changes to Power Management Unit Features Section ............25

Deleted Shutdown Mode Section .................................................25

Deleted Shutdown Mode, Mode 3 Section ..................................26

Changes to Wake-Up Sequence Section......................................28

Changes to Table 21........................................................................29

Changes to Table 24........................................................................30

Changes to Table 25........................................................................31

Deleted Shutdown Status Register Section and Table 27;

Renumbered Sequentially ..............................................................32

Changes to Table 29........................................................................33

Changed Clear GPIO Latch After Shutdown Register Section to

Power Modes Register Section ......................................................34

Changes to Table 31........................................................................34

Deleted Scratch Pad Image Register Section and Table 33 .......34

Deleted Scratch Pad Saved in Battery Domain Register Section

and Table 34.....................................................................................35

Changes to ARM Cortex-M3 Processor Features Section ........35

Changes to ARM Cortex-M3 Processor Related

Documents Section .........................................................................36

Changes to Cortex-M3 and Fault Management Section

and Table 41.....................................................................................42

Changes to Table 42........................................................................45

Changes to Table 46........................................................................49

Changes to Table 47 and Table 48................................................50

Changes to Analog Die Circuitry Summary Section .................52

Changes to ADC Circuit Overview Section ................................57

Changes to ADC Circuit Features Section ..................................58

Changes to Figure 9 ........................................................................59

Changes to Sinc3 Filter Section and Sinc2 Filter Section..........60

Changes to Statistics Option Section............................................61

Changes to Temperature Sensor 0 Section..................................62

Changes to Temperature Sensor 1 Section..................................63

Changes to ADC Initialization Section........................................64

Changes to Figure 14 ......................................................................66

Changes to Table 59 and Table 61................................................67

Changes to Table 64........................................................................70

Changes to Table 70........................................................................72

Changes to Table 71........................................................................73

Changes to Table 73........................................................................75

Changes to Table 76........................................................................76

Deleted Offset Cancellation (Optional Calibration) Register

Section and Table 100.....................................................................82

Deleted Gain Cancellation with DC Cancellation (PGA Gain = 4),

Optional Calibration Register Section, Table 101.............................83

Deleted Variance Output Register Section and Table 107 ..........84

Changes to Statistics Module Configuration Register Section

and Table 101...................................................................................83

Changes to Low Power DACs Section .........................................88

Changes to Figure 19 ......................................................................89

Changes to Electrochemical Amperometric

Measurement Section.....................................................................90

Change to Electrochemical Impedance

Spectroscopy Section......................................................................91

Changes to Table 109 .....................................................................93

Changes to Table 111 .....................................................................96

Changes to Table 114 .....................................................................98

Changes to Table 115 .....................................................................99

Changes to Table 117 ...................................................................100

Changes to Key Features Section and Table 120 ......................102

Changes to Using DE0 and DE1 Inputs with the High Speed

TIA Section and External RTIA Selection Section......................104

Changes to Table 123 ...................................................................106

Changes to Table 124 ...................................................................107

Changes to Dx Switch Matrix Status Register Section and

Px Switch Matrix Status Register Section..................................126

Changes to Nx Switch Matrix Status Register Section ............127

Changes to Tx Switch Matrix Status Register Section.............128

Added Sequencer Section, Sequencer Features Section,

Sequencer Overview Section, Sequencer Commands Section,

and Write Command Section .....................................................130

Added Timer Command Section, Figure 28, Figure 29,

Figure 30, and Sequencer Operation Section;

Renumbered Sequentially ............................................................131

Added Figure 31, Command Memory Section, Loading

Sequences Section, and Data FIFO Section...............................132

Added Data FIFO Word Format Section, Sequencer and the Sleep

and Wake-Up Timer Section, Sequencer Conflicts Section,

Table 153, Figure 32, and Figure 33 ...........................................133

Added Sequencer and FIFO Registers Section, Table 154,

Sequencer Configuration Register Section,

and Table 155 ................................................................................134

Added FIFO Configuration Register Section, Table 156, Sequencer

CRC Value Register Section, Table 157, Sequencer Command

Count Register Section, Table 158, Sequencer Timeout Counter

Added Data FIFO Read Register Section, Table 160, Command

FIFO Write Register Section, Table 161, Sequencer Sleep Control

Lock Register Section, Table 162, Sequencer Trigger Sleep Register

Section, Table 163, Sequence 0 Information Register Section,

and Table 164..................................................................................136

Added Sequence 2 Information Register Section, Table 165,

Command FIFO Write Address Register Section, Table 166,

Command Data Control Register Section, Table 167, Data

FIFO Threshold Register Section, and Table 168.....................137

Added Sequence 3 Information Register Section, and Table 169,

Sequence 1 Information Register Section, Table 170, Command

and Data FIFO Internal Data Count Register Section, Table 171,

Trigger Sequence Register Section, and Table 172...................138

Added AFE Interrupts Section, Interrupt Controller Interrupts

Section, Configuring the Interrupts Section, Custom Interrupts

Section, and Table 173..................................................................139

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 10 of 312

Added Interrupt Registers Section, Table 174, Interrupt Polarity

and Table 176 ................................................................................ 140

Added Interrupt Controller Select Registers Section

and Table 177 ................................................................................ 141

Added Interrupt Controller Flag Registers Section

and Table 178 ................................................................................ 142

Added Analog Generation Interrupt Register Section

and Table 179 ................................................................................ 144

Added Sleep and Wake-Up Timer Section, Sleep and Wake-Up

Timer Features Section, Figure 34, Sleep and Wake-Up Timer

Overview Section, Figure 35, Configuring a Defined Sequence

Order Section, and Figure 36...................................................... 145

Added Recommended Sleep and Wake-Up Timer Operation

Section, Sleep and Wake-Up Timer Registers Section,

and Table 180 ................................................................................ 146

Added Timer Control Register Section, Table 181, Order Control

Added Sequence 0 to Sequence 3 Wake-Up Time Registers (LSB)

Section, Table 183, Sequence 0 to Sequence 3 Wake-Up Time

Registers (MSB) Section, and Table 184 ................................... 148

Added Sequence 0 to Sequence 3 Sleep Time Registers (LSB)

Section, Table 185, Sequence 0 to Sequence 3 Sleep Time Registers

(MSB) Section, Table 186, Timer Wake-Up Configuration

Changes to Implementing Pulse Test Using High Speed TIA

Section and Cyclic Voltammetry Section ................................. 154

Change to Step 4: Measure RCAL via the Impedance

Measurement Engine Section ..................................................... 161

Changes to Step 5: Calculate the Impedance of Electrochemical

Sensor Sensing Electrode Node Section .................................... 162

Changes to DMA Analog Die Section and AFE Die Data

FIFO Section ................................................................................. 163

Changes to Program Flow Section............................................. 164

Change to Address Decrement Section..................................... 173

Changes to Table 219................................................................... 184

Changes to Instruction vs. Data SRAM Section ...................... 206

Changes to Programming Guidelines Section ......................... 208

Changes to Table 255................................................................... 217

Changes to Figure 58 ................................................................... 227

Changes to Automatic Clock Stretching Section..................... 229

Change to Performing SPI DMA Master Receive Section ..... 246

Change to General-Purpose Timers Overview Section .......... 267

Changes to Table 345................................................................... 271

Change to Table 350 .................................................................... 273

Added AFE PWM Section .......................................................... 274

Change to Table 365 .................................................................... 279

Change to DMA Access Steps Section ...................................... 306

Changes to Table 403................................................................... 307

8/2019—Rev. 0 to Rev. A

Changes to Analog Die Clock Features Section......................... 13

Change to Figure 2 ......................................................................... 14

Changes to Connecting AFE Die Clock to Digital Die Clock

Input Section................................................................................... 15

Changes to Table 11....................................................................... 20

Changes to ADC Transfer Function Section and ADC Low

Power Current Input Channels Section...................................... 59

Changes to Table 57....................................................................... 61

Changes to Temperature Sensor 0 Section................................. 62

Changes to Figure 12 ..................................................................... 63

Changes to ADC Initialization Section ....................................... 64

Changes to Table 68....................................................................... 70

Changes to Table 79 and Table 80 ............................................... 76

Added Figure 18; Renumbered Sequentially.............................. 88

Changes to Figure 22 ................................................................... 105

Changes to Table 228................................................................... 201

Deleted Register 0x40004030 and Register 0x40024030,

Table 277 ....................................................................................... 231

Deleted Chip Select Control for Multislave Connections Registers

Section and Table 290; Renumbered Sequentially .................. 240

Changes to Table 317................................................................... 255

3/2019—Revision 0: Initial Version

ADuCM355 Hardware Reference Manual UG-1262

Rev. B | Page 11 of 312

USING THE ADuCM355 REFERENCE MANUAL

Table 1. Number Notations

Notation Description

Bit N Bits are numbered in little endian format, where the least significant bit of a number is referred to as Bit 0.

V[x:y] A range from Bit x to Bit y of a value or a field (V) is represented in bit field format, V[x:y].

0xNN Hexadecimal (Base 16) numbers are preceded by the 0x prefix.

0bNN Binary (Base 2) numbers are preceded by the 0b prefix.

Table 2. Register Access Conventions

Mode Description

R/W Memory location has read and write access.

RC Memory location is cleared after reading the location.

R Memory location is read access only. A read always returns 0, unless otherwise specified.

W Memory location is write access only.

R/W1C Memory location has read access. To clear to 0, write 1 once to the memory location.

Memory mapped register (MMR) bits that are not documented are reserved. When writing to MMRs with reserved bits, the reserved bits

must be written with the value in the reset column of the relevant MMR description, unless otherwise specified.

Note that, throughout this user guide, multifunction pins, such as P0.0/SPI0_CLK, are referred to either by the entire pin name or by a

single function of the pin, for example, P0.0, when only that function is relevant.

In header files, registers are grouped in stacks, such as CLKG0_CLK and AFECON. These stack names serve as pointers to each element

in the associated structure and are used to access specific registers. For example, to access the STAT0 register, the user must enter the

following:

pADI_CLKG0_CLK->STAT0

Not all registers have stacks, in which case the register name is not preceded by a stack name in this hardware reference manual.

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 12 of 312

INTRODUCTION TO THE ADuCM355

MAIN FEATURES OF THE ADuCM355

The analog-to-digital converter (ADC) includes the following features:

 16-bit multichannel successive approximation register (SAR) ADC.

 Up to 34 input channels, programmable via input mux.

 Low noise transimpedance amplifiers (TIAs) for accurate current measurements.

 Low noise programmable gain amplifier (PGA) for accurate measurement of small input voltage signals.

 Internal 1.82 V and 2.5 V voltage reference sources.

 Hardware accelerators, including digital discrete Fourier transform (DFT) calculations.

The digital-to-analog converters (DACs) include the following features:

 Low power, low noise amplifiers designed for biasing external electrochemical sensors.

 Two dual output, low power DACs designed to set external sensor bias voltage and to support pulse and voltammetry

electrochemical techniques.

 Programmable switch configuration to support interfacing to a variety of sensors and external pins.

 High bandwidth DAC and excitation amplifier designed to generate an excitation signal for impedance measurements up to 200 kHz.

The ADuCM355 contains the following communication features:

 Industry-standard, 16450/16550 universal asynchronous receiver/transmitter (UART) peripheral and support for direct memory

access (DMA). Also supports wakeup from hibernate mode via the UART receive input.

 I2C, 2-byte transmit and receive first in, first out (FIFOs) for the master and slave, and support for DMA.

 Two serial peripheral interfaces (SPIs) with master or slave mode, separate 4-byte receive and transmit FIFOs, and receive and

transmit DMA channels.

 Multiple general-purpose input/output (GPIO) pins.

The processor of the ADuCM355 operates using the following:

 Arm® Cortex™-M3 processor, operating from an internal 26 MHz system clock.

 128 kB Flash/EE memory, 64 kB static random-access memory (SRAM) on digital die.

 In circuit programming and debug via serial wire.

The on-chip peripherals are as follows:

 Three general-purpose timers on the digital die. There are two general-purpose timers on the analog die.

 Wake-up timer on the digital die. There is an optional wake-up timer also on the analog die.

 Independent watchdog timer on the analog die.

The package is 6 mm × 5 mm, 72-lead land grid array (LGA) package, and the temperature range is −40°C to +85°C. A low cost

development system and a third party compiler and emulator tool support are included in the ADuCM355 evaluation kit.

Applications of the ADuCM355 include the following:

 Gas detection.

 Food quality.

 Environmental sensing (air, water, and soil).

 Blood glucose meters.

 Life sciences and biosensing analysis.

 Bioimpedance measurements.

 General amperometry, voltammetry, and impedance.

The memory organization of the device operates using the following:

 Arm Cortex-M3 memory system features include a predefined memory map, support for bit band operation for atomic operations,

and unaligned data access.

 On-chip peripherals are accessed via memory-mapped registers, situated in the bit band region.

 User memory size options are 128 kB Flash/EE memory and 64 kB SRAM.

 On-chip kernel for booting device with manufacturer data.

ADuCM355 Hardware Reference Manual UG-1262

Rev. B | Page 13 of 312

AFE DIE REGISTERS

0x400C_23FF

0x400C_0800

0x4004_4FFF

0x4000_0000

0x2000_7FFF

0x2000_0000

0x1000_7FFF

0x1000_0000

0x0001_FFFF

0x0000_0000

DIGITAL DIE REGISTERS

(MAPPABLE)

SRAM

(MAPPABLE)

SRAM

FLASH MEMORY

UNUSED ADDRESS SPACE

16675-002

Figure 1. Arm Cortex-M3 Memory Map Diagram

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 14 of 312

CLOCKING ARCHITECTURE

CLOCKING ARCHITECTURE OPERATION

The ADuCM355 contains two internal die. Therefore, there are two independent clock systems: a digital die clock system and an analog

die clock system. Figure 2 shows the overall clock architecture.

REQUIRED CLOCK RATIO BETWEEN DIGITAL DIE AND ANALOG DIE SYSTEM CLOCKS

To maintain reliable communications between the digital die and the analog die, the ratio of the digital die system clock frequency to the analog

die system clock frequency must be within the range of 3:1 and 1:3. For example, if the digital die system clock is set to 6.5 MHz, the analog die

system clock must be >2.2 MHz but <19 MHz. If this ratio is not maintained, the digital die can lose its communication link to the analog die.

DIGITAL DIE CLOCK FEATURES

At power-up, the processor executes from the internal 26 MHz oscillator, with the oscillator output divided by four to give a clock to the

central processing unit (CPU) of 6.5 MHz. User code can select the clock source for the digital die system clock and can divide the clock

by a factor of 1 to 32, where the clock divider bits are controlled by Bits[5:0] in the CTL1 register, which allows slower code execution

and reduced power consumption.

When switching clock sources, a stable clock must always be connected to the core. Otherwise, the system can halt before connecting to

the new clock. The digital die clocks include the following:

 The low frequency oscillator is a 32 kHz internal oscillator.

 The high frequency oscillator is a 26 MHz internal oscillator.

 External, 16 MHz and 32 MHz crystal options, routed through the analog die.

 External clock input option, routed through the analog die.

 The root clock is divided into several internal clocks.

 The reference clock (RCLK) clocks the reference timer in the flash controller. The RCLK controls the time for flash erase and write

operations. By default, RCLK is always connected to a 13 MHz clock source. The clock source is generated by a ½ divider connected

to the 26 MHz high frequency oscillator. Therefore, the default values of the flash timer registers correspond to a 13 MHz clock.

 The high power buck regulator clocks the high power buck module. When the high power buck regulator is enabled, this clock

source is always 200 kHz. The high power buck regulator is enabled and disabled by the CTL1 register in the power management

unit (PMU).

ANALOG DIE CLOCK FEATURES

At power-up, the internal high frequency oscillator is selected as the analog front end (AFE) system clock with a 16 MHz setting. User

code can divide the clock by a factor of 1 to 32, where the clock divider bits are controlled by CLKCON0, Bits[5:0], which allows reduced

power consumption.

The system performance of the analog die has only been validated with the system clock = 16 MHz. The analog die clocks include the

following:

 AFE low frequency oscillator is a 32 kHz internal oscillator used for the analog die watchdog timer.

 AFE high frequency oscillator is a 16 MHz or 32 MHz internal oscillator. The 32 MHz setting is only intended for clocking the ADC

when measuring signals >80 kHz, especially for high frequency impedance measurements. If the 32 MHz setting is used, ensure that

CLKCON0 Bits[5:0] = 2 to limit the digital die clock sources to 16 MHz. To select the 32 MHz oscillator option, use the following

sequence:

pADI_AFECON->CLKEN1 |= BITM_AFECON_CLKEN1_ACLKDIS; // Temporarily disable ACLK

pADI_AFE->HPOSCCON &= (~0x4); // Clear HPOSCCON[2] = 0 to select 32 MHz output

pADI_AFECON->CLKEN1 &= (~BITM_AFECON_CLKEN1_ACLKDIS); // Re-enable ACLK

The high power oscillator configuration register is key protected, and the temporary disabling of the analog clock (ACLK) ensures a

safe switchover of the high frequency oscillator from 16 MHz to 32 MHz or from 32 MHz to 16 MHz.

 External 16 MHz and 32 MHz crystal option. If the 32 MHz crystal is used, ensure that CLKCON0, Bits[5:0] = 2 to limit the digital

die clock sources to 16 MHz.

 External clock input option. If the 32 MHz crystal is used, ensure that CLKCON0, Bits[5:0] = 2 to limit the digital die clock sources

to 16 MHz.

 When using the 32 MHz oscillator on the analog die, the PMBW register in AFECON must be configured for high power mode.

 Note, the ADC clock cannot be divided. It runs at the same speed as the high frequency oscillator selected in CLKSEL, Bits[3:2].

ADuCM355 Hardware Reference Manual UG-1262

Rev. B | Page 15 of 312

HIGH

FREQUENCY

INTERNAL

OSCILLATOR

16MHz/32MHz

HIGH

FREQUENCY

INTERNAL

OSCILLATOR

26MHz

EXT CLK

LOW

FREQUENCY

INTERNAL

OSCILLATOR

32kHz

PCLK DIV

CLK CTL1

[13:8]

HCLK DIV

CLK CTL1

[5:0]

200kHz HPBUCK

DIV2

FLASH

RTC1

BEEPER

WDT

ROOT_CLK

CLK CTL0[1:0]

C UCLK

CTL5[5]

CTL5[4]

CTL5[3]

CTL5[0/1/2]

HIGH FREQUENCY OSCILLATOR CLK

LFXTAL

GPTx_CTL[6:5]

AFE HIGH

FREQUENCY

OSCILLATOR

16kHz/32MHz

AFE LOW

FREQUENCY

INTERNAL

OSC 32kHz

DIE TO DIE

SPI

TESTREG

SYSCLK DIV

CLKCON[5:0]

OTP PCLK

AFE

GENERAL-PURPOSE

TIMERS

AFE_SYSCLK

ADC

CLK IN

CLKSEL[1:0]

CLKSEL[3:2]

LOW

FREQUENCY

OSCILLATOR

HIGH

FREQUENCY

OSCILLATOR

CLK

AFE WDT

AFE WAKE-UP

TIMER

TIA CHOP

CLKEN0[0]

CLKEN0[1]

CLKEN0[2]

LOW FREQUENCY OSCILLATOR

HIGH FREQUENCY OSCILLATOR CLK

LOW FREQUENCY OSCILLATOR

EXT CLK

AFE_PCLK

MISC

INTC

AFEM

CLKEN1[0]

CLKEN1[1]

CLKEN1[2]

CLKEN1[3]

AGPT_CON[6:5]

AFE_PCLK

DFT/WG

AFE_ACLK

CLKEN1[9]

MISC_CLKEN1[6/7]

AFE DIE

0001 1011

13MHz

PCLK SELF GATED

PERIPHERALS

DIGITAL DIE

HPBUCK CLK

RCLK

RESERVED

CLKEN1[5]

16675-003

GENERAL-PURPOSE

TIMERS

Figure 2. Clock Architecture Block Diagram

CLOCK GATING

In the case of certain clocks, clocks can be individually gated depending on the power mode or register settings. For more information

about clock gating and power modes, refer to the Power Management Unit section.

On the digital die, the clock gates of the peripheral clocks are user-controllable in certain power modes. Register CTL5 in CLKG0_CLK

can be programmed to turn off certain clocks, depending on the user application. Set the appropriate bits in the CTL5 register to 1 to

disable the clock to individual blocks.

On the analog die, use the CLKEN0 register and the CLKEN1 register to disable the system clock to different peripherals on the analog die.

CONNECTING AFE DIE CLOCK TO DIGITAL DIE CLOCK INPUT

The AFE die 16 MHz oscillator is a more accurate oscillator than the 26 MHz high frequency oscillator on the digital die. For UART

communications, select the AFE die 16 MHz oscillator as the input clock to the digital die. Internally, the AFE system clock can be

connected to an internal pad, P2.2, on the AFE. There is an internal bond wire connecting this AFE die pad to the digital die pad, P1.10,

on the digital die that can be configured as the external clock input for the digital die.

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 16 of 312

To connect and select the AFE die 16 MHz oscillator as the external clock input for the digital die, perform the following steps:

1. Enable AFE die Pad P2.2 as an output.

pADI_AGPIO2->OEN |= 0x4;

2. Configure the internal digital die Pad P1.10 as an input and configure its mode as EXT_CLKIN.

DioCfgPin(pADI_GPIO1,PIN10,2); // External Clock mode for Digital die P1.10

DioIenPin(pADI_GPIO1,PIN10,1); // Enable p1.10 input path

3. Clear CLKEN1, Bits[9:8]. The user is required to close the switch on the AFE die to connect the AFE die clock to the P2.2 pad.

pADI_AFECON->CLKEN1 &= 0x0FF; // Clear CLKEN1 bits 9:8

4. Select the digital die clock source as the external clock from the AFE die.

DigClkSel(DIGCLK_SOURCE_AFE);

If the clock source is a 32 MHz external crystal, ensure the clock to the digital die is 16 MHz by setting CLKCON[9:6] = 2.

Hibernate Mode and AFE Die Clock Selected on Digital Die

Switch the digital die clock source back to a digital die clock before entering hibernate mode. The device does not wake up if both die are

in hibernate mode and the AFE die clock is used by both die, because, on waking from hibernate mode, the digital die wakes first. The

digital die then must read or write to an AFE die register to wake the AFE die. If the AFE die is the clock source to both die, the wake-up

sequence does not complete.

To enter hibernate mode, use the following suggested sequence:

DigClkSel(DIGCLK_SOURCE_HFOSC); // Switch digital die clock back to its own oscillator

pADI_UART0->COMDIV = 0; // Clear COMDIV to ensure UART operates after wake-up

EnterHibernateMode(); // Enter Hibernate mode

To exit hibernate mode to switch back to using only the AFE clock, use the following suggested sequence:

uiDummyRead = pADI_AFE->LPDACCON0; // Dummy read to wake-up AFE die

delay_10us(2000); // Wait 20mS

DigClkSel(DIGCLK_SOURCE_AFE);

UrtCfg(pADI_UART0,B57600, // Re-Initialize the UART

(BITM_UART_COMLCR_WLS|3),0); // Configure UART for 57600 baud rate

printf("Digital Die clocked by AFE die's 16MHz oscillator \r\n");

ADuCM355 Hardware Reference Manual UG-1262

Rev. B | Page 17 of 312

Table 3. Digital Die System Clock Register Summary (CLKG0_CLK Stack)

Address Name Description Reset Access

0x4004C10C KEY Key protection for CTL register 0x00000000 R/W

0x4004C110 CTL Oscillator control 0x00000302 R/W

0x4004C300 CTL0 Clock Control 0 0x00000078 R/W

0x4004C304 CTL1 Clock dividers 0x00100404 R/W

0x4004C314 CTL5 User clock gating control 0x0000001F R/W

0x4004C318 STAT0 Clocking status 0x00000000 R/W

Table 4. Analog Die Clock Register Summary (AFECON Stack)

Address Name Description Reset Access

0x400C0408 CLKCON0 Clock divider configuration 0x0441 R/W

0x400C0410 CLKEN1 Clock gate enable 0x010A R/W

0x400C0414 CLKSEL Clock select 0x0000 R/W

0x400C041C GPIOCLKMUXSEL GPIO clock mux select to GPIO1 pin 0x0000 R/W

0x400C0420 CLKCON0KEY Key protection for CLKCON0 0x0000 R/W

0x400C0A70 CLKEN0 Clock control of low power TIA chop, watchdog, and wake-up timers 0x0000 R/W

0x400C0A0C OSCKEY Key protection for OSCCON 0x0000 R/W

0x400C0A10 OSCCON Oscillator control 0x0303 R/W

0x400C20BC HPOSCCON High power oscillator configuration 0x00000024 R/W

0x400C22F0 PMBW Power mode configuration register 0x00000000 R/W

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 18 of 312

KEY PROTECTION FOR CTL REGISTER

Address: 0x4004C10C, Reset: 0x00000000, Name: KEY

Table 5. Bit Descriptions for KEY

Bits Bit Name Settings Description Reset Access

[31:16] Reserved Reserved. 0x0000 R

[15:0] VALUE 0xCB14

Oscillator Key. The CTL register is key protected. To unlock this protection, write

0xCB14 to KEY before writing to CTL. A write to any other register on the Arm

peripheral bus before writing to CTL returns the protection to the lock state.

0x0000 W

OSCILLATOR CONTROL REGISTER

Address: 0x4004C110, Reset: 0x00000302, Name: CTL

The CTL register is key protected. To unlock this protection, write 0xCB14 to KEY before writing to the CTL register. A write to any

other register on the Arm peripheral bus before writing to the CTL register returns the protection to the lock state.

Table 6. Bit Descriptions for CTL

Bits Bit Name Settings Description Reset Access

[31:10] Reserved Reserved. 0x0 R

9 HFOSCOK

Status of High Frequency Oscillator on Digital Die. This bit indicates when the

oscillator is stable after it is enabled. This bit is not a monitor and does not indicate a

subsequent loss of stability.

0x1 R

0 Oscillator is not yet stable or is disabled.

1 Oscillator is enabled, stable, and ready for use.

8 LFOSCOK

Status of Low Frequency Oscillator on Digital Die. This bit indicates when the

oscillator is stable after it is enabled. This bit is not a monitor and does not indicate a

subsequent loss of stability.

0x1 R

0 Oscillator is not yet stable or is disabled.

1 Oscillator is enabled, stable, and ready for use.

[7:2] Reserved Reserved. 0x0 R

1 HFOSCEN

High Frequency Internal Oscillator Enable. This bit is used to enable and disable the

high frequency oscillator on the digital die. The oscillator must be stable before use.

This bit must be set before the SYSRESETREQ system reset can be initiated.

SYSRESETREQ is a bit in the Arm Cortex-M3 AIRCR register.

0x1 R/W

0 The high frequency oscillator is disabled and placed in a low power state.

1 The high frequency oscillator is enabled.

0 Reserved Reserved. This bit must always be 0. 0x0 R/W

CLOCK CONTROL 0 REGISTER

Address: 0x4004C300, Reset: 0x00000078, Name: CTL0

The Clock Control 0 register is used to configure clock sources used by various systems, such as the core, memories, and peripherals. All

unused bits are read only and return a value of 0. Writing unused bits has no effect.

Table 7. Bit Descriptions for CTL0

Bits Bit Name Settings Description Reset Access

[31:2] Reserved Reserved. 0x0000000 R

[1:0] CLKMUX

Clock Mux Select. Determines which single shared clock source is used by the

gated system clock (peripheral clock (PCLK) on digital die) and high speed clock

(HCLK) dividers.

0x0 R/W

00 High frequency internal oscillator is selected.

01, 10 Reserved.

11 External clock routed from analog die. Can be external crystal or clock source.

ADuCM355 Hardware Reference Manual UG-1262

Rev. B | Page 19 of 312

CLOCK DIVIDERS REGISTER

Address: 0x4004C304, Reset: 0x00100404, Name: CTL1

The clock dividers register is used to set the divide rates for the HCLK, PCLK, and ACLK dividers. This register can be written to at any

time. All unused bits are read only, returning a value of 0. Writing to unused bits has no effect.

Table 8. Bit Descriptions for CTL1

Bits Bit Name Settings Description Reset Access

[31:24] Reserved Reserved. 0x0 R

[23:16] ACLKDIVCNT ACLK Clock Divider. This bit determines the ACLK rate based on the equation

ACLK = root clock/ACLKDIVCNT. For example, if the root clock is 26 MHz and

ACLKDIVCNT = 0x1, ACLK operates at 26 MHz. The value of ACLKDIVCNT takes

effect after a write access to this register and typically takes one ACLK cycle. This

range is from 1 to 32. Values larger than 32 are saturated to 32. Value 0 and

Value 1 have the same results as divide by 1. The default value of this register is

configured such that ACLK = 1.625 MHz.

0x10 R/W

[15:14] Reserved Reserved. 0x0 R

[13:8] PCLKDIVCNT PCLK Clock Divider. Determines the PCLK rate based on the equation PCLK = root

clock/PCLKDIVCNT. For example, if the root clock is 26 MHz and PCLKDIVCNT = 0x2,

PCLK operates at 13 MHz. The value of PCLKDIVCNT takes effect after a write access

to this register and typically takes 2 to 4 PCLK cycles. This register can be read at

any time and can be written to at any time. The value range is from 1 to 32.

Values larger than 32 are saturated to 32. Value 0 and Value 1 have the same

results as divide by 1. The default value of this register is configured such that

PCLK frequency = 6.5 MHz. It is recommended to only use the 0x1, 0x2, or 0x4

value and matching PCLKDIVCNT with HCLKDIVCNT.

0x4 R/W

[7:6] Reserved Reserved. 0x0 R

[5:0] HCLKDIVCNT HCLK Divide Count. Determines the HCLK rate based on the equation: HCLK = root

clock/HCLKDIVCNT. For example, if the root clock is 26 MHz and HCLKDIVCNT = 0x1,

HCLK operates at 26 MHz. The value of HCLKDIVCNT takes effect after a write

access to this register and typically takes 2 to 4 PCLK cycles (not HCLK cycles).

This register can be read at any time and can be written to at any time. The

value range is from 1 to 32. Values larger than 32 are saturated to 32. Value 0

and Value 1 have the same results as divide by 1. The default value of this

the values 0x1, 0x2, or 0x4 and match HCLKDIVCNT with PCLKDIVCNT.

0x4 R/W

USER CLOCK GATING CONTROL REGISTER

Address: 0x4004C314, Reset: 0x0000001F, Name: CTL5

User clock gating control is used to control the clock gating to peripherals.

Table 9. Bit Descriptions for CTL5

Bits Bit Name Settings Description Reset Access

[31:6] Reserved Reserved. 0x0 R

5 PERCLKOFF

Peripheral Clocks Off. This bit is used to disable all clocks connected to all

peripherals. After setting this bit, any read or write to any of the peripheral

registers automatically resets PERCLKOFF to 0, and that read or write transaction is

honored. After setting PERCLKOFF = 1, if the user reads the CTL5 register,

PERCLKOFF is automatically cleared and PERCLKOFF reads as 0. The user must

ensure that DMA transactions are done and no more transactions are expected

from the DMA. Ensure that the PERCLKOFF bit write is the last write and no writes

or reads to any of peripheral registers are performed after setting this bit.

Otherwise, the PERCLKOFF bit clears.

0x0 R/W

0 Clocks to all peripherals are active.

1 Clocks to all peripherals are gated off.

UG-1262 ADuCM355 Hardware Reference Manual

Rev. B | Page 20 of 312

Bits Bit Name Settings Description Reset Access

4 GPIOCLKOFF

GPIO Clock Control. This bit disables the GPIO clock and controls the gate on the

ACLK out from ACLK divider. This ACLK control is available in active mode and

Flexi™ mode. In hibernate mode, the ACLK is always off and this bit has no effect.

This bit does not automatically clear. Explicitly enable or disable this bit to control

ACLK out. Before programming the ACLKDIVCNT bits in the CTL1 register, clear

this bit to 0. Otherwise, the ACLKDIVCNT bit is not taken into effect.

0x1 R/W

0 GPIO clock is enabled.

1 GPIO clock is disabled.

3 UCLKI2COFF

I2C Clock User Control. This bit disables the I2C universal clock (UCLK) and controls

the gate on the I2C UCLK in active and flexi modes. In hibernate mode, the I2C

UCLK is always off and this bit has no effect. This bit is automatically cleared if the

user code accesses any of the I2C registers.

0x1 R/W

0 I2C clock is enabled.

1 I2C clock is disabled.

2 GPTCLK2OFF

General-Purpose Timer 2 User Control. This bit disables the General-Purpose Timer

2 clock (muxed version) and controls the gate in active and flexi modes. In

hibernate mode, the General-Purpose Timer 2 clock is always off and this bit has

no effect. This bit is automatically cleared if user code accesses any of the General-

Purpose Timer 2 registers.

0x1 R/W

0 Timer 2 clock is enabled.

1 Timer 2 clock is disabled.

1 GPTCLK1OFF

General-Purpose Timer 1 User Control. This bit disables the General-Purpose Timer

1 clock (muxed version) and controls the gate in active and flexi modes. In

hibernate mode, the General-Purpose Timer 1 clock is always off and this bit has

no effect. This bit is automatically cleared if user code accesses any of the General-

Purpose Timer 1 registers.

0x1 R/W

0 Timer 1 clock is enabled.

1 Timer 1 clock is disabled.

0 GPTCLK0OFF

General-Purpose Timer 0 User Control. This bit disables the General-Purpose Timer

0 clock (muxed version) and controls the gate in active and flexi modes. In

hibernate mode, the General-Purpose Timer 0 clock is always off and this bit has

no effect. This bit is automatically cleared if user code accesses any of the General-

Purpose Timer 0 registers.

0x1 R/W

0 Timer 0 clock is enabled.

1 Timer 0 clock is disabled.

CLOCKING STATUS REGISTER

Address: 0x4004C318, Reset: 0x00000000, Name: STAT0

Table 10. Bit Descriptions for STAT0

Bits Bit Name Settings Description Reset Access

[15:3] Reserved Reserved. Do not write to this bit. 0 R

2 SPLLUNLK System Phase-Locked Loop (PLL) Unlock Status. Write a 1 to this bit to clear it. R/W1C

0 No loss of PLL lock detected. 0

1 A PLL loss of lock is detected.

1 SPLLLK System PLL Lock Status. Write a 1 to this bit to clear it. 0 R/W1C

0 No PLL lock event detected.

1 A PLL lock event is detected.

0 SPLL System PLL Status. 0 R

0 PLL is not locked, do not use PLL.

1 PLL is locked and ready for use.

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