Cypress Traveo s6j3310 series User manual

S6J3310 Series

S6J3320 Series

S6J3330 Series

S6J3340 Series

32-bit Microcontroller

Traveo™ Family

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-10635 Rev. *I Revised September 5, 2018

The Traveo family expands the company’s automotive applications, scalability and high performance into one line-up and at the

same time adds new features to fulfill the latest requirements of the automotive industry. Based on the powerful Arm® Cortex®- R5F

core in single operations, it offers state-of-the-art real time performance, safety and security features. The family supports the latest

in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated

features to increase data security in the car.

S6J3310/20/30/40 is a microcontroller series for instrument clusters with small thin-film transistor (TFT) displays.

Features

System

32-bit Arm Cortex-R5F CPU core at up to 240 MHz

General purpose I/O port: up to 148

12-bit A/D converter: up to 48 channels

External interrupt: up to 24 channels

Base timer: up to 32 channels

32-bit reload timer: up to 6 channels

32-bit free-run timer: 8 channels

Input capture unit: 12 channels

Output compare unit: 12 channels

Stepper motor controller (SMC): 6 Units

Built-in CR oscillator

Real-time clock

DMA controller: 16 channels

JTAG debug interface

Graphics and Display (optional)

2D graphic engine

RGB888

LCD：up to 4 COM x 32 SEG

Communication

CAN-FD: up to 6 channels

Multi-function serial interface: up to 12 channels,

selectable protocol: UART, CSIO, LIN and I2C

Ethernet AVB MAC (optional)

MediaLB (optional)

Automotive Remote Handler for APIX® (optional)

Memory

HyperBus™ Memory interface

DDR High Speed SPI

External BUS interface

Multimedia (optional)

I2S input/output: 2 channels

PCM to PWM output unit

Sound mixer: 1 unit x 10 inputs

Stereo audio DAC

Security and Safety

Secure Hardware Extension – SHE

Safety features, such as MPU, TPU, ECC and others

CRC generator: 1 channel

Watchdog timer with window function

Low voltage detector

Clock supervisor for all source clocks

Applications

Instrument cluster

 
 
 
 
 
Document Number: 002-10635 Rev. *I Page 2 of 325 
 
 
 
S6J3310/20/30/40 Series 
 
Table of Contents 
Overview........................................................................3 
1 Overview ...................................................................3 
2 Document Definition..................................................3 
Function List .................................................................4 
1 Function List..............................................................4 
2 Optional Function......................................................6 
Product Description......................................................9 
1 Overview ...................................................................9 
2 Product Description...................................................9 
Package and Pin Assignment....................................15 
1 Pin Assignment .......................................................15 
2 Package Dimensions...............................................27 
IO Circuit Type ............................................................31 
1 I/O Circuit Type .......................................................31 
2 Note.........................................................................36 
Port Description..........................................................37 
1 Port Description List ................................................37 
2 Remark................................................................... 58 
Port Configuration...................................................... 59 
1 Resource Input Configuration Module .................... 59 
2 Port Output Function Configuration ...................... 148 
Precautions and Handling Devices......................... 158 
1 Handling Precautions............................................ 158 
2 Handling Devices.................................................. 161 
Electric Characteristics............................................ 163 
1 Electrical Characteristics....................................... 163 
Acronyms.................................................................. 261 
Ordering Information................................................ 262 
Errata......................................................................... 263 
Appendix................................................................... 265 
1 Application 1: JTAG Tool Connection................... 265 
Major Changes.......................................................... 266 
Document History.......................................................... 323 
Sales, Solutions, and Legal Information...................... 325 
 

Document Number: 002-10635 Rev. *I Page 3 of 325

S6J3310/20/30/40 Series

1. Overview

1.1 Overview

S6J3310/20/30/40 is a microcontroller series which is to be applied to automotive systems representative of a graphical cluster

control unit on a dashboard.

1.2 Document Definition

The related documents of S6J3310/20/30/40 are the followings.

Table 1-1: Document Definition

Document Type

Definition

Primary User

Document Code

S6J3310/20/30/40

Datasheet

This document.

The function and its characteristics

are specified quantitatively.

Investigator and hardware

engineer

002-10635

S6J3300 Hardware

Manual

S6J3300 Series 32-bit Microcontroller

Traveo™ Family Hardware Manual

The function and its operation of

S6J3300 series are described.

Software engineer

002-10185

TraveoTM Platform

Hardware Manual

32-Bit Microcontroller Traveo™

Family S6J33xx, S6J34xx, S6J35xx

Series Hardware Manual Platform

Part

The function and its operation of CPU

core platform are described.

Software engineer

002-07884

Application Note

The reference software, sample

application, the reference board

design and so on are explained.

Software and hardware engineer

002-03898

002-04455

002-04446

002-09716

002-04452

002-04096

002-12061

002-02495

Notes:

−Refer all documents for the system development.

−"Primary user" is a most likely engineer for whom the document is the most useful.

−The description of the datasheet and the S6J3300 Hardware Manual should precede the duplicated description of TraveoTM

Platform Hardware Manual.

−TraveoTM Platform Hardware Manual is expected to be used as dictionary of platform specification.

Document Number: 002-10635 Rev. *I Page 4 of 325

S6J3310/20/30/40 Series

2. Function List

2.1 Function List

The table shows the functions which are implemented in S6J3310/20/30/40 series.

Table 2-1: Function List

Function

S6J3310

S6J3320

S6J3330

S6J3340

Remarks

CPU core

Arm Cortex R5F

FPU

Available

PPU

Available

MPU

Available

TPU

Available

Endian

Little endian

Core clock frequency

240 MHz

HPM bus frequency

200 MHz

LLPM bus frequency

240 MHz

Resource clock frequency

80 MHz (Max)

Embedded CR oscillation

Slow clock:100 kHz,

Fast clock: 4 MHz

(Center frequency)

See 9.1.4.1

PLL

PLL0, 1, 2, 3

SSCG PLL

SSCG0, 1, 2, 3

Clock supervisor

Available

DMA

16 ch

Boot-ROM

16 Kbyte

JTAG

Available

Data cache

16 Kbyte

Instruction cache

16 Kbyte

Program FLASH

Option

See 2.2.1

Work FLASH

112 Kbyte

TCRAM

128 Kbyte

System SRAM

384 Kbyte

Backup RAM

32 Kbyte

Security (SHE)

Option

Low latency interrupt

Available

Power domain

5 domains

External power supply

5 V (VCC5, VCC53),

3 V (VCC3, VCC53),

1.2 V (VCC12)

Embedded LDO power supply

for 5.0 V

Available

Low voltage detection of

external power supply

Available

Low voltage detection of

internal LDO output

Available

Hardware watchdog timer

Available

Software watchdog timer

Available

Package

Option

See 2.2.1

AUTOSAR

AUTOSAR 4.0.3

General Purpose I/O

Option

See 2.2.3

Up/down counter

2 ch

I/O timer

(FRT 5 ch x ICU 6 ch x OCU 6 ch) + (FRT 3 ch x ICU 6 ch x OCU 6

ch)

32bit Reload timer

6 ch

Real time clock

Available

Automatic calibration

Sound generator

5 ch

Sound waveform generator

1 unit x 5 outputs

See 2.2.1

Sound mixer

1 unit x 10 inputs

See 2.2.1

Document Number: 002-10635 Rev. *I Page 5 of 325

S6J3310/20/30/40 Series

Function

S6J3310

S6J3320

S6J3330

S6J3340

Remarks

Stereo audio DAC

1 unit (L and R)

See 2.2.1

PCM-PWM

1 unit (L and R)

See 2.2.1

Base timer

16 units (32 ch)

Stepping motor controller

(SMC)

For 6 gauges

12bit-A/D converter

2 unit - 48 input ports (Max)

See 2.2.3

CRC

4 units

Programmable CRC

1 unit

Source clock timer

4 ch

NMI

Available

External interrupt

24 ch

Internal interrupt

512 vectors

I2S

2 ch

1 ch

One only supports

an output as a

function of the sound

system.

DDR HSSPI

1 ch

A type of Quad SPI

Hyper BUS

1 ch

See the AC

specification on

9.1.4.17.

Multi-function serial interface

12 ch

CAN-FD

6 ch

CAN-FD RAM (ECC

supported)

16 KB/ch

It equivalents to 128 message buffer per channel of MCAN module

Ethernet AVB

1 unit

See 2.2.1

Media-LB (MOST50)

1 unit

See 2.2.1

LCD controller

4 COM x 32 SEG (Max)

See 2.2.3

Indicator PWM

1 ch

MPU for AHB

1 unit

MPU for AXI

1 unit

Graphic engine clock

80 MHz (Max)

Graphic AXI clock

80 MHz (Max)

Display clock

25 MHz

Display clock source

Graphic display controller clock or external clock

Target resolution

WQVGA 480 x 272

Target frame rate

60 fps

Number of display outputs

1 output

TTL output (RGB888)

Option

See 2.2.1

2D Graphic engine

1 unit

2D Driver API

CYPRESS proprietary

External BUS

1 ch

APIX® for ARH

(Automotive Remote Handler)

1 unit (2 ch)

See 2.2.1

Notes:

−The options are described in 2.2.

Document Number: 002-10635 Rev. *I Page 6 of 325

S6J3310/20/30/40 Series

2.2 Optional Function

2.2.1 Basic Option

The figure shows the optional function and the part number relations of the series.

Figure 2-1: Option and Part Number for S6J3310/20/30/40 Series

Notes:

−This table only shows the relations between the optional function and the part numbers. That is, all products are not

necessarily available for orders. See 11, and confirm actual availabilities of products.

−The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.

S 6 J 3 x x x x x x x

Digit

Digit SHE MK_CEER* VCC DVCC

S5V

B3V

U5V

D3V

T5V

F3V

V5V

H3V

Digit Pin Count

H144pin

J176pin

K208pin

Program Work Main Backup

E4,160KB 112KB 512KB 16+16KB

D3,136KB 112KB 512KB 16+16KB

C2,112KB 112KB 512KB 16+16KB

B1,600KB 112KB 512KB 16+16KB

Digit Graphic Ethernet MediaLB

Sound

System

ARH for

APIX

1Yes Yes Yes Yes Yes

2Yes Yes Yes Yes -

3Yes Yes Yes - -

4Yes - - - -

Selectable

OFF

Identifer: Automotive MCU

* Chip Erase Enable Register

Pin count:

Memory size:

Digit

Flash

RAM

Function:

Product series

Revision:

Option:

Fixed to

Enable

Fixed TCFLASH Sector Write Permission and Data Retention after Reset

OFF

Fixed Stabilization time for sub oscillator

Leakage current improvement

Fixed Operation frequency of embedded Program Flash and CPU,

Description

Ordering options 7 digit

Document Number: 002-10635 Rev. *I Page 7 of 325

S6J3310/20/30/40 Series

2.2.2 ID

ID is specified for each function digit and revision which is defined at Figure 2-1.

Function Digit

Revision

Chip ID

JTAG ID

S,U,T,V

0x10122100

0x1000B5CF

D, E

0x10122200

A,C,E,G

0x10128100

D, E

0x10128200

B,D,F,H

0x10120100

D, E

0x10120200

2.2.3 Restriction

Some functions have restrictions which depend on package pin counts.

Table 2-2: Pin Restriction

Function

TEQFP176

TEQFP144

Analog input port (12bit-

ADC)

AN4~7, AN10~11,

AN14~15,

AN25~26, AN28~30,

SEG port of LCD controller

SEG0~3

SEG5~8

General Purpose I/O

P4_00 ~ P4_31

P3_00 ~ P3_31

CAN

RX0_2, TX0_2

RX1_0, TX1_0

RX1_1, TX1_1

RX2_0, TX2_0

RX2_1, TX2_1

RX3_2, TX3_2

RX0_1, TX0_1

RX0_2, TX0_2

RX1_0, TX1_0

RX1_1, TX1_1

RX2_0, TX2_0

RX2_1, TX2_1

RX3_1, TX3_1

RX3_2, TX3_2

RX5_1, TX5_1

RX6_1, TX6_1

BaseTimer

PPG4/5/6/7/8/9_TOUT0_1

PPG4/5/6/7/8/9_TOUT2_1

PPG10/11/12/13/15_TOUT0_1

PPG10/11/12/13/14/15_TOUT2_1

PPG0/1/2/3/4/5_TIN1_1

PPG6/7/8/9/10/11_TIN1_1

PPG12/13/14/15_TIN1_1

ExtBus

MDQM1

MAD15~21

MDATA8~15

Document Number: 002-10635 Rev. *I Page 8 of 325

S6J3310/20/30/40 Series

Function

TEQFP176

TEQFP144

External Interrupt

EINT1_4, EINT1_5

EINT2_1, EINT2_2

EINT3_2, EINT4_2

EINT5_4, EINT5_5

EINT6_4, EINT7_1

EINT7_4, EINT8_4

EINT8_5, EINT9_1

EINT10_1, EINT10_4

EINT10_5, EINT13_2

EINT13_3, EINT14_2

EINT14_3, EINT15_3

EINT16_1, EINT16_3

EINT16_4, EINT19_4

EINT20_3, EINT21_3

EINT22_1, EINT22_3

EINT23_3, EINT23_4

EINT0_4, EINT1_1

EINT1_4, EINT1_5

EINT2_1, EINT2_2

EINT2_4, EINT3_1

EINT3_2, EINT3_4

EINT4_2, EINT4_4

EINT5_4, EINT5_5

EINT6_1, EINT6_4

EINT7_1, EINT7_4

EINT8_1, EINT8_4

EINT8_5, EINT9_1

EINT9_2, EINT10_1

EINT10_2, EINT10_4

EINT10_5, EINT11_2

EINT11_5, EINT12_1

EINT12_2, EINT12_5

EINT13_2, EINT13_3

EINT13_5, EINT14_1

EINT14_2, EINT14_3

EINT14_5, EINT15_2

EINT15_3, EINT16_1

EINT16_2, EINT16_3

EINT16_4, EINT16_5

EINT17_1, EINT17_3

EINT17_5, EINT18_1

EINT18_3, EINT18_5

EINT19_1, EINT19_3

EINT19_4, EINT20_1

EINT20_2, EINT20_3

EINT21_1, EINT21_3

EINT22_1, EINT22_3

EINT23_3, EINT23_4

Notes:

−See multiplexed functions on pin assignment sheet.

−The optional restriction will be added without notification.

Document Number: 002-10635 Rev. *I Page 9 of 325

S6J3310/20/30/40 Series

3. Product Description

3.1 Overview

This chapter explains the product features of S6J3310/20/30/40 series. The description of this chapter should precede the

duplicated description on TraveoTM Platform Hardware Manual.

3.2 Product Description

The table shows features.

Table 3-1: Product Features

Feature

Description

Technology

40-nm CMOS technology with embedded FLASH

Fully automotive qualified according to ISO/TS 16949 and AEC-Q100

Developed according to ISO26262, safety target ASIL-B

Functional Safety

The product series has some functional safety features suited for ASIL-B application.

Peripherals

See function list.

Power Domain (PD)

See the TraveoTM Platform Hardware Manual and chapter STATE TRANSITION in detail.

The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,

PD4_1 and PD6.

The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,

and "0" is always read from the reset factor flags of them.

This series doesn't support partial wakeup for PD6.

Debug and Trace

See the TraveoTM Platform Hardware Manual in detail.

−Standard 5-pin JTAG interface

−4 kB Embedded Trace Buffer

4-bit trace support for TEQFP package.

System Control

See the TraveoTM Platform Hardware Manual in detail.

Main and sub oscillator is available.

−A wide range of 3.6 - 16MHz is available for main oscillator

−32KHz is available for sub oscillator

Sub clock is enable/disable by register settings

Clock

See the TraveoTM Platform Hardware Manual in detail.

CLK_CLKO (Clock Output Function) is supported.

Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)

Embedded CR oscillation

See the TraveoTM Platform Hardware Manual in detail.

Stabilization time is as followings.

−0.35 ms to 0.8 ms for 4 MHz (Fast clock)

−0.43 ms to 1.28 ms for 100 kHz (Slow clock)

Clock Supervisor

See the TraveoTM Platform Hardware Manual in detail.

This product series doesn’t support clock supervisor output port. (Related register and internal

circuit is implemented.)

Reset

RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)

−Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD

−Release factor: Inputting “H” level to RSTX pin

See the TraveoTM Platform Hardware Manual in detail.

Following resets are not mounted on this device.

−SRSTX (and nSRST pin)

The product series does not support EX5VRST and writing EX5VRSTCNT bits in

SYSC0_SPECFGR has no effect.

Document Number: 002-10635 Rev. *I Page 10 of 325

S6J3310/20/30/40 Series

Feature

Description

Hardware watchdog

See the TraveoTM Platform Hardware Manual in detail.

Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the

bit

ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK = 1).

The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and

internal circuit is implemented.)

Standby mode

See the TraveoTM Platform Hardware Manual in detail.

Standby mode with 5 V (or 3 V) single external power supply is available.

Turning off the 1.2 V external power supply in standby mode is available.

The long term pulse of the indicator PWM can be outputted during RTC Standby mode.

PLL / SSCG PLL

See the TraveoTM Platform Hardware Manual in detail.

Use case assumption is following.

PLL

−Sound system clock

−Sound frequency master clock

−Peripherals

−Display clock

−Trace clock

SSCG

−CPU core

−GDC core

−Hyper BUS

−DDR-HSSPI

Product supports down spread and center spread modes with the conditions defined in 9.1.4.3

Internal Clock Timing (S6J3310).

External Interrupts

See the TraveoTM Platform Hardware Manual in detail.

NMI

See the TraveoTM Platform Hardware Manual in detail.

1 NMI pin.

Memory Protection

MPU16 AHB: See the TraveoTM Platform Hardware Manual in detail.

MPU for AXI: ch.0

MPU for AHB: ch.1

Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the

chapter of MPU for AHB and MPU for AXI

To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,

− Lock: 0x112ABB56

− Unlock: 0xACCABB56

Peripheral Protection

See the TraveoTM Platform Hardware Manual in detail.

Protected peripherals are described in the base address map.

Internal Memories

System SRAM

384 KByte

1 wait cycle is necessary for RAM read at over 120MHz.

Internal Memories

TCRAM

128 KByte

Internal Memories

Backup RAM

32 KByte

Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the

memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM

is not supported and cannot be used.

Document Number: 002-10635 Rev. *I Page 11 of 325

S6J3310/20/30/40 Series

Feature

Description

Embedded

Program/Work Flash

Memory

Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80MHz or less.

0-wait-cycle: 80MHz or less.

1-wait-cycle: 160MHz or less.

2-wait-cycle: more than 160MHz.

Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.

6-wait-cycle: 80MHz or less.

12-wait-cycle: 160MHz or less.

The wait-cycle setting see the TraveoTM Platform Hardware Manual in details.

The CLK_FCLK maximum frequency should be referred in 9.1.4.3.

Erase suspend is supported. Reading and writing to the other sector are possible when Flash

Erase is suspended.

Serial Flash programing and Parallel Flash programing are supported.

Margin mode is not supported.

Internal Power Domain

PD1: Always ON

PD2: Cortex R5F platform/ GDC/ additional peripherals

PD4: Backup RAM in Always On domain

PD6: Peripherals in Always On domain

* The chapter of the block diagram explains in detail.

Power Supply

5 V, and 3 V, 1.2 V external power supply is required.

Built in LDO provides internal power supply for Always On region (PD1).

1.2 V external power supply control pin is supported.

3 V external power supply could be controlled by GPIO.

There are constraints of power on/off sequence.

Low Voltage Detection

LVD for external voltage is supported.

LVD for internal voltage is supported.

See 9.1.4.11 and 9.1.4.12.

Low voltage detection for

RAM retention (RVD)

RVD for RAM retention is effective during the standby mode only. That is, it is only for the

Backup RAM of 32KB that the function is available.

Resource inter-connect

The output signal of some resources can be inputted to the other resource.

I/O Ports

5 V general purpose I/O

3 V general purpose I/O

Multi input level and multi output drivability

Pull-up, pull-down function is available.

Resource input and output is multiplexed.

+B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain.

A/D Converter

12 bit resolution, 2 unit (Unit0 is possible to select channels 4-31. Unit1 is possible to select

channels 32-63.)

48 channels of analog input for TEQFP208

48 channels of analog input for TEQFP176

35 channel of analog input for TEQFP144

24 channels of them are shared with the SMC for TEQFP208/176/144

External trigger and timer trigger are available.

The description of the A/D converter function should be referred in the S6J3300 Hardware

Manual. Though the chapter of I/O port in TraveoTM Platform Hardware Manual describes

another A/D converter function, do not refer it.

A/D Channel Control Register (ADC12Bn_CHCTRL0) [bit5:0] ANIN[5:0]: Analog Input Selection

bits.

This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).

AN39 to AN63 are not support for S6J33xxxAx, S6J33xxxCx, S6J33xxxEx, and S6J33xxxGx

option.

CRC

See the TraveoTM Platform Hardware Manual in detail.

Document Number: 002-10635 Rev. *I Page 12 of 325

S6J3310/20/30/40 Series

Feature

Description

Programmable CRC

DMA support

Sound Generator

Produces sound/melody with varying frequency and amplitude for convenient duration

Square wave sound output

Automatic linear amplitude increment or decrement

Interrupt request generated when specified sound length has ended

Sound Waveform

generator

Sine waveform, saw-tooth waveform and Square waveform are generated with easy

configuration of the parameters which specified sound sources.

Fade-in and Fade-out control for reverberation.

Sound Mixer

The input channels of 0 - 4 are reserved for waveform generator.

Mixing different sampling frequency sounds.

Mixing Internal sounds and External I2S input sounds.

Saturating addition function for keeping sound quality.

Cut a specific frequency data by digital filter.

LPF is support by FIR filter.

Fade-in and Fade-out control.

PCM-PWM

Conversion of PCM audio streaming to Pulse Width Modulated signals.

Supports 2 output channels for stereo and mono data

Up to 16-bit output sample resolution

Support for half and full H-bridges

Audio DAC

The sound source of the fixed 48 kHz sampling frequency can be outputted.

1 unit, L/R channels support.

BTL connection is available.

I2S

2 ch.

−I2S0 only supports the output of sound sources.

−I2S1 supports both the input and the output.

Base Timer

See the TraveoTM Platform Hardware Manual in detail.

A unit consists of a pair of 16-bit base timers. 16 units, that is, 32 channels of base timers are

available.

Reload Timer

See the TraveoTM Platform Hardware Manual in detail.

I/O Timer

See the TraveoTM Platform Hardware Manual in detail.

Up/Down Counter

See the TraveoTM Platform Hardware Manual in detail.

Multi-Functional Serial

(MFS)

See the TraveoTM Platform Hardware Manual in detail.

Only 2 ports of MFS have the dedicated I/O for I2C.

See I2C timing in 9.1.4.6 Multi-Function Serial in detail.

The I2C is not designed to be hot swappable.

CTS/RTS is not mounted (hardware flow control is not supported for this series.)

CAN-FD

Flexible data rate is supported.

16 KB/ch of message RAM is available.

The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function

of the message RAM is not supported for this device. Therefore CAN FD ECC Error Insertion

Control Register (FDFECR) is not writeable.

Real Time Clock (RTC)

with auto-calibration

See the TraveoTM Platform Hardware Manual in detail.

DDR High Speed SPI

ch.0: HSSPI as a MCU peripheral

Hyper BUS I/F

ch.0: Hyper Bus as a MCU peripheral

The following register is not supported and cannot be used.

−Controller Status Register (HYPERBUSIn_CSR)

−Interrupt Enable Register (HYPERBUSIn_IEN)

−Interrupt Status Register (HYPERBUSIn_ISR)

−Write Protection Register (HYPERBUSIn_WPR)

−Test Register (HYPERBUSIn_TEST)

GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can

select using HyperBus of PF or using HyperBus of Graphic Sub System.

Document Number: 002-10635 Rev. *I Page 13 of 325

S6J3310/20/30/40 Series

Feature

Description

Stepper Motor Control

(SMC)

Each channel has 6 motor drivers with high output capability

External Interrupt Capture

Unit (EICU)

See the TraveoTM Platform Hardware Manual in detail.

Ethernet AVB

10/100 Mbps

MII-Interface

Supports Audio-Video Bridging (AVB)

MediaLB

MOST50 (1024FS)

3 wires

Maximum 15 ch is available.

LCD Controller

TEQFP208: 4 com x 32 seg

TEQFP176: 4 com x 32 seg

TEQFP144: 4 com x 24 seg

LCDC pins are initialized with Reset. (Stop LCDC alternating current output)

Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2,

SEG26/ST3, SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8)

SHE

See the TraveoTM Platform Hardware Manual in detail.

Source Clock Timer

See the TraveoTM Platform Hardware Manual in detail.

Graphics Subsystem

80 MHz maximum clock frequency

Variable setting about GDC clock. (Asynchronous with CPU clock)

480 x 272 pixels maximum frame resolution

Video modes up to 25 MHz pixel clock

RGB888,

Order replacement of RGB pins.

External BUS

TEQFP208: 22 bit address and 16 bit data

TEQFP176: 22 bit address and 16 bit data

TEQFP144: 15 bit address and 8 bit data

ARH

2 ch

This device does not have PHY macro and its function.

Power Supply Control

(PSC)

PSC (PSC_1) output is used for external 1.2 V power supply module control and automatically

switched with the following condition.

"High": Request to supply VCC12

- "Power ON Reset" is released

- CPU wakes up from PSS shutdown mode

"Low": Request to stop supplying VCC12

- CPU transfers from RUN mode to PSS shutdown mode.

For timing chart of output signals include PSC in detail, see the "S6J3300 Hardware Manual"

and chapter "State Transition"

Document Number: 002-10635 Rev. *I Page 14 of 325

S6J3310/20/30/40 Series

3.2.1 Ethernet

The following functions are not supported.

Functions

Remarks

External FIFO Interface

Additional Low Latency TX FIFO Interface for DMA configurations

MAC Transmit Block

- half-duplex

- collision

- back_pressure

MAC Filtering Block

- external address match

- Wakeup On Lan

Energy Efficient Ethernet support

LPI Operation in Cadence IP

PHY Interface

- GMII

- SGMII

- TBI

10/100/1000 Operation

- 1000 M

SGMII Operation

Jumbo Frames

Physical Control Sub-Layer

Document Number: 002-10635 Rev. *I Page 15 of 325

S6J3310/20/30/40 Series

4. Package and Pin Assignment

4.1 Pin Assignment

Alphabets with pin numbers are signs specify I/O circuit type.

4.1.1 TEQFP-208 Pin Assignment

Figure 4-1: TEQFP-208 (S6J331xKyz *1)

*1: x, y, z are selected from the following parameters:

x: E, D, C, B (Memory Size)

y: S, A, B, U, C, D, T, E, F, V, G, H (Option)

z: C, D, E (Revision)

LCDD4

LCDD3

LCDD0

SCS43_0

SCS42_0

LCDD2

LCDD1

SDA4

SCL4

SCS32_1

SCS31_1

SCS23_1

SCS22_1

SCS21_1

SCS20_1

SOT2_1

SCL12

SDA11

SCL11

SDA10

SCL10

SDA9

SCS41_0

SCS40_0

SOT4_0

SCK4_0

SIN4_0

SCS33_1

EINT20_5

EINT19_5

SCS30_1

SOT3_1

SCK3_1

SIN3_1

PPG14_TOUT0_1

PPG13_TOUT2_1

PPG13_TOUT0_1

PPG12_TOUT2_1

PPG12_TOUT0_1

SDA12

SCK12_0

SIN12_0

SCS111_0

SCS110_0

SOT11_0

SCK11_0

SIN11_0

SCS100_0

SOT10_0

SCK10_0

SIN10_0

SCS91_0

SCS90_0

SOT9_0

EINT3_6

EINT2_6

EINT1_6

EINT0_6

EINT23_5

EINT22_5

EINT0_0

EINT21_5

ADTRG1_2

ADTRG0_1

PPG12/13/14/15_TIN1_1

PPG15_TOUT2_1

PPG15_TOUT0_1

PPG14_TOUT2_1

EINT15_5

EINT14_5

EINT13_5

EINT12_5

EINT11_5

SCS120_0

SOT12_0

PPG12/13/14/15_TIN1_0

PPG15_TOUT2_0

PPG15_TOUT0_0

PPG14_TOUT2_0

PPG14_TOUT0_0

PPG13_TOUT2_0

PPG13_TOUT0_0

PPG12_TOUT2_0

PPG12_TOUT0_0

PPG6/7/8/9/10/11_TIN1_0

PPG11_TOUT2_0

PPG11_TOUT0_0

PPG10_TOUT2_0

PPG10_TOUT0_0

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

EINT18_5

EINT17_5

EINT16_5

EINT3_1

SEG4

SEG3

SEG2

SEG1

SEG0

SCK2_1

SIN2_1

EINT9_5

EINT7_5

EINT6_5

EINT23_0

EINT4_5

EINT3_5

EINT2_5

EINT0_5

EINT22_0

EINT22_4

EINT21_4

EINT20_4

EINT21_0

EINT18_4

EINT17_4

EINT15_4

MAD0

MDATA7

MDATA6

MDATA5

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

MCSX1

SEG8

SEG7

SEG6

SEG5

MCSX0

MDATA11

MDATA10

MDATA9

MDATA8

PWM2M5

PWM2P5

PWM1M5

PWM1P5

PWM2M4

PWM2P4

PWM1M4

PWM1P4

PWM2M3

PWM2P3

PWM1M3

PWM1P3

PWM2M2

PWM2P2

PWM1M2

EINT16_4

PWM1P2

DSP0_R6_0

DSP0_R5_0

DSP0_R4_0

DSP0_R3_0

DSP0_R2_0

DSP0_R1_0

DSP0_R0_0

DSP0_CLK_0

DSP0_VSYNC_0

DSP0_HSYNC_0

MDATA15

MDATA14

MDATA13

MDATA12

DSP0_EN_0

I2S0_SCK_1

I2S0_WS_1

I2S0_SD_1

I2S0_ECLK_1

EINT10_5

EINT2_1

AN63

EINT8_5

AN62

AN61

AN60

EINT5_5

AN59

AN58

AN57

EINT1_5

AN56

AN55

EINT23_4

AN54

AN53

AN52

EINT19_4

AN51

AN50

AN49

AN47

VSS

P2_19

P2_18

P2_17

P2_16

P2_15

P2_14

P2_13

P2_12

P2_11

P2_10

P3_31

P3_30

P3_29

P3_28

VCC53

VSS

VCC12

P2_09

P3_27

P3_26

P3_25

P3_24

P4_31

P4_30

DVCC

DVSS

P2_08

P4_29

P2_07

P2_06

P2_05

P4_28

P2_04

P2_03

P2_02

P4_27

P2_01

DVCC

DVSS

P2_00

P4_26

P1_31

P1_30

P1_29

P4_25

P1_28

P1_27

P1_26

P4_24

P1_25

DVCC

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

- - - - - - - - - - - - - VCC53 - 1 156 -DVSS - - - - - - - - - - - - -

- - - - - - - - LCDD5 EINT0_1 SEG19 MAD1 DSP0_R7_0 P0_00 S 2 155 P P1_24 AN46 PWM2M1 EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - - -

- - - - - LCDD6 ARH0_AIC1_TCKI ARH0_AIC1_DNCLK SIN1_0 EINT1_0 SEG20 MAD2 DSP0_G0_0 P0_01 S 3 154 P P1_23 AN45 PWM2P1 EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - - -

- - - - LCDD7 ARH0_AIC1_DNDATA1 ARH0_AIC1_TDA1 SCL1 SCK1_0 EINT4_1 SEG21 MAD3 DSP0_G1_0 P0_02 S 4 153 P P1_22 AN44 PWM1M1 EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - - -

- - - - - LCDD8 ARH0_AIC1_dbg_out_1 SDA1 SOT1_0 EINT5_1 SEG22 MAD4 DSP0_G2_0 P0_03 S 5 152 P P1_21 AN43 PW M1P1 EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - - -

- - - - - - - - - RX0_2 - EINT7_1 RXCLK_1 P4_00 T 6 151 P P1_20 AN42 PWM2M0 EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - - -

- - - - - - - - - TX0_2 - EINT9_1 RXER_1 P4_01 T 7 150 P P1_19 AN41 PWM2P0 EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - - -

- - - - - - - - - - - EINT10_1 RXDV_1 P4_02 T 8 149 P P1_18 AN40 PWM1M0 EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - - -

- - - - - LCDD9 ARH0_AIC1_dbg_out_0 SIN0_1 SCS10_0 EINT11_1 SEG23 MAD5 DSP0_G3_0 P0_04 S 9 148 P P1_17 AN39 PWM1P0 EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - - -

- - - - LCDD10 ARH0_AIC1_DNDATA0 ARH0_AIC1_TDA0 SOT0_1 SCS11_0 EINT13_1 SEG24 MAD6 DSP0_G4_0 P0_05 S 10 147 - DVCC - - - - - - - - - - - - -

- - LCDD11 ARH0_AIC1_UPCLK ARH0_AIC1_RCK SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 SEG25 MAD7 DSP0_G5_0 I2S1_ECLK_0 P0_06 S 11 146 -DVSS - - - - - - - - - - - - -

- - LCDD12 ARH0_AIC1_UPDATA1 ARH0_AIC1_RDA1 SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 SEG26 MAD8 DSP0_G6_0 I2S1_SD_0 P0_07 S 12 145 -AVSS - - - - - - - - - - - - -

- - - - LCDD13 ARH0_AIC1_UPDATA0 ARH0_AIC1_RDA0 PPG1_TOUT0_1 EINT0_2 SEG27 MAD9 DSP0_G7_0 I2S1_WS_0 P0_08 S 13 144 -AVRL5 - - - - - - - - - - - - -

- - - LCDD14 ARH0_AIC0_TCKI ARH0_AIC0_DNCLK SIN17_1 PPG1_TOUT2_1 EINT1_2 SEG28 MAD10 DSP0_B0_0 I2S1_SCK_0 P0_09 S 14 143 - AVRH5 - - - - - - - - - - - - -

- - - - - - - - SCS170_1 RX3_2 - EINT2_2 TXCLK_1 P4_03 T 15 142 - AVCC5 - - - - - - - - - - - - -

- - - - - - - - SCK17_1 TX3_2 - EINT3_2 TXEN_1 P4_04 T 16 141 G P4_23 - EINT10_4 - - SCS160_1 - - - - - - - -

- - - - - - - - - SOT17_1 - EINT4_2 TXD0_1 P4_05 T 17 140 E P4_22 ADTRG1_0 EINT22_1 - - SCS161_1 - - - - - - - -

- - - LCDD15 ARH0_AIC0_DNDATA1 ARH0_AIC0_TDA1 SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29 MAD11 DSP0_B1_0 I2S0_ECLK_0 P0_10 S 18 139 H P1_16 ADTRG0_0 - EINT9_4 SGO4_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 - -

- - - - - LCDD16 ARH0_AIC0_dbg_out_1 PPG2_TOUT2_1 EINT6_2 SEG30 MAD12 DSP0_B2_0 I2S0_SD_0 P0_11 S 19 138 G P4_21 - EINT8_4 - SCK16_1 - - - - - - - - -

- - - - - LCDD17 ARH0_AIC0_dbg_out_0 PPG3_TOUT0_1 EINT7_2 SEG31 MAD13 DSP0_B3_0 I2S0_WS_0 P0_12 S 20 137 G P4_20 - EINT7_4 - - SOT16_1 - - - - - - - -

- - - - - CS# ARH0_AIC0_dbg_select PPG3_TOUT2_1 EINT8_2 COM0 MAD14 DSP0_B4_0 I2S0_SCK_0 P0_13 S 21 136 G P4_19 - EINT16_1 - - SIN16_1 - - - - - - - -

- - - - - - - - - - - - - VCC53 - 22 135 - VCC5 - - - - - - - - - - - - -

- - - - - - - - - - - - - VSS -23 134 -VSS - - - - - - - - - - - - -

- - - - - - - - - - - - - VCC12 - 24 133 - VCC12 - - - - - - - - - - - - -

- - - - - - - - SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 25 132 - VCC12 - - - - - - - - - - - - -

- - - - - - - - SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 26 131 G P4_18 - EINT6_4 - SIN12_1 - - - - - - - - -

- - - - - - - - SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 27 130 G P4_17 - EINT5_4 - SOT12_1 - - - - - - - - -

- - - - - - - - SCS10_1 PPG5_TOUT2_1 EINT11_2 MAD18 TXER_1 P3_03 T 28 129 H P1_15 AN32 EINT16_0 SGA4_0 PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATOR0_1 - -

- - - - - - - - SCS11_1 PPG0/1/2/3/4/5_TIN1_1 EINT12_2 MAD19 RXD0_1 P3_04 T 29 128 G P1_14 AN31 EINT15_0 SGO3_0 PPG5_TOUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX3_0 SIN17_0 SYSC0_CLK_1 - - -

- - - - - - - - - - - EINT13_2 RXD1_1 P4_06 T 30 127 G P3_23 AN30 EINT4_4 TX6_1 SCS120_1 - - - - - - - - -

- - - - - - - - - - - EINT14_2 RXD2_1 P4_07 T 31 126 G P3_22 AN29 EINT19_1 RX6_1 SCS91_1 - - - - - - - - -

- - - - - - - - SCS12_1 SIN4_1 EINT15_2 MAD20 RXD3_1 P3_05 T 32 125 G P3_21 AN28 EINT3_4 TOT49_1 SCS90_1 - - - - - - - - -

- - - - - - - - SCS13_1 SOT4_1 EINT16_2 MAD21 MDIO_1 P3_06 T 33 124 E P3_20 EINT2_4 PPG6/7/8/9/10/11_TIN1_1 TIN49_1 TX5_1 SOT9_1 - - - - - - - -

- - - - - - WR# ARH0_AIC1_dbg_select SCK4_1 EINT17_2 COM1 MOEX DSP0_B5_0 P0_14 S 34 123 E P3_19 EINT17_1 PPG11_TOUT2_1 OCU10_OTD1_1 ICU10_IN1_1 RX5_1 SCK9_1 - - - - - - -

- - - - - - - RD# SCS40_1 EINT18_2 COM2 MWEX DSP0_B6_0 P0_15 S 35 122 E P3_18 EINT20_1 PPG11_TOUT0_1 OCU10_OTD0_1 ICU10_IN0_1 SIN9_1 - - - - - - - -

- - - - - - ARH0_AIC0_DNDATA0 ARH0_AIC0_TDA0 SCS41_1 EINT19_2 COM3 MCLK DSP0_B7_1 P0_16 S 36 121 -VSS - - - - - - - - - - - - -

- - - - - - - - - - SCS42_1 EINT20_2 MDQM1 P3_07 T 37 120 - C - - - - - - - - - - - - -

- - - - - - - SCS43_1 EINT21_2 V0 MDQM0 DSP0_B7_0 RXCLK_0 P0_17 V 38 119 O MODE - - - - - - - - - - - - -

- - - - - RS ARH0_AIC0_UPCLK ARH0_AIC0_RCK EINT22_2 V1 MCSX2 MDC_1 RXER_0 P0_18 V 39 118 D PSC_1 - - - - - - - - - - - - -

- - - - - RES# ARH0_AIC0_UPDATA1 ARH0_AIC0_RDA1 EINT23_2 V2 MCSX3 COL_1 RXDV_0 P0_19 V 40 117 N RSTX - - - - - - - - - - - - -

- - - - - TE ARH0_AIC0_UPDATA0 ARH0_AIC0_RDA0 EINT0_3 V3 MRDY CRS_1 TXCLK_0 P0_20 U 41 116 G P4_16 - EINT1_4 - - - - - - - - - - -

- - - - - - - - - - - - - VCC53 - 42 115 G P3_17 AN26 EINT0_4 SGO4_1 PPG10_TOUT2_1 OCU9_OTD1_1 ICU9_IN1_1 TOT48_1 TX3_1 - - - - -

- - - - - - - - - - - - - VSS -43 114 G P3_16 AN25 EINT14_1 SGA4_1 PPG10_TOUT0_1 OCU9_OTD0_1 ICU9_IN0_1 TIN48_1 RX3_1 - - - - -

- - - - - - - - - - - - - AVSS -44 113 G P1_13 AN24 EINT14_0 SGA3_0 OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - - -

- - - - - - - - - - - - - DAC_R A 45 112 L2 JTAG_TMS - - - - - - - - - - - - -

- - - - - - - - - - - - - C_R A 46 111 L2 JTAG_TCK - - - - - - - - - - - - -

- - - - - - - - - - - - - AVSS -47 110 L2 JTAG_TDI - - - - - - - - - - - - -

- - - - - - - - - - - - - AVCC3_DAC - 48 109 M JTAG_TDO - - - - - - - - - - - - -

- - - - - - - - - - - - - DAC_L A 49 108 L JTAG_NTRST - - - - - - - - - - - - -

- - - - - - - - - - - - - C_L A 50 107 KX0 - - - - - - - - - - - - -

- - - - - - - - - - - - - AVSS -51 106 KX1 - - - - - - - - - - - - -

- - - - - - - - - - - - - VSS -52 105 -VSS - - - - - - - - - - - - -

100

101

102

103

104

VCC3

P0_21

P0_22

P0_23

P0_24

P0_25

VSS

P0_26

VSS

VCC3

P0_27

P0_28

P0_29

P0_30

P0_31

VSS

VCC3

P1_00

P1_01

P1_02

VCC12

VSS

VCC5

P4_08

P4_09

P4_10

P4_11

P3_08

P3_09

P3_10

P3_11

P1_03

P1_04

P3_12

P3_13

P1_05

P1_06

P3_14

P3_15

P1_07

P1_08

P1_09

P4_12

P4_13

P1_10

P4_14

P4_15

NMIX

X0A

X1A

VCC5

M_SDATA0_0

M_SDATA0_2

M_SDATA0_1

M_SSEL0

M_SDATA0_3

M_SCLK0

M_SDATA1_0

M_SDATA1_2

M_SDATA1_1

M_SSEL1

M_SDATA1_3

MLBCLK

MLBSIG

MLBDAT

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN21

P1_11

P1_12

M_DQ3

M_DQ2

M_DQ1

M_DQ0

M_CS#_1

M_CK

M_RWDS

M_DQ4

M_DQ5

M_DQ6

M_DQ7

M_CS#_2

COL_0

CRS_0

EINT13_3

EINT14_3

EINT15_3

EINT16_3

EINT18_1

EINT6_1

EINT17_3

EINT8_1

EINT4_0

EINT5_0

EINT21_1

EINT18_3

EINT6_0

EINT7_0

EINT12_1

EINT19_3

EINT8_0

ADTRG1_1

EINT10_0

EINT20_3

EINT21_3

EINT11_0

EINT22_3

EINT23_3

EINT12_0

EINT13_0

TXEN_0

TXD0_0

TXD1_0

TXD2_0

TXD3_0

TXER_0

RXD0_0

RXD1_0

RXD2_0

RXD3_0

MDIO_0

MDC_0

EINT11_3

EINT12_3

SGA0_1

SGO0_1

SGA1_1

SGO1_1

BN0(BL0)

BP0(BH0)

SGA2_1

SGO2_1

AN0(AL0)

AP0(AH0)

SGA3_1

SGO3_1

BN1(BL1)

EINT9_0

AN1(AL1)

AP1(AH1)

PPG4_TOUT0_0

PPG4_TOUT2_0

EINT2_0

EINT1_3

EINT2_3

EINT3_3

EINT4_3

EINT5_3

EINT6_3

EINT3_0

EINT7_3

EINT8_3

EINT9_3

EINT10_3

SCS32_0

SCS33_0

PPG7_TOUT2_1

PPG0_TOUT0_0

PPG0_TOUT2_0

PPG8_TOUT0_1

PPG8_TOUT2_1

SGA0_0

SGO0_0

PPG9_TOUT0_1

PPG9_TOUT2_1

SGA1_0

BP1(BH1)

SGA2_0

SGO2_0

OCU8_OTD0_0

OCU8_OTD1_0

SIN2_0

SCK2_0

SOT2_0

SCS20_0

SCS21_0

SCS22_0

SCS23_0

SIN3_0

SCK3_0

SOT3_0

SCS30_0

SCS31_0

PPG6_TOUT0_1

PPG6_TOUT2_1

PPG7_TOUT0_1

OCU1_OTD1_1

OCU0_OTD0_0

OCU0_OTD1_0

OCU2_OTD0_1

OCU2_OTD1_1

PPG1_TOUT0_0

PPG1_TOUT2_0

OCU8_OTD0_1

OCU8_OTD1_1

PPG2_TOUT0_0

SGO1_0

PPG3_TOUT0_0

PPG3_TOUT2_0

ICU9_IN0_0

ICU9_IN1_0

SIN9_2

SOT9_2

SCK9_2

SCS90_2

SCS91_2

SIN8_2

SCK8_2

SOT8_2

SCS80_2

OCU0_OTD0_1

OCU0_OTD1_1

OCU1_OTD0_1

ICU1_IN1_1

ICU0_IN0_0

ICU0_IN1_0

ICU2_IN0_1

ICU2_IN1_1

ICU1_IN0_0

ICU1_IN1_0

ICU8_IN0_1

ICU8_IN1_1

OCU1_OTD0_0

PPG2_TOUT2_0

OCU2_OTD0_0

OCU2_OTD1_0

TIN17_0

TOT17_0

ICU0_IN0_1

ICU0_IN1_1

ICU1_IN0_1

TOT1_1

AIN8

BIN8

TIN16_1

TOT16_1

ZIN8

AIN9

TIN17_1

TOT17_1

ICU2_IN0_0

OCU1_OTD1_0

ICU8_IN0_0

ICU8_IN1_0

RX2_0

TX2_0

TIN0_1

TOT0_1

TIN1_1

RX1_1

TIN0_0

TOT0_0

TX1_1

SCK10_1

TIN1_0

TOT1_0

RX2_1

TX2_1

BIN9

ICU2_IN1_0

SCK16_0

SOT16_0

SCS160_0

SCS161_0

SIN8_1

RX0_1

TX0_1

SCS80_1

FRT0/1/2/3_TEXT

FRT4/8/9/10_TEXT

SIN10_1

TRACE3_1

RX0_0

TX0_0

SOT10_1

SCS100_1

TIN16_0

ZIN9

SCL16

SDA16

INDICATOR0_0

SCK8_1

SOT8_1

TRACE1_1

SIN0_0

SCK0_0

TRACE2_1

SOT0_0

SCS00_0

TRACE_CTL_1

TRACE_CLK_1

RX1_0

TOT16_0

TRACE_CTL_0

TRACE_CLK_0

TRACE0_1

SCL0

SDA0

TRACE1_0

TRACE2_0

TX1_0

TRACE0_0

SIN16_0

TRACE3_0

●

TOP VIEW

TEQFP-208

Document Number: 002-10635 Rev. *I Page 16 of 325

S6J3310/20/30/40 Series

Figure 4-2: TEQFP-208 (S6J332xKyz *1)

*1: x, y, z are selected from the following parameters:

x: E, D, C, B (Memory Size)

y: S, A, B, U, C, D, T, E, F, V, G, H (Option)

z: C, D, E (Revision)

LCDD4

LCDD3

LCDD0

SCS43_0

SCS42_0

LCDD2

LCDD1

SDA4

SCL4

SCS32_1

SCS31_1

SCS23_1

SCS22_1

SCS21_1

SCS20_1

SOT2_1

SCL12

SDA11

SCL11

SDA10

SCL10

SDA9

SCS41_0

SCS40_0

SOT4_0

SCK4_0

SIN4_0

SCS33_1

EINT20_5

EINT19_5

SCS30_1

SOT3_1

SCK3_1

SIN3_1

PPG14_TOUT0_1

PPG13_TOUT2_1

PPG13_TOUT0_1

PPG12_TOUT2_1

PPG12_TOUT0_1

SDA12

SCK12_0

SIN12_0

SCS111_0

SCS110_0

SOT11_0

SCK11_0

SIN11_0

SCS100_0

SOT10_0

SCK10_0

SIN10_0

SCS91_0

SCS90_0

SOT9_0

EINT3_6

EINT2_6

EINT1_6

EINT0_6

EINT23_5

EINT22_5

EINT0_0

EINT21_5

ADTRG1_2

ADTRG0_1

PPG12/13/14/15_TIN1_1

PPG15_TOUT2_1

PPG15_TOUT0_1

PPG14_TOUT2_1

EINT15_5

EINT14_5

EINT13_5

EINT12_5

EINT11_5

SCS120_0

SOT12_0

PPG12/13/14/15_TIN1_0

PPG15_TOUT2_0

PPG15_TOUT0_0

PPG14_TOUT2_0

PPG14_TOUT0_0

PPG13_TOUT2_0

PPG13_TOUT0_0

PPG12_TOUT2_0

PPG12_TOUT0_0

PPG6/7/8/9/10/11_TIN1_0

PPG11_TOUT2_0

PPG11_TOUT0_0

PPG10_TOUT2_0

PPG10_TOUT0_0

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

EINT18_5

EINT17_5

EINT16_5

EINT3_1

SEG4

SEG3

SEG2

SEG1

SEG0

SCK2_1

SIN2_1

EINT9_5

EINT7_5

EINT6_5

EINT23_0

EINT4_5

EINT3_5

EINT2_5

EINT0_5

EINT22_0

EINT22_4

EINT21_4

EINT20_4

EINT21_0

EINT18_4

EINT17_4

EINT15_4

MAD0

MDATA7

MDATA6

MDATA5

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

MCSX1

SEG8

SEG7

SEG6

SEG5

MCSX0

MDATA11

MDATA10

MDATA9

MDATA8

PWM2M5

PWM2P5

PWM1M5

PWM1P5

PWM2M4

PWM2P4

PWM1M4

PWM1P4

PWM2M3

PWM2P3

PWM1M3

PWM1P3

PWM2M2

PWM2P2

PWM1M2

EINT16_4

PWM1P2

DSP0_R6_0

DSP0_R5_0

DSP0_R4_0

DSP0_R3_0

DSP0_R2_0

DSP0_R1_0

DSP0_R0_0

DSP0_CLK_0

DSP0_VSYNC_0

DSP0_HSYNC_0

MDATA15

MDATA14

MDATA13

MDATA12

DSP0_EN_0

I2S0_SCK_1

I2S0_WS_1

I2S0_SD_1

I2S0_ECLK_1

EINT10_5

EINT2_1

AN63

EINT8_5

AN62

AN61

AN60

EINT5_5

AN59

AN58

AN57

EINT1_5

AN56

AN55

EINT23_4

AN54

AN53

AN52

EINT19_4

AN51

AN50

AN49

AN47

VSS

P2_19

P2_18

P2_17

P2_16

P2_15

P2_14

P2_13

P2_12

P2_11

P2_10

P3_31

P3_30

P3_29

P3_28

VCC53

VSS

VCC12

P2_09

P3_27

P3_26

P3_25

P3_24

P4_31

P4_30

DVCC

DVSS

P2_08

P4_29

P2_07

P2_06

P2_05

P4_28

P2_04

P2_03

P2_02

P4_27

P2_01

DVCC

DVSS

P2_00

P4_26

P1_31

P1_30

P1_29

P4_25

P1_28

P1_27

P1_26

P4_24

P1_25

DVCC

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

- - - - - - - - - - - - - VCC53 - 1 156 -DVSS - - - - - - - - - - - - -

- - - - - - - - LCDD5 EINT0_1 SEG19 MAD1 DSP0_R7_0 P0_00 S 2 155 P P1_24 AN46 PWM2M1 EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - - -

- - - - - LCDD6 - - SIN1_0 EINT1_0 SEG20 MAD2 DSP0_G0_0 P0_01 S 3 154 P P1_23 AN45 PWM2P1 EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - - -

- - - - LCDD7 - - SCL1 SCK1_0 EINT4_1 SEG21 MAD3 DSP0_G1_0 P0_02 S 4 153 P P1_22 AN44 PWM1M1 EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - - -

- - - - - LCDD8 - SDA1 SOT1_0 EINT5_1 SEG22 MAD4 DSP0_G2_0 P0_03 S 5 152 P P1_21 AN43 PWM1P1 EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - - -

- - - - - - - - - RX0_2 - EINT7_1 RXCLK_1 P4_00 T 6 151 P P1_20 AN42 PWM2M0 EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - - -

- - - - - - - - - TX0_2 - EINT9_1 RXER_1 P4_01 T 7 150 P P1_19 AN41 PWM2P0 EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - - -

- - - - - - - - - - - EINT10_1 RXDV_1 P4_02 T 8 149 P P1_18 AN40 PWM1M0 EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - - -

- - - - - LCDD9 - SIN0_1 SCS10_0 EINT11_1 SEG23 MAD5 DSP0_G3_0 P0_04 S 9 148 P P1_17 AN39 PWM1P0 EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - - -

- - - - LCDD10 - - SOT0_1 SCS11_0 EINT13_1 SEG24 MAD6 DSP0_G4_0 P0_05 S 10 147 - DVCC - - - - - - - - - - - - -

- - LCDD11 - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 SEG25 MAD7 DSP0_G5_0 I2S1_ECLK_0 P0_06 S 11 146 -DVSS - - - - - - - - - - - - -

- - LCDD12 - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 SEG26 MAD8 DSP0_G6_0 I2S1_SD_0 P0_07 S 12 145 -AVSS - - - - - - - - - - - - -

- - - - LCDD13 - - PPG1_TOUT0_1 EINT0_2 SEG27 MAD9 DSP0_G7_0 I2S1_WS_0 P0_08 S 13 144 -AVRL5 - - - - - - - - - - - - -

- - - LCDD14 - - SIN17_1 PPG1_TOUT2_1 EINT1_2 SEG28 MAD10 DSP0_B0_0 I2S1_SCK_0 P0_09 S 14 143 - AVRH5 - - - - - - - - - - - - -

- - - - - - - - SCS170_1 RX3_2 - EINT2_2 TXCLK_1 P4_03 T 15 142 - AVCC5 - - - - - - - - - - - - -

- - - - - - - - SCK17_1 TX3_2 - EINT3_2 TXEN_1 P4_04 T 16 141 G P4_23 - EINT10_4 - - SCS160_1 - - - - - - - -

- - - - - - - - - SOT17_1 - EINT4_2 TXD0_1 P4_05 T 17 140 E P4_22 ADTRG1_0 EINT22_1 - - SCS161_1 - - - - - - - -

- - - LCDD15 - - SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29 MAD11 DSP0_B1_0 I2S0_ECLK_0 P0_10 S 18 139 H P1_16 ADTRG0_0 - EINT9_4 SGO4_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 - -

- - - - - LCDD16 - PPG2_TOUT2_1 EINT6_2 SEG30 MAD12 DSP0_B2_0 I2S0_SD_0 P0_11 S 19 138 G P4_21 - EINT8_4 - SCK16_1 - - - - - - - - -

- - - - - LCDD17 - PPG3_TOUT0_1 EINT7_2 SEG31 MAD13 DSP0_B3_0 I2S0_WS_0 P0_12 S 20 137 G P4_20 - EINT7_4 - - SOT16_1 - - - - - - - -

- - - - - CS# - PPG3_TOUT2_1 EINT8_2 COM0 MAD14 DSP0_B4_0 I2S0_SCK_0 P0_13 S 21 136 G P4_19 - EINT16_1 - - SIN16_1 - - - - - - - -