Analog Devices EV-AD7284TMSDZ User manual

CHASSIS
ADDITIONAL JUMPERS ON CELL INPUTS 6/2/17 SABC
2.2UF AND 100NF PER VDD PIN
LOCAL GROUND
VSS
PLACE CLOSE TO TRANSFORMER
D_DWN_N AND DWN_P
CHASSIS
VSS
LOCAL GROUND
D_UP_N AND D_UP_P
100R DIFFERENTIAL PAIRS
200 200
* *
Transformer Isolated Config.
1
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1KOHM AT 100MEGHZ
D_DWN_P
D_UP_ND_UP
D_DWN_P
D_DWN_N
BLK
CCM
VSS
D_DWN_N
MASTER
VREFGND1
D_UP_ND_UP
VSSVSS
VDD
VSS
VREFBUF
GPO1
GPO2
68PF 68PF
0
0
0
0
0
0
0
0
0.22UF
0.22UF
0
1K
51
3 2
ADR4525BRZ
4.99K
20
0
1UF
8
2 3
AD7284
6
1
4
3
2.2UF
2.2UF
2
1
4
0
7
6
5
0
4
1
2
4
5
5
6
7
8
1
3
60OHM
1UF
BAT54W T/R
10K 4.99K
TG110-E050N5LF
68PF
0
1803280
1UF
1000PF
0
8
1000PF
68PF
1K
TG110-E050N5LF
51
SML-211UTT86
7
TSW-101-08-F-D
VREG5
SML-211UTT86
BAT54W T/R
4.99K
VREG5 LED
TSW-101-08-F-D
1UF
SML-211UTT86
BZG03C43-TR
22-28-4033
LQFP64_SKTPPE20X20HOLDER_ALT
4
C
NTS
-
-
S. Bradshaw
AD7284
-
P1
R115
R116
R30
R114
C79 C80
C78
R112
R113
P8
P9
C19C17
R12
R11
R19
R98
C67C66
R99
TP66
C76
R101R100
R15
T1
T1
R85
C14
TP67TP21
P3
TP70
TP69
TP68
TP50
R89
C75C74
C73
U10
DS1
R8
R9 DS2
DS13
R16
TP65
TP64
TP63
TP62TP61
R21 R20
CR7
CR6
R22
D5 R87
R86
R18
R17
R83
C64
C65
C63C62
C12
R24
R27
C9
U1
R109
P4
TP3TP2
TP9
R5
TP1
TP4 C2
C1
E2
C3
TP5
R1
E1
C8
C7C5
C4
CR3
C6
TP8
C13
TP11
TP14
CR4
VREG5
VSS
VSS
VREG5 VSS
DUPND_UP_N
D_UP_P
SDO DDWNN
VSS
VSS
VSS
VSS
SDI
VSS
VSS
VREG5
VSS
VDD
VREFBUF
VSS
VSS
VDRIVE
VSS
VPIN<8..0>
VSIN<8..0>
VSS
BAT-
BAT+
VDD
VPAUX<4..1>
VSS
VREFBUF
RESET VSS
VSS
DUPP
VSS
VSS
VREG5
CB<8..1>
SCLK
CS_N
D_DWN_N
D_DWN_P
VSS
DDWNP
CCM
VSS
VSS
VSS
VSS
VREG5
VREF2
VDD
VREF1
VREF2
2 1
3
2
1
2
1
1
8
6
7
11
9
10
12 5
3
1
2
16
14
15
13 4
11
3
2
1
1
1
1
1
6
28
7 5 3 1 4
A C
A C
A C
1
1
1
11
A
C
A
C
1
3
3
2
1
11
1
1
1
21
1
21
13
1
1
1
1
3
NC
AD7284_THERMISTORS
VSS
VREFBUF
VPAUX<4..1>
VREG5
GPOP1
GPOP2
PAD
VSIN8 VSIN7 VSIN6 VSIN5
CB8 CB7 CB6 CB5
D_UP_N
D_UP
NC NC
AGND2
ADCGND2 REFGND2
VREF2
NC
MASTER
DGND
DVCC
CCM
RESET
VDRIVE
CS_N
SCLK
SDI
SDO
D_DWN_N
D_DWN
AVCC VPAUX4 VPAUX3 VPAUX2 VPAUX1 VREF1 VREFBUF REFGND1 ADCGND1 VSIN4 VSIN3 VSIN2 VSIN1 VSIN0 CB4 CB3
CB2
CB1
AGND1
VSS
VSS
VPIN0
VPIN1
VPIN2
VPIN3
VPIN4
VPIN5
VPIN6
VPIN7
VPIN8
VDD
VDD
AD7284_CELL_CONNECTIONS
BAT+
VPIN<8..0>
VSIN<8..0>
CB<8..1>
BAT-
VSS
IO
NC1
VIN
GND TP
VOUT
NC
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE

VSSDGND
ISOLATORS
OPTIONAL
GPIO4 CONTROLS VDRIVE
GPIO2 CONTROLS RESET
GPIO1 ENABLES LEVEL SHIFTERS
GPIO4 IS USED TO KEEP VDRIVE LOW UNTIL THE SOFTWARE ENABLES IT.
VSS
Transformer Isolated Config.
S. Bradshaw
-
AD7284
-
NTS
C
ADP3303ARZ-5
330K
0.01UF 330K
ADP3303ARZ-3.3
0.01UF
4.7UF
1UF0.01UF
ADP7104ARDZ-5.0
0
0
0
0
0
0
0
10UF
SML-311UTT86
100K
100K 10UF
0
0.01UF 1UF
1K
1UF 0.01UF
10K
1K
1UF 10K 0
ADUM1201WTRZ
10UF
0
DNI
0
270PF
ADUM5401WCRWZ
SML-311UTT86
4.7UF
4.7UF
VDRIVE
DGND DGND DGND
VSSVSS
CS_N
SCLK
SDI
SDO
RESET
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
-
42
0.1UF
TP57
P5 DS3
R3
C10 C20
A1
C21
C22
R4
C23
U6
A2
C28 R23R6
R7
C25 C26
U4
U3
P6P6
A3
C53 C54
R26 R82
DS12
R81
R80
P7
U2
C51 C52
C16C15
R2
C24C11
R25
R14
R13
C60 C58
U5
U7
U8
U9
C61
C59
C55
C56
C57
R79
R84
R88
C68
C50
TP56
TP43 TP44 TP46
TP59TP58
TP52
TP53
TP54
TP55
TP60
C27
R91
R92
R93
R94
R95
R96
R97
M1
C77
DGND
DGND
DVDD
VSS
GPIO1
GPIO4
GPIO1
SPI_MOSI
SPI_CLK
DGND
SPI_MOSI
SPI_SEL
SPI_SEL
SPI_MISO
GPIO1
DVDD
DGND
EEPROM A0
DGND
GPIO2
GPIO4
VSDP
GPIO1
SPI_CLK
DGND
EEPROM A0
DGND
DVDD
VSDP
+9V
DGND
GPIO4
+5V
GPIO2
GPIO1
DGND
DGND
DVDD
DGND
DGND
DGND
DVDD
+5V
VSS
VSS
VDRIVE
RESET
SCLK
GPIO1
VDRIVE
CS_N
DGND
SPI_MISO
DVDD
+3.3V
GPIO1
DVDD
+3.3V
DVDD
DGND
+9V
SDI
SDO
DGND
1
2
3
4C
A
6
4
7
8
3
1
2
5
2
8 9
15
7
1
3
4
511
16
14
13
12
610
4 5
1 8
7
3
26
2
3
1
5
4
1
2
3
65
8
4
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
6
4
7
8
3
1
2
5
C
A
1
2
3
4
5
6
7
8
9
10
2
3
1
5
4
2
3
1
5
4
2
3
1
5
4
2
3
1
5
4
1
1 1 1
111
1
1
1
1
1
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SH8 SH9
SH10
SH11
SH12
SH13
SH14
SH15
SH16
Y
OE_N
A
VCC
GND
Y
OE_N
A
VCC
GND
Y
OE_N
A
VCC
GND
Y
OE_N
A
VCC
GND
VISO
GNDISO
VOA
VIB
VIC VID
VSEL
GNDISOGND1
RCOUT
VOD VOC
VOB
VIA
GND1
VDD1
VOA
VDD1
VIB VOB
VIA
VDD2
GND1 GND2
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELDSHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
IO
IO
Y
OE_N
A
VCC
GND
VSS
VCC
WP
A2
A1
A0
SCL SDA
IO
IO
IO
IO
IO
IN
NR
IN1 OUT OUT1
ERR_N
GNDSD_N
IO
IO
IN
NR
IN1 OUT OUT1
ERR_N
GNDSD_N
SENSE
PAD
VIN
PG
EN
NC GND
VOUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE

ANALOG FRONT-END
330
*
0.33UF
*
330
*
0.33UF
*
0.33UF
*
0.33UF
*
330
*
330
*
0.33UF
*
330
*
330
*
0.33UF
*
330
*
0.33UF
*
330
*
0.33UF
*
330
*
0.33UF
*
0.33UF
*
330
*
330
*
0.33UF
*
0.33UF
*
330
*
330
*330
*
0.33UF
*
0.33UF
*
330
*
330
*
0.33UF
*
0.33UF
*
330
*
330
*
0.33UF
*
0.33UF
*
3 4
-
-
AD7284
Transformer Isolated Config.
NTS
C
-
S. Bradshaw
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
APT2012LSECK/J3-PRV
VPIN0
CB8
CB7
CB6
CB5
CB4
CB3
CB2
CB1
VPIN1
VPIN2
VPIN3
VPIN4
VPIN5
VPIN6
VPIN7
VPIN8
CELL0
CELL1CELL3
CELL5
CELL7
CELL8
CELL2
CELL4
CELL6
1K
8
8
0
8
SQ2360EES-T1-GE3
0
0
0
0
0
0
0
1K
1K
SQ2360EES-T1-GE3
1
1
2
3
4
5
6
0
1K
3
4
1K
7
0
4
6
5
7
0
6
7
5
0
0
3
0
2
2
1
0
0
0
0
1K
1K
1K
SQ2360EES-T1-GE3
SQ2360EES-T1-GE3SQ2360EES-T1-GE3
0
1844304
M20-9990245
M20-9990245
0
SQ2361AEES-T1-GE3
SQ2361AEES-T1-GE3
SQ2361AEES-T1-GE3
51K
51K
51K
51K
51K
51K
51K
51K
P13
P10
P11
R121
R124
R120
R123
R125
R118
R122
R119
R117
R111
R102
R103
R104
R106
R107
R108
R105
R110
TP38
TP35
TP36
TP37
TP31
TP32
TP24
TP33
TP34
TP23
TP30
TP22
TP29
TP28
TP27
TP26
TP25
CELL0
CELL1TP18
TP16
TP10
TP7
TP19
TP17
TP15
R52 DS11
R54
Q8
R70
R74
C49
R78
C48
R49 DS10
R53
Q7
R77
C47
C46
R69
R73
R48
R51
DS9
Q6
R66
R72
C42
C45
R76
R46
R50
DS8
R68
Q5
R67
R75
C43
C44
R71
R64 C41
C40
R61
R43 DS7
R47
Q4
DS6
R42
R45
Q3
R63
R65
R62
C39
C38
R41 DS5
R44
Q2
R58
C37
R60
C36
R59
C35
Q1
DS4
C18
R39
R57
R40 R56
R55
C30
R29
R28
C29
CELL5
CB<8..1>
VSIN<8..0>
VSS
VSS
VSS
VPIN<8..0>
VSS
C2
CELL4
CELL0
CELL1
C6
C4
CELL7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C7
C5
C3
BAT-
CELL2
CELL3
CELL6
CELL8
C1
BAT+
11
10
9
8
7
6
5
4
3
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11
1
1
1
1
1
1
A C
2
1
3
A C
2
1
3
A C
2
1
3
A C
2
1
3
A C
2
1
3
AC
AC
AC
S
G
D
S
G
D
IO
IO
IN
OUT
IO
IO
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
S
G
D
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER DESIGN VIEW
REV DATE

THERMISTORS
4 4
-
-
AD7284
Transformer Isolated Config.
NTS
C
-
S. Bradshaw
0.1UF0.1UF0.1UF
0.1UF
33K
33K
33K
33K
VPAUX1 VPAUX4VPAUX3VPAUX2
TSW-101-08-F-D
0
0
0
33K33K
33K
0
2
1
3
4
33K
0
0R38
RT1
R36
RT2
RT3
RT4
R37
R35
P2 TP40 TP41 TP42TP39
C31
R31 R32 R33 R34
C32 C33 C34
C69 C70 C71 C72
R90R10
P12
VREFBUF
VSS
VPAUX<4..1>
VBUF
3
1
2
4
5
6
1 1 11
1
2
IO
IO
IO
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE