Atmel AT90S1200 User manual

1
Features
•Utilizes the AVR
®
RISC Architecture
•AVR - High-performance and Low-power RISC Architecture
– 89 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
•Data and Nonvolatile Program Memory
– 1K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In System Programming
•Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
•Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power Down Mode: <1 µA
•I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
•Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
•Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the
Rev. 0838E–04/99
8-bit
Microcontroller
with 1K bytes
In-System
Programmable
Flash
AT90S1200
Pin Configuration
(continued)

AT90S1200
2
AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump-
tion versus processing speed.
The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The AT90S1200 Block Diagram

AT90S1200
3
The architecture supports high level languages efficiently as well as extremely dense assembler code programs. The
AT90S1200 provides the following features: 1K bytes of In-System Programmable Flash, 64 bytes EEPROM, 15 general
purpose I/O lines, 32 general purpose working registers, internal and external interrupts, programmable Watchdog Timer
with internal oscillator, an SPI serial port for program downloading and two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the registers, timer/counter, watchdog and interrupt system to continue functioning.
The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next
external interrupt or hardware reset.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip In-System Program-
mable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a
conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable
Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The AT90S1200 AVR is supported with a full suite of program and system development tools including: macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1
also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The
Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and
are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S1200 as listed on page 27.
Port D (PD6..PD0)
Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.
As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins
are tri-stated when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S1200 as listed on page 31.
RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses
are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-
chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from
an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

AT90S1200
4
Figure 2. Oscillator Connections
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
Figure 3. External Clock Drive Configuration
On-chip RC Oscillator
An on-chip RC oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. If enabled, the
AT90S1200 can operate with no external components. A control bit - RCEN in the Flash Memory selects the on-chip RC
oscillator as the clock source when programmed (“0”). The AT90S1200 is normally shipped with this bit unprogrammed
(“1”). Parts with this bit programmed can be ordered as AT90S1200A. The RCEN-bit can be changed by parallel program-
ming only. When using the on-chip RC oscillator for serial program downloading, the RCEN bit must be programmed in
parallel programming mode first.
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC

AT90S1200
5
Figure 4. The AT90S1200 AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S1200 AVR RISC microcontroller architecture. The AVR
uses a Harvard architecture concept - with separate memories and buses for program and data memories. The program
memory is accessed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions
have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3 level deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory
maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.

AT90S1200
6
General Purpose Register File
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
Figure 5. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a
register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the
registers in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two regis-
ters or on a single register apply to the entire register file.
Register 30 also serves as an 8-bit pointer for indirect address of the register file.
ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories - arithmetic, logic and bit-functions.
In-System Programmable Flash Program Memory
The AT90S1200 contains 1K bytes on-chip In-System Programmable Flash memory for program storage. Since all instruc-
tions are single 16-bit words, the Flash is organized as 512 x 16. The Flash memory has an endurance of at least 1000
write/erase cycles.
The AT90S1200 Program Counter is 9-bit wide, thus addressing the 512 words Flash program memory.
See page 34 for a detailed description on Flash data downloading.
Program and Data Addressing Modes
The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the
different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruc-
tion word. To simplify, not all figures show the exact location of the addressing bits.
70
R0
R1
R2
General …
Purpose …
Working R28
Registers R29
R30 (Z-Register)
R31

AT90S1200
7
Register Direct, Single Register Rd
Figure 6. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Indirect
Figure 7. Indirect Register Addressing
The register accessed is the one pointed to by the Z-register (R30).

AT90S1200
8
Register Direct, Two Registers Rd and Rr
Figure 8. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
I/O Direct
Figure 9. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

AT90S1200
9
Relative Program Addressing, RJMP and RCALL
Figure 10. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Subroutine and Interrupt Hardware Stack
The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bit wide and
stores the Program Counter - PC - return address while subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels
1-2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from
stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack.
If more than 3 subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.
EEPROM Data Memory
The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described on page 23 specifying the EEPROM address register, the EEPROM data
register, and the EEPROM control register. For the SPI data downloading, see page 42 for a detailed description.
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 11 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.

AT90S1200
10
Figure 11. The Parallel Instruction Fetches and Instruction Executions
Figure 12 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 12. Single Cycle ALU Operation
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4

AT90S1200
11
I/O Memory
The I/O space definition of the AT90S1200 is shown in the following table:
Note: Reserved and unused locations are not shown in the table.
All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and
OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within
the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of
single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
The different I/O and peripherals control registers are explained in the following sections.
Table 1. The AT90S1200 I/O Space
Address Hex Name Function
$3F SREG Status REGister
$3B GIMSK General Interrupt MaSK register
$39 TIMSK Timer/Counter Interrupt MaSK register
$38 TIFR Timer/Counter Interrupt Flag register
$35 MCUCR MCU general Control Register
$33 TCCR0 Timer/Counter 0 Control Register
$32 TCNT0 Timer/Counter 0 (8-bit)
$21 WDTCR Watchdog Timer Control Register
$1E EEAR EEPROM Address Register
$1D EEDR EEPROM Data Register
$1C EECR EEPROM Control Register
$18 PORTB Data Register, Port B
$17 DDRB Data Direction Register, Port B
$16 PINB Input Pins, Port B
$12 PORTD Data Register, Port D
$11 DDRD Data Direction Register, Port D
$10 PIND Input Pins, Port D
$08 ACSR Analog Comparator Control and Status Register

AT90S1200
12
Status Register - SREG
The AVR status register - SREG - at I/O space location $3F is defined as:
•Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are
enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
•Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A
bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
•Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
•Bit 4 - S: Sign Bit, S = N⊕V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-
tion Set Description for detailed information.
•Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
•Bit 2 - N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set
Description for detailed information.
•Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description
for detailed information.
•Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Reset and Interrupt Handling
The AT90S1200 provides 3 different interrupt sources. These interrupts and the separate reset vector, each have a sepa-
rate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0 etc.’
Bit 76543210
$3F I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0

AT90S1200
13
The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp TIM0_OVF ; Timer0 Overflow Handler
$003 rjmp ANA_COMP ; Analog Comparator Handler
;
$004 MAIN: <instr> xxx ; Main program start
… … … …
Reset Sources
The AT90S1200 has three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the
program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 13 shows the reset logic. Table 3 defines the timing and electrical parameters
of the reset circuitry. Note that Power On Reset timing is clocked by the internal RC oscillator. Refer to characterization
data for RC oscillator frequency at other VCC voltages.
Figure 13. Reset Logic
Table 2. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET Hardware Pin, Power-on Reset and Watchdog Reset
2 $001 INT0 External Interrupt Request 0
4 $002 TIMER0, OVF0 Timer/Counter0 Overflow
5 $003 ANA_COMP Analog Comparator

AT90S1200
14
Notes: 1. The Power-On Reset will not work unless the supply voltage has been below Vpot (falling).
Power-on Reset
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 13, an internal timer
clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has
reached the Power-on Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 14).
Figure 14. MCU Start-Up, RESET Tied to VCC.
If the build-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By
holding the RESET pin low for a period after VCC has been applied, the Power-on Reset period can be extended. Refer to
Figure 15 for a timing example on this.
Table 3. Reset Characteristics (VCC = 5.0V)
Symbol Parameter Min Typ Max Units
VPOT(1) Power-On Reset Threshold Voltage (rising) 0.8 1.2 1.6 V
Power-On Reset Threshold Voltage (falling) 0.2 0.4 0.6 V
VRST Pin Threshold Voltage - - 0.85VCC V
tPOR Power-On Reset Period 2 3 4 ms
tTOUT Reset Delay Time-Out Period (The Time-out
period equals 16K WDT cycles. See “Typical
Characteristics” on page 48. for typical WDT
frequency at different voltages).
11 16 21 ms
VCC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST

AT90S1200
15
Figure 15. MCU Start-up, RESET Controlled Externally
External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even
if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has
expired.
Figure 16. External Reset During Operation
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 22 for details on operation of the Watchdog.
VCC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST
VCC
RESET
TIME-OUT
INTERNAL
RESET

AT90S1200
16
Figure 17. Watchdog Reset During Operation
Interrupt Handling
The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address
$3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user
software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is
executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-
ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
active.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
General Interrupt Mask Register - GIMSK
•Bit 7 - Res: Reserved bit
This bit is a reserved bit in the AT90S1200 and always read as zero.
•Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether
the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0 can be activated even if
the pin is configured as an output. See also page 17.
•Bits 5..0 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
Bit 7 6 5 4 3 2 1 0
$3B - INT0 - - - - - - GIMSK
Read/Write R R/W R R R R R R
Initial value 0 0 0 0 0 0 0 0

AT90S1200
17
Timer/Counter Interrupt Mask Register - TIMSK
•Bits 7..2 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
•Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•Bit 0 - Res: Reserved bit
This bits is a reserved bit in the AT90S1200 and always read as zero.
Timer/Counter Interrupt FLAG Register - TIFR
•Bits 7..2 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
•Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-
bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt
is executed.
•Bit 0 - Res: Reserved bit
This bits is a reserved bit in the AT90S1200 and always read as zero.
External Interrupts
The external interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or low level. This is
set up as described in the specification for the MCU control register - MCUCR. When INT0 is level triggered, the interrupt is
pending as long as INT0 is held low.
The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt.
The interrupt flag can not be directly accessed by the user. If an external edge triggered interrupt is suspected to be
pending, the flag can be cleared as follows.
1. Disable the external interrupt by clearing the INT0 flag in GIMSK.
2. Select level triggered interrupt.
3. Select desired interrupt edge.
4. Re-enable the external interrupt by setting INT0 in GIMSK.
Bit 7 6 5 4 3 2 1 0
$39 - - - - - - TOIE0 - TIMSK
Read/Write R R R R R R R/W R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$38 -- ----TOV0-TIFR
Read/Write R R R R R R R/W R
Initial value 0 0 0 0 0 0 0 0

AT90S1200
18
Interrupt Response Time
The interrupt execution response for all the enabled
AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the
interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this
4 clock cycle period, the Program Counter (9 bits) is pushed onto the Stack. The vector is normally a relative jump to the
interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this
instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits)
is popped back from the Stack and the I flag in SREG is set. When the
AVR exits from an interrupt, it will always return to
the main program and execute one more instruction before any pending interrupt is served.
Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than 3 nested subroutines and
interrupts are executed, only the most recent 3 return addresses are stored.
MCU Control Register - MCUCR
The MCU Control Register contains general microcontroller control bits for general MCU control functions.
•Bits 7, 6 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
•Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
•Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes” on
the following page.
•Bits 3, 2 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
•Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK register is set. The level and edges on the external INT0 pin that activate the interrupt are defined as:
Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register.
Otherwise an interrupt can occur when the bits are changed.
Bit 76543210
$35 - - SE SM - - ISC01 ISC00 MCUCR
Read/Write R R R/W R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 4. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
01Reserved
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.

AT90S1200
19
The value on the INT0 pin is sampled before detecting edges. If edge interrupt is selected, pulses with a duration longer
than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low
level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate
an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.
Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction makes the MCU enter the Idle Mode stopping the CPU but allow-
ing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from
external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the
Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the
Analog Comparator Control and Status register - ACSR. This will reduce power consumption in Idle Mode. When the MCU
wakes up from Idle mode, the CPU starts program execution immediately.
Power Down Mode
When the SM bit is set (one), the SLEEP instruction makes the MCU enter the Power Down Mode. In this mode, the exter-
nal oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external
reset, a watchdog reset (if enabled), an external level interrupt on INT0 can wake up the MCU.
Note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer
than the reset delay time-out period tTOUT. Otherwise, the device will not wake up.
Timer/Counter0
The AT90S1200 provides one general purpose 8-bit Timer/Counter. The Timer/Counter0 gets the prescaled clock from the
10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase or as a counter
with an external pin connection which triggers the counting.
Timer/Counter0 Prescaler
Figure 18 shows the general Timer/Counter0 prescaler.

AT90S1200
20
Figure 18. Timer/Counter0 Prescaler
The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the
Timer/Counter0, added selections as CK, external clock source and stop, can be selected as clock sources. Figure 19
shows the block diagram for Timer/Counter0.
Figure 19. Timer/Counter 0 Block Diagram
T0
TCK0
T0