Alinx ARTIX-7 FPGA User manual

ARTIX-7 FPGA
Development Board
AC7100B
System on Module

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Version Record
Version
Date
Release By
Description
Rev 1.0
2020-10-28
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................................2
Part 1: AC7100B Core Board Introduction........................................................4
Part 2: FPGA Chip................................................................................................. 6
Part 3: Active Differential Crystal........................................................................ 8
Part 3.1: 200Mhz Active Differential clock.................................................8
Part 3.2: 148.5Mhz Active Differential Crystal..........................................9
Part 4: DDR3 DRAM........................................................................................... 11
Part 5: QSPI Flash.............................................................................................. 15
Part 6: LED Light on Core Board......................................................................17
Part 7: Reset Button............................................................................................18
Part 8: JTAG Interface........................................................................................ 19
Part 9: Power Interface on the Core Board.................................................... 20
Part 10: Board to Board Connectors pin assignment................................... 21
Part 11: Power Supply........................................................................................ 28
Part 12: Structure Diagram................................................................................30

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Part 1: AC7100B Core Board Introduction
AC7100B (core board model, the same below) FPGA core board, it is
based on XILINX's ARTIX-7 series 100T XC7A100T-2FGG484I. It is a
high-performance core board with high speed, high bandwidth and high
capacity. It is suitable for high-speed data communication, video image
processing, high-speed data acquisition, etc.
This AC7100B core board uses two pieces of MICRON's
MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two
DDR chips are combined into a 32-bit data bus width, and the read/write data
bandwidth between FPGA and DDR3 is up to 25Gb; such a configuration can
meet the needs of high bandwidth data processing.
The AC7100B core board expands 180 standard IO ports of 3.3V level, 15
standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX
differential signals. For users who need a lot of IO, this core board will be a
good choice. Moreover, the routing between the FPGA chip and the interface is
equal length and differential processing, and the core board size is only 45*55
(mm), which is very suitable for secondary development.

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Figure 1-1: AC7100B Core Board (Front View)
Figure 1-2: AC7100B Core Board (Rear View)

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Part 2: FPGA Chip
As mentioned above, the FPGA model we use is XC7A100T-2FGG484I,
which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the
temperature grade is industry grade. This model is a FGG484 package with
484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below
Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series
Figure 2-2: FPGA chip on board
The main parameters of the FPGA chip XC7A100T are as follows
Name
Specific parameters
Logic Cells
101440
Slices
15850
CLB flip-flops
126800
Block RAM（kb）
4860

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DSP Slices
240
PCIe Gen2
1
XADC
1 XADC, 12bit, 1Mbps AD
GTP Transceiver
4 GTP, 6.6Gb/s max
Speed Grade
-2
Temperature Grade
Industrial
FPGA power supply system
Artix-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCO, VMGTAVCC and
VMGTAVTT. VCCINT is the FPGA core power supply pin, which needs to be connected
to 1.0V; VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V;
VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of
each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On
AC7100B FPGA core board, BANK34 and BANK35 need to be connected to
DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK
is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can
be changed by replacing the LDO chip. VMGTAVCC is the supply voltage of
the FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the
termination voltage of the GTP transceiver, connected to 1.2V.
The Artix-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If
VCCINT and VCCBRAM have the same voltage, they can be powered up at
the same time. The order of power outages is reversed. The power-up
sequence of the GTP transceiver is VCCINT, then VMGTAVCC, then
VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage, they can be
powered up at the same time. The power-off sequence is just the opposite of
the power-on sequence.

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Part 3: Active Differential Crystal
The AC7100B core board is equipped with two Sitime active differential
crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main
clock for FPGA and used to generate DDR3 control clock; the other is 125MHz,
model is SiT9102 -125MHz, reference clock input for GTP transceivers.
Part 3.1: 200Mhz Active Differential clock
G1 in Figure 3-1 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz
differential clock can be used to drive the user logic in the FPGA. Users can
configure the PLLs and DCMs inside the FPGA to generate clocks of different
frequencies.
Figure 3-1: 200Mhz Active Differential Crystal Schematic

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Figure 3-2: 200Mhz Active Differential Crystal on the Core Board
200Mhz Differential Clock Pin Assignment
Signal Name
FPGA PIN
SYS_CLK_P
R4
SYS_CLK_N
T4
Part 3.2: 148.5Mhz Active Differential Crystal
G2 in Figure 3-3 is the 148.5Mhz active differential crystal, which is the
reference input clock provided to the GTP module inside the FPGA. The crystal
output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and
MGTREFCLK0N (E6) of the FPGA.

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Figure 3-3: 148.5Mhz Active Differential Crystal Schematic
Figure 3-4: 1148.5Mhz Active Differential Crystal on the Core Board
125Mhz Differential Clock Pin Assignment
Net Name
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6

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Part 4: DDR3 DRAM
The FPGA core board AC7100B is equipped with two Micron 4Gbit
(512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed
of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly
connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
The specific configuration of DDR3 SDRAM is shown in Table 4-1.
Bit Number
Chip Model
Capacity
Factory
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
Table 4-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 4-1: The DDR3 DRAM Schematic

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Figure 4-2: The DDR3 on the Core Board
DDR3 DRAM pin assignment:
Net Name
FPGA PIN Name
FPGA P/N
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
E1
DDR3_DQS0_N
IO_L3N_T0_DQS_AD5N_35
D1
DDR3_DQS1_P
IO_L9P_T1_DQS_AD7P_35
K2
DDR3_DQS1_N
IO_L9N_T1_DQS_AD7N_35
J2
DDR3_DQS2_P
IO_L15P_T2_DQS_35
M1
DDR3_DQS2_N
IO_L15N_T2_DQS_35
L1
DDR3_DQS3_P
IO_L21P_T3_DQS_35
P5
DDR3_DQS3_N
IO_L21N_T3_DQS_35
P4
DDR3_DQ[0]
IO_L2P_T0_AD12P_35
C2
DDR3_DQ [1]
IO_L5P_T0_AD13P_35
G1
DDR3_DQ [2]
IO_L1N_T0_AD4N_35
A1
DDR3_DQ [3]
IO_L6P_T0_35
F3
DDR3_DQ [4]
IO_L2N_T0_AD12N_35
B2
DDR3_DQ [5]
IO_L5N_T0_AD13N_35
F1

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DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2
DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3

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DDR3_A[6]
IO_L5P_T0_34
W1
DDR3_A[7]
IO_L1P_T0_34
T1
DDR3_A[8]
IO_L2N_T0_34
V2
DDR3_A[9]
IO_L2P_T0_34
U2
DDR3_A[10]
IO_L5N_T0_34
Y1
DDR3_A[11]
IO_L4P_T0_34
W2
DDR3_A[12]
IO_L4N_T0_34
Y2
DDR3_A[13]
IO_L1N_T0_34
U1
DDR3_A[14]
IO_L6N_T0_VREF_34
V3
DDR3_BA[0]
IO_L9N_T1_DQS_34
AA3
DDR3_BA[1]
IO_L9P_T1_DQS_34
Y3
DDR3_BA[2]
IO_L11P_T1_SRCC_34
Y4
DDR3_S0
IO_L8P_T1_34
AB3
DDR3_RAS
IO_L12P_T1_MRCC_34
V4
DDR3_CAS
IO_L12N_T1_MRCC_34
W4
DDR3_WE
IO_L7P_T1_34
AA1
DDR3_ODT
IO_L14N_T2_SRCC_34
U5
DDR3_RESET
IO_L15P_T2_DQS_34
W6
DDR3_CLK_P
IO_L3P_T0_DQS_34
R3
DDR3_CLK_N
IO_L3N_T0_DQS_34
R2
DDR3_CKE
IO_L14P_T2_SRCC_34
T5

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Part 5: QSPI Flash
The FPGA core board AC7100B is equipped with one 128MBit QSPI
FLASH, and the model is W25Q256FVEI, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, core application
code and other user data files. The specific models and related parameters of
QSPI FLASH are shown in Table 5-1.
Position
Model
Capacity
Factory
U8
N25Q128
128M Bit
Numonyx
Table 5-1: QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 5-1 shows the hardware connection of QSPI Flash.
Figure 5-1: QSPI Flash Schematic

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QSPI Flash pin assignments:
Net Name
FPGA PIN Name
FPGA P/N
QSPI_CLK
CCLK_0
L12
QSPI_CS
IO_L6P_T0_FCS_B_14
T19
QSPI_DQ0
IO_L1P_T0_D00_MOSI_14
P22
QSPI_DQ1
IO_L1N_T0_D01_DIN_14
R22
QSPI_DQ2
IO_L2P_T0_D02_14
P21
QSPI_DQ3
IO_L2N_T0_D03_14
R21
Figure 5-2: QSPI on the Core Board

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Part 6: LED Light on Core Board
There are 3 red LED lights on the AC7100B FPGA core board, one of
which is the power indicator light (PWR), one is the configuration LED light
(DONE), and one is the user LED light. When the core board is powered, the
power indicator will illuminate; when the FPGA is configured, the configuration
LED will illuminate. The user LED light is connected to the IO of the BANK34,
the user can control the light on and off by the program. When the IO voltage
connected to the user LED is high, the user LED is off. When the connection IO
voltage is low, the user LED will be lit. The schematic diagram of the LED light
hardware connection is shown in Figure 6-1:
Figure 6-1: LED lights on core board Schematic
Figure 6-2: LED lights on the Core Board
User LEDs Pin Assignment
Signal Name
FPGA Pin Name
FPGA Pin Number
Description
LED1
IO_L15N_T2_DQS_34
W5
User LED

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Part 7: Reset Button
There is a reset button on the AC7100B FPGA core board. The reset
button is connected to the normal IO of the BANK34 of the FPGA chip. The
user can use this reset button to initialize the FPGA program. When the button
is pressed in the design, the signal voltage input to IO is low, and the reset
signal is valid; when the button is not pressed, the signal input to IO is high.
The schematic diagram of the reset button connection is shown in Figure 7-1:
Figure 7-1: Reset Button Schematic
Figure 7-2: Reset button on the Core Board
Reset button pin assignment
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
Description
RESET_N
IO_L17N_T2_34
T6
FPGA system reset

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Part 8: JTAG Interface
The JTAG test socket J1 is reserved on the AC7100B core board for JTAG
download and debugging when the core board is used alone. Figure 8-1 is the
schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND,
+3.3V these six signals.
Figure 8-1: JTAG Interface Schematic
The JTAG interface J1 on AC7100B FPGA core board uses a 6-pin
2.54mm pitch single-row test hole. If you need to use the JTAG connection to
debug on the core board, you need to solder a 6-pin single-row pin header.
Figure 8-2 shows the JTAG interface J1 on the AC7100B FPGA core board.
Figure 8-2 JTAG Interface on Core Board

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Part 9: Power Interface on the Core Board
In order to make the AC7100B FPGA core board work alone, the core
board is reserved with the 2PIN power interface (J3). When the user supplies
power to the core board through 2PIN power interface (J3), it cannot be
powered through the carrier board. Otherwise, current conflict may occur.
Figure 9-1: Power Interface on the Core Board