Atmel ATF15 DK3-U Series User manual

Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015
Introduction
The Atmel®ATF15xx-DK3-U Complex Programmable Logic Device (CPLD) Development/Programmer Kit is a
complete development system and an In-System Programming (ISP) programmer for the Atmel ATF15xx
Family of industry standard pin compatible CPLDs with Logic Doubling®features. This kit provides designers a
very quick and easy way to develop prototypes and evaluate new designs with an ATF15xx ISP CPLD. The
ATF15xx Family of ISP CPLDs includes the Atmel ATF15xxAS, ATF15xxASL, ATF15xxASV, and
ATF15xxASVL CPLDs. With the availability of the different socket adapter boards to support most of the
package types(1) offered in the ATF15xx Family of ISP CPLDs, this kit can be used as an ISP programmer to
program the ATF15xx ISP CPLDs in most of the available package types(1) through the industry standard JTAG
interface (IEEE 1149.1).
Kit Contents
CPLD Development/Programmer Board (ATF15xx-DK3)
44-pin TQFP Socket Adapter Board (ATF15xxDK3-SAA44)(2)
ATF15xx USB-based JTAG ISP Download Cable (ATDH1150USB or ATDH1150USB-K)
Two Atmel 44-pin TQFP Sample Devices
Device Support
The ATF15xx-DK3-U CPLD Development/Programmer Kit supports the following devices in all currently
available Atmel speed grades and packages (except the 100-PQFP):
ATF1502AS/ASL
ATF1504AS/ASL
ATF1508ASV/ASVL
ATF1502ASV
ATF1504ASV/ASVL
ATF1508AS/ASL
1. The socket adapter board is not offered for the 100-pin PQFP.
2. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other socket adapter boards are sold separately. See
“Hardware Description” section for more information on socket adapter board ordering codes.
ATF15xx-DK3-U
CPLD Development/Programmer Kit
USER GUIDE
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Table of Contents
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPLD Development/Programmer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Doubling CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ATF15xx ISP Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PLD Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CPLD Development/Programmer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7-segment Displays with Selectable Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LEDs with Selectable Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Push-button Switches with Selectable Jumpers for I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins . . . . . . . . . . . . . . . . . . . . . 9
2MHz Oscillator and Clock Selection Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCCIO and VCCINT Voltage Selection Jumpers and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ICCIO and ICCINT Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply Switch and Power LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply Jack and Power Supply Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JTAG ISP Connector and TDO Selection Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Socket Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Atmel ATF15xx ISP Download Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Atmel ProChip Designer Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Atmel WinCUPL Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Atmel ATMISP Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Atmel POF2JED Conversion Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Kit Features
CPLD Development/Programmer Board
10-pin JTAG-ISP Port
Regulated Power Supply Circuits for 9VDC Power Source
Selectable 5V, 3.3V, 2.5V, or 1.8V I/O Voltage Supply
Selectable 1.8V, 3.3V, or 5.0V Core Voltage Supply
44-pin TQFP Socket Adapter Board
Headers for I/O Pins of the ATF15xx Device
2MHz Crystal Oscillator
Four 7-segment LED Displays
Eight Individual LEDs
Eight Push-button Switches
Global Clear and Output Enable Push-button Switches
Current Measurement Jumpers
Logic Doubling CPLDs
ATF15xx ISP CPLD with Logic Doubling Architecture
ATF15xx ISP Download Cable
5V, 3.3V, 2.5V, or 1.8V ISP Download Cable for the Universal Serial Bus (USB) port of a PC
There are two versions of the ATF15xx USB ISP Download Cable; ATDH1150USB and
ATDH1150USB-K. They are built by two different vendors but have identical circuit design, and the
Atmel Ordering Code is ATDH1150USB. The ATDH1150USB-K is built by Kanda (www.kanda.com)
and it can be directly purchased from Kanda. More details are available online at
www.atmel.com/tools/ATDH1150USB.aspx.
PLD Development Software
The Atmel PLD development software tools are available online for PLD designer’s use of the ATF15xx
ISP CPLDs. Please reference the Overview document, “PLD Design Software Overview” available at:
http://www.atmel.com/images/atmel-3629-pld-design-software-overview.pdf
System Requirements
The minimum hardware and software required to program an ATF15xx ISP CPLD device designed
using the Atmel ProChip Designer Software on the CPLD Development/Programmer Board through
the Atmel ATMISP (ATF15xx CPLD ISP Software) are:
x86 or x64 Microprocessor-based Computer
Windows XP®or Windows 7
128-MByte RAM
500-MByte Free Hard Disk Space
Windows-supported Mouse
Available USB 1.1 / 2.0 / 3.0 Port
9VDC Power Supply with 500mA of Supply Current
SVGA Monitor (800 x 600 Resolution)
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Ordering Information
Note: 1. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other socket adapter boards are
sold separately. See “Hardware Description” section for more information on socket adapter board
ordering codes.
Hardware Description
CPLD Development/Programmer Board
The CPLD Development/Programmer and Socket Adapter Boards shown in the below figure contain
features that are useful for developing, prototyping, or evaluating ATF15xx CPLD designs. Features
that make this a very versatile starter/development kit and an ISP programmer for the ATF15xx family
of JTAG-ISP CPLDs include:
Figure 1. CPLD Development/Programmer Kit with 44-pin TQFP Socket Adapter Board
Atmel Part Number Description
ATF15xx-DK3-U CPLD Development/Programmer Kit (includes the ATF15xxDK3-SAA44(1) and
ATDH1150USB or ATDH1150USB-K)
ATF15xxDK3-SAA100 100-pin TQFP Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ44 44-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ84 84-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAA44(1) 44-pin TQFP Socket Adapter Board for DK3 Board
Push-button Switches
LEDs
7-segment Displays
2MHz Crystal Oscillator
5V, 3.3V, 2.5V, or 1.8V VCCIO Selector
1.8V, 3.3V, or 5.0V VCCINT Selector
JTAG ISP Port
Socket Adapters
Voltage
Regulators
GCLR
Switch
GOE
Switch
VccIO
Selector
VCCINT Selector
VccIO LED
VccINT LED
Power LED
Clock Selector
Power Switch
Oscillator
Power Supply Jack
Power Supply Header
JTAG Cascade Jumper
JTAG ISP Header
gu
la
7-Segment
Displays
ATF15xxDK3-SAA44
Socket Adapter Board
User I/O
Pin Headers
LEDs
Device Socket
Push-Button Switches
IccINT Jumper
IccIO Jumper
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7-segment Displays with Selectable Jumpers
The CPLD Development/Programmer Board contains four 7-segment displays which allow the
observation of the ATF15xx CPLD outputs. These four displays are labeled as DSP1, DSP2, DSP3,
and DSP4. The 7-segment displays have common anode LEDs with the common anode lines
connected to the VCCIO (I/O supply voltage for the CPLD) through a series of resistors with selectable
jumpers labeled as JPDSP1, JPDSP2, JPDSP3, and JPDSP4. These jumpers can be removed to
disable the displays by unconnecting the VCCIO to the displays. Individual cathode lines are connected
to the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Kit. To turn on a
particular segment, including the DOT of a display, the corresponding ATF15xx I/O pin connected to
this LED segment must be in a logic low state with the corresponding selectable jumper set; therefore,
the outputs of the ATF15xx device will require configuration for active-low outputs in the design file.
The displays work best at 2.5V VCCIO or higher.
Each segment of each display is hard-wired to one specific I/O pin of the ATF15xx device. For the
higher pin count devices (100-pin and larger), all seven segments and the DOT segments of the four
displays are connected to the I/O pins; however, for the lower pin count devices, only a subset of the
displays, first and fourth displays, are connected to the ATF15xx device’s I/O pins. Tables 1and 2
show the 7-segment display package connections to the ATF15xx device. The circuit schematic of the
displays and jumpers is shown in the figure below.
Figure 2. Circuit Diagram of 7-segment Display and Jumpers
a b c d e f
Vc1 Vc2
g
a
b
c
d
e
fg
DOT
DSP1
a b c d e f
Vc1 Vc2
g
a
b
c
d
e
fg
DOT
DSP2
a b c d e f
Vc1 Vc2
g
a
b
c
d
e
fg
DOT
DSP3
a b c d e f
Vc1 Vc2
g
a
b
c
d
e
fg
DOT
DSP4
RDSP21
RDSP22
RDSP23
RDSP24
RDSP25
RDSP26
RDSP27 RDSP31
RDSP32
RDSP33
RDSP34
RDSP35
RDSP36
RDSP37 RDSP41
RDSP42
RDSP43
RDSP44
RDSP45
RDSP46
RDSP47
VccIO
DOT2 DOT3 DOT4
RDOT2 RDOT3 RDOT4
D4A D4B D4C D4D D4E D4F D4G
JPDSP1
JPLED1
JPDSP2
JPLED2
JPDSP3
JPLED3
JPDSP4
JPLED4
RDOT1
RDSP11
RDSP12
RDSP13
RDSP14
RDSP15
RDSP16
RDSP17
DOT1
D1A D1B D1C D1D D1E D1F D1G D2A D2B D2C D2D D2E D2F D2G D3A D3B D3C D3D D3E D3F D3G
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Table 1. ATF15xx 44-pin Connections to 7-segment Displays
Table 2. ATF15xx 84-pin and 100-pin Connections to 7-segment Displays
44-pin TQFP 44-pin PLCC
DSP/Segment PLD Pin DSP/Segment PLD Pin DSP/Segment PLD Pin DSP/Segment PLD Pin
1/A 27 3/A NC 1/A 33 3/A NC
1/B 33 3/B NC 1/B 39 3/B NC
1/C 30 3/C NC 1/C 36 3/C NC
1/D 21 3/D NC 1/D 27 3/D NC
1/E 18 3/E NC 1/E 24 3/E NC
1/F 23 3/F NC 1/F 29 3/F NC
1/G 20 3/G NC 1/G 26 3/G NC
1/DOT 31 3/DOT NC 1/DOT 37 3/DOT NC
2/A NC 4/A 3 2/A NC 4/A 9
2/B NC 4/B 10 2/B NC 4/B 16
2/C NC 4/C 6 2/C NC 4/C 12
2/D NC 4/D 43 2/D NC 4/D 5
2/E NC 4/E 35 2/E NC 4/E 41
2/F NC 4/F 42 2/F NC 4/F 4
2/G NC 4/G 34 2/G NC 4/G 40
2/DOT NC 4/DOT 11 2/DOT NC 4/DOT 17
84-pin PLCC 100-pin TQFP
DSP/Segment PLD Pin DSP/Segment PLD Pin DSP/Segment PLD Pin DSP/Segment PLD Pin
1/A 68 3/A 22 1/A 67 3/A 13
1/B 74 3/B 28 1/B 71 3/B 19
1/C 70 3/C 25 1/C 69 3/C 16
1/D 63 3/D 21 1/D 61 3/D 8
1/E 58 3/E 16 1/E 57 3/E 83
1/F 65 3/F 17 1/F 64 3/F 6
1/G 61 3/G 12 1/G 60 3/G 92
1/DOT 73 3/DOT 29 1/DOT 75 3/DOT 20
2/A 52 4/A 5 2/A 52 4/A 100
2/B 57 4/B 10 2/B 54 4/B 94
2/C 55 4/C 8 2/C 47 4/C 97
2/D 48 4/D 79 2/D 41 4/D 81
2/E 41 4/E 76 2/E 46 4/E 76
2/F 50 4/F 77 2/F 40 4/F 80
2/G 45 4/G 75 2/G 45 4/G 79
2/DOT 56 4/DOT 11 2/DOT 56 4/DOT 93
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LEDs with Selectable Jumpers
The CPLD Development/Programmer Board has eight individual LEDs, which allow designers to
display the output signals from the user I/Os of the ATF15xx devices. These eight LEDs are labeled
LED1 to LED8 on the CPLD Development/Programmer Board. The cathode of each LED is connected
to Ground (GND) through a series resistor, while the anode of each LED is connected to a user I/O pin
of the CPLD through the JPL1/2/3/4/5/6/7/8 selectable jumper. These jumpers can be removed to
disable the LEDs by unconnecting the anodes of the LEDs to the I/O pins of the CPLD. The figure
below illustrates the circuit diagram of the LEDs with the selection jumpers.
To turn on a particular LED, the corresponding ATF15xx I/O pin connected to the LED must be in a
logic high state with the corresponding jumper set; therefore, the outputs of the ATF15xx device will
need to be configured as active high outputs. The LEDs work best at 2.5V VCCIO or higher.
The lower pin count devices (44-pin) only have four I/Os connected to LED1/2/3/4. For the higher
pin-count devices (100-pin and larger), all eight LEDs are connected to the I/Os of the device. Table 3
shows the different package connections of the CPLD I/Os to the LEDs.
Figure 3. Circuit Diagram of the LEDs and Jumpers
Table 3. ATF15xx Connections to LEDs
44-pin TQFP 44-pin PLCC 84-pin PLCC 100-pin TQFP
LED PLD Pin LED PLD Pin LED PLD Pin LED PLD Pin
LED1 28 LED1 34 LED1 69 LED1 68
LED2 25 LED2 31 LED2 67 LED2 65
LED3 22 LED3 28 LED3 64 LED3 63
LED4 19 LED4 25 LED4 60 LED4 58
LED5 27 LED5 17
LED6 24 LED6 14
LED7 18 LED7 10
LED8 15 LED8 9
LED8
GREEN
LED7
GREEN
LED6
GREEN
LED5
GREEN
JPL8
SIP2
JPL7
SIP2
JPL6
SIP2
JPL5
SIP2
RL8
330
RL7
330
RL6
330
RL5
330
LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8
LED4
GREEN
LED3
GREEN
LED2
GREEN
LED1
GREEN
JPL4
SIP2
JPL3
SIP2
JPL2
SIP2
JPL1
SIP2
RL4
330
RL3
330
RL2
330
RL1
330
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Push-button Switches with Selectable Jumpers for I/O Pins
The CPLD Development/Programmer Board contains eight push-button switches, which are
connected to the I/O pins of the CPLD. The switches send input logic signals to the user I/O pins of the
ATF15xx device. These switches are labeled SW1 to SW8 on the CPLD Development/Programmer
Board. One end of each input push-button switch is connected to VCCIO, while the other end of each
push-button switch is connected to a pull-down resistor and then connected to the specific I/O pin of
the CPLD through the JPS1/2/3/4/5/6/7/8 selectable jumper.
If any one of these switches is pressed and the corresponding jumper is set, the specific I/O pin of the
device will be driven to a logic high state by the output of switch circuit. Since each push-button switch
is also connected to a pull-down resistor, the input will have a logic low state if the switch is not pressed
with the corresponding jumper set. If the push-button jumper is not set, the corresponding pin will be
treated as an unconnected pin. Figure 4 is a circuit diagram of the push-button switch and selectable
jumper. Table 4 shows the connections of these eight push-button switches to the CPLD I/O pins in the
different package types.
Figure 4. Circuit Diagram of the Push-button Switches and Jumpers for the I/O Pins
Table 4. ATF15xx Connections to the I/O Pin Switches
44-pin TQFP 44-pin PLCC 84-pin PLCC 100-pin TQFP
Push Button PLD Pin Push Button PLD Pin Push Button PLD Pin Push Button PLD Pin
SW1 15 SW1 21 SW1 54 SW1 48
SW2 14 SW2 20 SW2 51 SW2 36
SW3 13 SW3 19 SW3 49 SW3 44
SW4 12 SW4 18 SW4 44 SW4 37
SW5 8 SW5 14 SW5 9 SW5 96
SW6 5 SW6 11 SW6 6 SW6 98
SW7 2 SW7 8 SW7 4 SW7 84
SW8 44 SW8 6 SW8 80 SW8 99
R19
1K
SW1
VCCIO
C13
0.001uF
JPS1
SIP2
SW1
R29
1K
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Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins
The CPLD Development/Programmer Board contains two push-button switches for the Global Clear
(GCLR) and Output Enable (OE1) pins of the CPLD. The switches control the logic states of the OE1
and GCLR inputs of the ATF15xx devices. These switches are labeled SW-GCLR and SW-GOE1 on
the board. One end of the SW-GCLR input push-button switch is connected to GND. The other end of
the push-button switch is connected to a pull-up resistor to VCCIO, and then connected to the GCLR
dedicated input pin of the ATF15xx device. It is intended to be used as an active-low reset signal to
reset the registers in the ATF15xx device with the JPGCLR selectable jumper set. Similarly, one end of
the SW-GOE1 input push-button switch is connected to GND. The other end of the push-button switch
is connected to a pull-up resistor to VCCIO, and then connected to the OE1 dedicated input pin of the
ATF15xx device. It is intended to be used as an active-low output enable signal to control the
enabling/disabling of the tri-state output buffers in the ATF15xx with the JPGOE selectable jumper set.
Figure 5 is the circuit diagram of the push-button switches and the jumpers for the GCLR and OE1
pins.
If any of these push-button switches is pressed and the corresponding jumper is set, the specific I/O of
the CPLD will be driven to a logic low state. Since each push-button is also connected to a pull-up
resistor, the corresponding CPLD input will have a logic high state if the push-button switch is not
pressed with the corresponding selectable jumper set. If the selectable jumper is not set, the
corresponding dedicated input pin of the CPLD can be considered a No Connect (NC) pin. Table 5
shows the pin numbers of the GCLR and OE1 dedicated input pins of the ATF15xx devices in all
available package types.
Figure 5. Circuit Diagram of Push-button Switches and Selectable Jumpers for GCLR and OE1
Table 5. Pin Numbers of GCLR and OE1
44-pin TQFP 44-pin PLCC 84-pin PLCC 100-pin TQFP
GCLR 39 1 1 89
OE1 38 44 84 88
GCLR
R15
1K
R16
1K
VccIO
JPGCLR JPGOE GOE
C7
0.001uF
C8
0.001uF
SW-GCLR
SW-GCLR
SW-GOE
SW-GOE
R37
1K
R38
1K
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ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015
10
2MHz Oscillator and Clock Selection Jumper
The Clock Selection Jumper labeled JP-GCLK on the CPLD Development/Programmer Board is a
two-position jumper that allows the users to select which GCLK dedicated input pin (either GCLK1 or
GCLK2) of the ATF15xx device should be connected to the output of the 2MHz oscillator. In addition,
the jumper can be removed to allow an external clock source to be connected to GCLK1 and/or GCLK2
of the ATF15xx device. Figure 6 is an illustration of the circuit diagram of the oscillator and selection
jumper. Table 6 shows the pin numbers for the GCLK1 and GCLK2 dedicated input pins of the
ATF15xx device in all the different available package types.
Figure 6. Circuit Diagram of Oscillator and Clock Selection Jumper
If GCLK1 jumper is set, the jumper will be located toward the side of the board. On the other
hand, if GCLK2 jumper is set, the jumper will be located toward the middle of the board.
Table 6. Pin Numbers of GCLK1 and GCLK2
44-pin TQFP 44-pin PLCC 84-pin PLCC 100-pin TQFP
GCLK1 37 43 83 87
GCLK2 40 2 2 90
1 4
2 3
OSC
2MHZ
GCLK2 GCLK1
1 2 3
JPGCLK
R18
1K
R17
1K
VccOSC
C21
0.1uF
R39
100
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