Atmel AVR ATtiny15L Owner's manual

1
Features
•High-performance, Low-power AVR®8-bit Microcontroller
•Advanced RISC Architecture
– 90 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Fully Static Operation
•Nonvolatile Program and Data Memories
– 1K bytes In-System Programmable Flash Program Memory
Endurance: 1,000 Write/Erase Cycles
– 64 bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
•Peripheral Features
– Interrupt and Wakeup on Pin Change
– Two 8-bit Timer/Counters with Separate Prescalers
– One150 kHz, 8-bit High-speed PWM Output
– 4 channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20x
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
•Special Microcontroller Features
– In-System Programmable via SPI Port
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal, Calibrated 1.6 MHz Tuneable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter
– External and Internal Interrupt Sources
– Low-power Idle and Power-down Modes
•I/O and Packages
– 8-pin PDIP/SOIC: 6 Programmable I/O Lines
•Operating Voltages
– 2.7V - 5.5V (ATtiny15L)
•Internal 1.6 MHz System Clock
•Commercial and Industrial Temperature Ranges
Description
The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single-clock cycle, the ATtiny15L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Rev. 1187B–03/00
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny15L
Advance
Information
Pin Configuration
1
2
3
4
8
7
6
5
(RESET/ADC0) PB5
(ADC3) PB4
(ADC2) PB3
GND
VCC
PB2 (ADC1/SCK/T0/INT0)
PB1 (AIN1/MISO/OC1A)
PB0 (AIN0/AREF/MOSI)
PDIP/SOIC
(continued)

ATtiny15L
2
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The ATtiny15L provides 1K bytes of Flash, 64 bytes EEPROM, 6 general-purpose I/O lines, 32 general-purpose working
registers, two 8-bit timer/counters, one with high speed PWM output, internal oscillators, internal and external interrupts,
programmable Watchdog Timer, 4-channel 10-bit Analog to Digital Converter with one differential voltage input with
optional 20x gain, and three software-selectable power-saving modes. The Idle mode stops the CPU while allowing the
ADC, analog comparator, timer/counters and interrupt system to continue functioning. The ADC Noise Reduction mode
facilitates high-accuracy ADC measurements by stopping the CPU while allowing the ADC to continue functioning. The
Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next
interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny15L to be highly responsive
to external events, still featuring the lowest power consumption while in the power-saving modes.
The device is manufactured using Atmel’s high density nonvolatile memory technology. By combining an enhanced RISC
8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny15L is a powerful microcontroller that provides a highly-flexible
and cost-efficient solution to many embedded control applications. The peripheral features make the ATtiny15L particularly
suited for battery chargers, lighting ballasts, and all kinds of intelligent sensor applications.
The ATtiny15L AVR is supported with a full suite of program and system development tools including macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.

ATtiny15L
3
Block Diagram
Figure 1. The ATtiny15L Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
HARDWARE
STACK
MCU CONTROL
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
INSTRUCTION
DECODER
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PROGRAMMING
LOGIC
TIMING AND
CONTROL
TIMER/
COUNTER1
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORT B DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
+
-
ANALOG
COMPARATOR
8-BIT DATABUS
Z
ISP MODULE
INTERRUPT
UNIT
DATA
EEPROM
INTERNAL
OSCILLATOR
TUNABLE
ANALOG MUX ADC

ATtiny15L
4
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or open-
drain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is external Reset. The
port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port B also accommodates analog I/O pins. The Port B pins with alternate functions are shown in Table 1:
Analog Pins
Up to four analog inputs can be selected as inputs to Analog to digital converter (ADC).
Internal Oscillators
The internal oscillator provides a clock rate of nominally 1.6 MHz for the system clock CK. Due to large initial variation
(0.8 MHz -1.6 MHz) of the internal oscillator, a tuning capability is built in. Through an eight bit control register OSCCAL,
the system clock rate can be tuned with less than 1% steps of the nominal clock.
There is an internal PLL that provides a 16x clock rate locked to the system clock (CK) for the use of the Peripheral
Timer/Counter1. The nominal frequency of this peripheral clock, PCK, is 25.6 MHz.
Table 1. Port B Alternate Functions
Port Pin Alternate Function
PB0
MOSI (Data Input Line for Memory Downloading)
AREF (ADC Voltage Reference)
AIN0 (Analog Comparator Positive Input)
PB1
MISO (Data Output Line for Memory Downloading)
OC1A (Timer/Counter PWM Output)
AIN1 (Analog Comparator Negative Input)
PB2
SCK (Serial Clock Input for Serial Programming)
INT0 (External Interrupt0 Input)
ADC1 (ADC Input Channel 1)
T0 (Timer/Counter0 External Counter Input)
PB3 ADC2 (ADC Input Channel 2)
PB4 ADC3 (ADC Input Channel 3)
PB5 RESET (External Reset Pin)
ADC0 (ADC Input Channel 0)

ATtiny15L
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ATtiny15L Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access
time. This means that during one single-clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file –in one clock
cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and
can address the register file, IO file, and the Flash program memory.
Figure 2. The ATtiny15L AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single-register
operations are also executed in the ALU. Figure 2 shows the ATtiny15L AVR RISC microcontroller architecture. The AVR
uses a Harvard architecture concept with separate memories and buses for program and data memories. The program
memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have
a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3 level deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, and
other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
512 x 16
Program
FLASH
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Direct Addressing
Status
and Test
Control
Registrers
Interrupt
Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
I/O Lines
Data Bus 8-bit
SPI Unit
ADC
64 x 8
EEPROM

ATtiny15L
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The General-purpose Register File
Figure 3 shows the structure of the 32 general-purpose registers in the CPU.
Figure 3. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a
register and the LDI instruction for load-immediate constant data. These instructions apply to the second half of the regis-
ters in the register file –R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or
on a single-register apply to the entire register file.
Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and register file access.
When the register file is accessed, the contents of R31 is discarded by the CPU.
The ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a
single-clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories –arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature a hard-
ware multiplier in the arithmetic part of the ALU.
The Flash Program Memory
The ATtiny15L contains 1K bytes on-chip, in-system programmable Flash memory for program storage. Since all instruc-
tions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least
1000 write/erase cycles.
The ATtiny15L Program Counter is 9-bit wide, thus addressing the 512 words Flash program memory.
See page 48 for a detailed description on Flash memory programming.
The Program and Data Addressing Modes
The ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the
various addressing modes supported in the ATtiny15L. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
70
R0
R1
R2
General …
Purpose …
Working R28
Registers R29
R30 (Z-Register low byte)R3
R31 (Z-Register high byte)

ATtiny15L
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Register Direct, Single-register Rd
Figure 4. Direct Single-register Addressing
The operand is contained in register d (Rd).
Register Indirect
Figure 5. Indirect Register Addressing
The register accessed is the one pointed to by the Z-register low byte (R30).
Register Direct, Two Registers Rd and Rr
Figure 6. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

ATtiny15L
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I/O Direct
Figure 7. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Relative Program Addressing, RJMP and RCALL
Figure 8. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Constant Addressing Using the LPM Instruction
Figure 9. Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), and LSB selects
low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
+1
$1FF

ATtiny15L
9
Subroutine and Interrupt Hardware Stack
The ATtiny15L uses a 3-level deep hardware stack for subroutines and interrupts. The hardware stack is 9-bit wide and
stores the Program Counter (PC) return address while subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1-2
are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from
stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack.
If more than 3 subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.
Pushing four return addresses A1, A2, A3, and A4 followed by four subroutine or interrupt returns, will pop A4, A3, A2, and
once more A2 from the hardware stack.
The EEPROM Data Memory
The ATtiny15L contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes
can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described on page 25, specifying the EEPROM Address Register, the EEPROM Data Register,
and the EEPROM Control Register.
Memory Access and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 10 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 10. The Parallel Instruction Fetches and Instruction Executions
Figure 11 shows the internal timing concept for the register file. In a single-clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 11. Single Cycle ALU Operation
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4

ATtiny15L
10
I/O Memory
The I/O space definition of the ATtiny15L is shown in the following table:
Note: Reserved and unused locations are not shown in the table.
All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT
instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the
address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin-
gle bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. For
compatibility with future devices, reserved bits should be written zero if accessed. Reserved I/O memory addresses should
never be written.
The I/O and peripheral control registers are explained in the following sections.
Table 2. ATtiny15L I/O Space
Address Hex Name Function
$3F SREG Status Register
$3B GIMSK General Interrupt Mask Register
$3A GIFR General Interrupt Flag Register
$39 TIMSK Timer/Counter Interrupt Mask Register
$38 TIFR Timer/Counter Interrupt Flag Register
$35 MCUCR MCU Control Register
$34 MCUSR MCU Status Register
$33 TCCR0 Timer/Counter0 Control Register
$32 TCNT0 Timer/Counter0 (8-bit)
$31 OSCCAL Oscillator Calibration Register
$30 TCCR1 Timer/Counter1 Control Register
$2F TCNT1 Timer/Counter1 (8-bit)
$2E OCR1A Timer/Counter1 Output Compare Register A
$2D OCR1B Timer/Counter1 Output Compare Register B
$2C SFIOR Special Function I/O Register
$21 WDTCR Watchdog Timer Control Register
$1E EEAR EEPROM Address Register
$1D EEDR EEPROM Data Register
$1C EECR EEPROM Control Register
$18 PORTB Data Register, Port B
$17 DDRB Data Direction Register, Port B
$16 PINB Input Pins, Port B
$08 ACSR Analog Comparator Control and Status Register
$07 ADMUX ADC Multiplexer Select Register
$06 ADCSR ADC Control and Status Register
$05 ADCH ADC Data Register High
$04 ADCL ADC Data Register Low