NXP Semiconductors LPC2880 User manual

UM10208
LPC2880/LPC2888 User manual
Rev. 02 — 1 June 2007 User manual
Document information
Info Content
Keywords LPC2880, LPC2888, LPC288x, ARM, ARM7, embedded, 32-bit,
microcontroller, USB 2.0, USB HS
Abstract LPC288x User manual

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User manual Rev. 02 — 1 June 2007 2 of 362
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10208
LPC288x User manual
Revision history
Rev Date Description
02 20070601 Various editorial and content updates to the following chapters:
•The format of this user manual has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Universal Asynchronous Receiver-Transmitter (UART):
The UART baud rate is derived from the UART baud rate clock (UART_CLK).
•External Memory Controller (EMC):
SDRAM Usage notes added (Section 8–12).
•Clock Generation Unit (CGU) and power control:
CGU Usage notes added including a section on how to achieve low-power operation
(Section 7–5).
•USB Device controller:
–DMA mode transfer section was improved (Section 17–6.4).
–Endpoint configuration table added (Table 17–232).
–Section 17–8.6 on interrupt handling was further elaborated.
•I/O pinning:
Section 25–2.5 “Pin structure”added.
•DC-to-DC converter:
Section 6–2 “General operation”was improved.
•SD/MMC interface:
Status register contents were corrected (Table 23–345). Descriptions on bits 17 and 19
were swapped.
•General Purpose DMA controller (GPDMA):
Register locations for registers DMA3EXTEN and DMA5EXTEN were corrected
(Table 15–196).
•Dual-channel 16-bit Digital-to-Analog Converter (DDAC):
–Description of Dual DAC was improved.
–Section 22–6.2 “Power-up procedure”was corrected.
•Dual-channel 16-bit Analog-to-Digital converter (DADC):
Bits 0-7 of Decimator Control register were corrected (Table 21–306).
•I2S output module (DAO):
DAO pin description was corrected (Table 20–292).
•Boot process:
Part Identification register (Table 3–4) was moved to this chapter from chapter “System
control ”.
•Chapter “System control” removed.
•Chapter “General Purpose I/O (GPIO)” added.
01 20060905 LPC288x User manual

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1. Introduction
The LPC288x is an ARM7-based microcontroller for portable applications requiring low
power and high performance. It includes a USB 2.0 High Speed device interface, an
external memory interface that can interface to SDRAM and Flash, an MMC/SD memory
card interface, A/D and D/A converters, and serial interfaces including UART, I2C, and I2S.
Architectural enhancements like multi-channel DMA, processor cache, simultaneous
operations on multiple internal buses, and flexible clock generation help ensure that the
LPC288x can handle more demanding applications than many competing devices. The
chip can be powered from a single battery, from the USB, or from regulated 1.8 and 3.3V.
2. Features
•ARM7TDMI processor with 8 kB cache operating at up to 60 MHz
•1 MB on-chip Flash Program Memory with 128-bit access for high performance
•64 kB SRAM
•32 kB ROM
•On-chip DC-DC converter can generate all required voltages from a single battery or
from USB power
•Multiple internal buses allow simultaneous GP DMA, USB DMA, and program
execution from on-chip Flash without contention.
•External memory controller supports Flash, SRAM, ROM, and SDRAM.
•Advanced Vectored Interrupt Controller, supporting up to 30 vectored interrupts
•Innovative Event Router allows interrupt, power-up, and clock-start capabilities from
up to 105 sources
•Multi-channel GP DMA controller that can be used with most on-chip peripherals as
well as for memory-to-memory transfers.
•Serial Interfaces:
–Hi-Speed or Full-speed USB 2.0 Device (480 or 12 Mbits/s) with on-chip PHYsical
layer
–UART with fractional baud rate generation, flow control, IrDA support, and FIFOs
–I2C Interface
–I2S (Inter-IC Sound) interface for independent stereo digital audio input and output
•Secure Digital (SD) / MultiMediaCard (MMC) memory card interface
•10 bit A/D Converter with 5-channel input multiplexing
•16 bit stereo A/D and D/A converters with gain control and optional DMA
•Advanced clock generation and power control reduce power consumption
•Two 32-bit Timers with selectable prescalers
•8-bit LCD interface bus
•Real Time Clock can be clocked by 32 kHz oscillator or another source
•Watchdog Timer with interrupt and/or reset capabilities
UM10208
Chapter 1: Introductory information
Rev. 02 — 1 June 2007 User manual

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User manual Rev. 02 — 1 June 2007 4 of 362
NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
•180 pin TFBGA package
3. Applications
•Portable, battery powered devices
•USB devices
4. Architectural overview
The LPC288x includes an ARM7TDMI CPU with an 8kB cache, an AMBA Advanced
High-performance Bus (AHB) interfacing to high speed on-chip peripherals and internal
and external memory, and four AMBA Advanced Peripheral Buses (APBs) for connection
to other on-chip peripheral functions. The LPC288x permanently configures the
ARM7TDMI processor for little-endian byte order.
The LPC288x includes a multi-layer AHB and four separate APBs, in order to minimize
interference between the USB controller, other DMA operations, and processor activity.
Bus masters include the ARM7 itself, the USB block, and the general purpose DMA
controller.
Lower speed peripheral functions are connected to the APBs. Four AHB-to-APB bridges
interface the APBs to the AHB.
5. ARM7TDMI processor
The ARM7TDMI is a general purpose 32 bit microprocessor that offers high performance
and very low power consumption. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, and the instruction set and related decode mechanism
are much simpler than those of microprogrammed Complex Instruction Set Computers.
This simplicity results in a high instruction throughput and impressive real-time interrupt
response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI processor has two instruction sets:
•The standard 32 bit ARM instruction set.
•A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.

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NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
THUMB code be as little as 65% of the code size of ARM, and 160% of the performance
of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI processor is described in detail on the ARM website.
6. On-Chip flash memory system
The LPC2888 includes a 1 MB Flash memory system. This memory may be used for both
code and data storage. Programming of the Flash memory may be accomplished in
several ways. It may be programmed In System via the USB port. The application
program may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage and field firmware upgrades.
The Flash is 128 bits wide and includes buffering to allow 3 out of 4 sequential read
operations to operate without wait states.
7. On-Chip Static RAM
The LPC288x includes 64 kB of static RAM that may be used for code and/or data
storage.
8. On-Chip ROM
The LPC288x includes 32 kB of Read Only Memory that may be used for code and/or
constant storage. Execution begins in on-chip ROM after a Reset.
Philips provides a standard boot code in this ROM that reads the state of the Mode inputs
and accordingly does one of the following:
1. starts execution in internal Flash,
2. starts execution in external memory,
3. performs a hardware self-test, or
4. downloads code from the USB interface into on-chip RAM and transfers control to the
downloaded code.

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User manual Rev. 02 — 1 June 2007 6 of 362
NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
9. Block diagram
(1) LPC2888 only
Fig 1. LPC288x block diagram
MULTI-LAYER AHB
AIN[4:0]
Px.y
WATCHDOG
TIMER
SD/MMC CARD
INTERFACE
GENERAL
PURPOSE I/O
SYSTEM
CONTROL
EVENT
ROUTER
register
interface
DC-TO-DC
CONVERTER
START,
STOP
SCL, SDA
MCLK
MD[3:0], MCMD
DATI
BCKI, WSI
AOUTL,
AOUTR
AINL, AINR
DATO
BCKO, DCLKO,
WSO
+1.5 V
or +5 V
3.3 V,
1.8 V
XTALI
XTALO
X32I
X32O
CLOCK
GENERATION
UNIT
OSCILLATOR
AND PLLs
ARM7TDMI-S
JTAG DEBUG
INTERFACE
8 kB CACHE
JTAG_TRST JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_SEL
FLASH
INTERFACE
1 MB
FLASH(1)
SRAM
INTERFACE
64 kB
SRAM
ROM
INTERFACE
BOOT
ROM
REAL-TIME
CLOCK
OSCILLATOR
FIFO FIFO I2S-BUS
INPUT
FIFO I2S-BUS
OUTPUT
DUAL ANALOG
INPUT
FIFO
DUAL ANALOG
OUTPUT
EXTERNAL
MEMORY
CONTROLLER
A[20:0],
D[15:0],
etc.
VECTORED
INTERRUPT
CONTROLLER
HS USB
WITH DMA
DP, DM, VBUS,
RREF, CONNECT
LPC2880/2888
AHB TO APB
BRIDGE 0
AHB TO APB
BRIDGE 3
AHB TO APB
BRIDGE 1
AHB TO APB
BRIDGE 2
GP DMA
CONTROLLER
10-BIT A/D
CONVERTER
UART WITH
IrDA
TXD, RTS
RXD, CTS
LCD
INTERFACE LCD bus
I2C-BUS
INTERFACE
32-BIT
TIMER 0
32-BIT
TIMER 1
002aac296

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User manual Rev. 02 — 1 June 2007 7 of 362
1. Memory map and peripheral addressing
ARM processors have a single 4 GB address space. The following table shows how this
space is used on the LPC288x. Addresses not shown in this table are not used.
1.1 Memory map
The LPC2880/2888 memory map incorporates several distinct regions, as shown in
Figure 2–2. When an application is running, the CPU interrupt vectors are remapped to
allow them to reside in on-chip SRAM.
UM10208
Chapter 2: LPC2800 Memory addressing
Rev. 02 — 1 June 2007 User manual
Table 1. LPC288x memory usage
Address range General use Address range details and description
0x0000 0000 to
0x0FFF FFFF Cacheable area 0x0020 0000 - 0x0020 7FFF Internal ROM (32 kB)
0x0040 0000 - 0x0040 FFFF Internal RAM (64 kB)
(other addresses) Software can map other internal and external
memory into this area, to improve its effective
access time.
0x1000 0000 to
0x1FFF FFFF Internal Memory 0x1040 0000 - 0x104F FFFF Flash (1 MB)
0x2000 0000 to
0x5FFF FFFF External Memory 0x2000 0000 - 0x201F FFFF and 0x4000 0000 - 0x401F FFFF Static memory bank 0, 2 MB, STCS0
0x2400 0000 - 0x241F FFFF and
0x4400 0000 - 0x441F FFFF Static memory bank 1, 2 MB, STCS1
0x2800 0000 - 0x281F FFFF and
0x4800 0000 - 0x481F FFFF Static memory bank 2, 2 MB, STCS2
0x3000 0000-0x33FF FFFFand
0x5000 0000 - 0x53FF FFFF Dynamic memory bank 0, 64 MB
0x8000 0000 to
0x8FFF FFFF Peripherals See Table 2–2 Includes AHB Peripherals and 4 APBs

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NXP Semiconductors UM10208
Chapter 2: LPC2800 Memory mapping
Fig 2. Memory map
remapped area
0x0000 0000
0.0 GB
2.0 GB
4.0 GB
0x0FFF FFFF
0x2000 0000
0x8000 0000
0x7FFF FFFF
0x1FFF FFFF
0xFFFF FFFF
0x1000 0000
internal memory
external memory
(first instance)
peripherals
static memory bank 2, 2 MB 0x2800 0000 to 0x281F FFFF
reserved 0x2420 0000 to 0x27FF FFFF
dynamic memory bank 0, 64 MB 0x3000 0000 to 0x33FF FFFF
exception vectors 0x0000 0000 to 0x0000 001F
static memory bank 1, 2 MB 0x2400 0000 to 0x241F FFFF
static memory bank 0, 2 MB 0x2000 0000 to 0x201F FFFF
reserved 0x1050 0000 to 0x1FFF FFFF
internal ROM (32 kB) 0x0020 0000 to 0x0020 7FFF
reserved 0x0050 0000 to 0x0FFF FFFF
internal RAM (64 kB) 0x0040 0000 to 0x0040 FFFF
reserved 0x2020 0000 to 0x23FF FFFF
internal flash (1 MB) 0x1040 0000 to 0x104F FFFF
reserved 0x1000 0000 to 0x0000 003F
reserved 0x2820 0000 to 0x2FFF FFFF
reserved 0x3400 0000 to 0x3FFF FFFF
static memory bank 2, 2 MB 0x4800 0000 to 0x481F FFFF
reserved 0x4420 0000 to 0x47FF FFFF
dynamic memory bank 0, 64 MB 0x5000 0000 to 0x53FF FFFF
static memory bank 1, 2 MB 0x4400 0000 to 0x441F FFFF
static memory bank 0, 2 MB 0x4000 0000 to 0x401F FFFF
reserved 0x4020 0000 to 0x43FF FFFF
reserved 0x4820 0000 to 0x4FFF FFFF
reserved 0x5400 0000 to 0x7FFF FFFF
0x4000 0000
0x3FFF FFFF
0x9000 0000
0x8FFF FFFF
external memory
(second instance)
1.0 GB
includes AHB and 4 APB buses 0x8000 0000 to 0x8FFF FFFF
reserved 0x9000 0000 to 0xFFFF FFFF
002aac240

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NXP Semiconductors UM10208
Chapter 2: LPC2800 Memory mapping
2. Peripheral addressing
Peripheral devices on the LPC288x are distributed among the ARM High-speed Bus
(AHB) and four ARM Peripheral Buses (APBs). The following table indicates which bus
each device is connected to. Addresses not shown in this table are not used.
Table 2. LPC288x Peripheral devices
Address allocation Bus Register addresses (inclusive) Peripheral device
0x8000 0000 - 0x8000 1FFF APB0 0x8000 0000 - 0x8000 1C00 Event Router
0x8000 2000 - 0x8000 23FF APB0 0x8000 2000 - 0x8002 027C Real Time Clock (RTC)
0x8000 2400 - 0x8000 27FF APB0 0x8000 2400 - 0x8000 2430 10 bit Analog to Digital Converter (ADC)
0x8000 2800 - 0x8000 2BFF APB0 0x8000 2800 - 0x8000 283C Watchdog Timer (WDT)
0x8000 3000 - 0x8000 3FFF APB0 0x8000 3000 - 0x8000 31E8 I/O Configuration (IOCONF)
0x8000 4000 - 0x8000 4BFF APB0 0x8000 4000 - 0x8000 443C Clock Generation Unit (CGU) Switchbox
0x8000 4C00 - 0x8000 4FFF APB0 0x8000 4C00 - 0x8000 4CFC Clock Generation Unit (CGU)
0x8000 5000 - 0x8000 53FF APB0 0x8000 5000 - 0x8000 507C System Configuration Registers
0x8000 8000 - 0x8000 8FFF AHB 0x8000 8000 - 0x8000 8258 External Memory Controller (EMC)
0x8002 0000 - 0x8000 03FF APB1 0x8002 0000 - 0x8002 0010 Timer 0
0x8002 0400 - 0x8000 07FF APB1 0x8002 0400 - 0x8002 0410 Timer 1
0x8002 0800 - 0x8002 0BFF APB1 0x8002 0800 - 0x8002 082C I2C Controller
0x8004 0000 - 0x8004 1FFF AHB 0x8004 0000 - 0x8004 10B4 USB Controller
0x8010 0000 - 0x8010 0FFF APB2 0x8010 0000 - 0x8010 00BC Secure Digital / Multimedia Card
Interface (SD/MCI)
0x8010 1000 - 0x8010 1FFF APB2 0x8010 1000 - 0x8010 1034
0x8010 1FD4 - 0x8010 1FEC UART
0x8010 2000 - 0x8010 2FFF APB2 0x8010 2000 - 0x8010 201C
0x8010 2FD8 - 0x8010 2FEC Flash Programming Interface
0x8010 3000 - 0x8010 33FF APB2 0x8010 3000 - 0x8010 3080 LCD Interface
0x8010 3800 - 0x8010 3FFF APB2 0x8010 3800 - 0x8010 38FC
0x8010 3A00 - 0x8010 3A7C
0x8010 3C00 - 0x8010 3C10
GPDMA Controllers
0x8010 4000 - 0x8010 40FF APB2 0x8010 4000 - 0x8010 4058 ARM7 cache control
0x8020 0000 - 0x8020 007F APB3 0x8020 0000 - 0x8020 0078 Streaming Analog Input 1 (SAI1)
0x8020 0180 - 0x8020 01FF APB3 0x8020 0180 - 0x8020 01F8 Streaming Analog Input 4 (SAI4)
0x8020 0200 - 0x8020 027F APB3 0x8020 0200 - 0x8020 027C Streaming Analog Output 1 (SAO1)
0x8020 0280 - 0x8020 028F APB3 0x8020 0280 - 0x8020 02FC Streaming Analog Output 2 (SAO2)
0x8020 0380 - 0x8020 03FF APB3 0x8020 0380 - 0x8020 03BC I2S and Streaming Analog Converters
0x8030 0000 - 0x8030 0FFF AHB 0x8030 0000 - 0x8030 0474 Interrupt Controller

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User manual Rev. 02 — 1 June 2007 10 of 362
1. Introduction
Upon reset, the LPC288x executes code from an internal ROM. This code allows four
possible types of startup. These are:
•Execute code from internal flash memory.
•Execute code from external memory bank 0.
•Download code from USB to memory.
•Test mode. Toggles a port pin to indicate basic device functionality.
2. Operation
Internal pulldowns on the P2.3 and P2.2 pins cause them to read as 0 when unconnected.
This results in the default startup mode being execution from internal Flash memory. One
or two external pullup resistors can cause startup to use one of the other modes, as
shown in Table 3–3.
3. Boot mode descriptions
The boot process is illustrated in figure 1. The following discussion describes each boot
mode in more detail.
Mode 0: Execute user program from internal flash memory
This is the default mode if the P2.3 and P2.2 pins are left unconnected. The Flash
memory begins at address 0x1040_0000. This is the address branched to in this mode.
In order to prevent accidental execution of an unprogrammed Flash, the ROM code
checks for a specific valid user program marker value in memory prior to branching into
the Flash memory. This marker is stored as address 0x104F_F800, 2K bytes below the
top of the 1MB Flash memory. The value expected here is 0xAA55_AA55. If Mode 0 is
selected and the valid user program marker value is not found in the Flash, control is
transferred to Mode 2 (USB download mode).
UM10208
Chapter 3: Boot process
Rev. 02 — 1 June 2007 User manual
Table 3. Boot flow chart
P2.3/Mode2 P2.2/Mode1 Mode selected
0 0 Execute user program from internal flash memory.
0 1 Execute user program from external memory on bank 0.
1 0 Download program from USB port to memory.
1 1 Test mode.

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NXP Semiconductors UM10208
Chapter 3: LPC2800 Boot process
Mode 1: Execute user program from external memory on static memory bank 0
Static bank 0 of external memory controller is used in a default configuration to execute a
user program. The configuration of static bank 0 following reset is for a bus width of 16 bits
and an active low chip select. The starting address used for the external static memory is
0x2000_0000. The full address range for bank 0 is 0x4000_0000 through 0x401F_FFFF,
a 2 megabyte space.
Mode 2: Download program from USB port to memory (DFU mode)
The purpose of this mode is to allow programming of the internal Flash memory via USB.
Files to be download must be specially formatted in order to be handled by the ROM
download code. A conversion program and a DFU downloader are available from Philips.
Mode 3: Test mode
This mode is a simple test for device function. Port pin P2.1 is toggled to indicate basic
functionality of the device in its current environment.

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NXP Semiconductors UM10208
Chapter 3: LPC2800 Boot process
4. Part Identification register (SYS_PARTID - 0x8000 507C)
The SYS_PARTID register contains a value that identifies this device.
Fig 3. Boot process
Basic Initialization
- disable interrupts
- disable cache
- initialize CGU
Initialize exception modes
Mode = 3? Y
N
Initialize external memory
controller
Mode = 1? Y
N
Mode = 2? Y
N
Initialize internal memory
systems
Reset
- Continuously toggle pin P2.1
- Branch to first Flash address.
- USB download
- Branch to first bank 0 address.
Flash ready? N
Valid User
Program
Marker?
N
Y
Y

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NXP Semiconductors UM10208
Chapter 3: LPC2800 Boot process
Table 4: Part Identification register (SYS_PARTID - 0x8000 507C)
Bit Symbol Description Reset
value
31:0 PART_ID This value distinguishes this device type. 0x0102 100A

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1. Introduction
The ARM CPU in the LPC288x has been extended with a 2-way set-associative cache
controller. The cache is 8 kB in size and can store both data and instruction code.
The biggest benefit of this cache is that if code is run from non-zero-wait state memory, for
instance the internal FLASH controller, these memories can still behave almost as if they
are zero-wait state memory. If code is executed from the cache, the CPU will run at 1
clock per instruction most of the time.
The trade-off in introducing this cache is that each AHB access that bypasses the cache
will have an extra wait state inserted. So, it is generally advisable that both instruction
caching and data caching are turned on for most regions of on and off-chip memory.
2. Features
•8 kB in a 2-way set-associative cache
•Configured as 2×128 cache lines of eight 32-bit words each
•Sixteen pages of address mapping each allow any address range to be selected for
caching
3. Cache definitions
•A 2-way cache includes two cache lines that can be used for each memory address.
•A cache line is 8 consecutive 32 bit words. The cache contains 128 cache lines, each
with 2 ways, making 8 kB total.
•The association of memory addresses to cache lines is that cache line 0 corresponds
with address word addresses 0x0 to 0x07, cache line 1 corresponds with word
addresses 0x08 to 0x0F, etc. After 1024 words, this repeats. Thus, word address 0,
word address 1024, word address 2048, ... all map to cache line 0.
•A tag word is associated with each cache line. The tag includes the address each
cache line is currently associated with, a "dirty" flag that indicates if the line has been
written to since it was read from memory, and a "Least Recently Used" tag that
identifies which of the two cache lines should be overwritten if another address that
maps there is accessed by the CPU.
•For the purposes of cache operation, memory is divided into pages of 2 megabytes,
composed of 4 kB sub-pages (1024 words of 32 bits).
•A cache line is marked as "dirty" when the CPU writes to an address which is
currently in the cache. In this case, the data in the "real" memory no longer reflects the
actual value. The entire cache line is marked as dirty when any element within that
cache line is written.
•A cache miss is defined as a read or write by the CPU to an address in memory which
is not currently in the cache.
UM10208
Chapter 4: Processor cache and memory mapping
Rev. 02 — 1 June 2007 User manual

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NXP Semiconductors UM10208
Chapter 4: LPC2800 Cache
•A cache hit is defined as a read or write by the CPU to an address in memory which is
currently in cache.
•A cache flush is the act of writing a dirty cache line back to memory.
4. Description
Figure 4–4 shows the structure of the cache and how memory addresses map to cache
lines. For caching purposes, memory is divided into pages of 2 megabytes of 4 kB
sub-pages (1024 words of 32 bits). The sub-pages correspond to 128 cache lines (128
entries of eight 32-bit words).
The associated cache line in memory will be stored in cache memory at a fixed position.
An example sequence could begin with an access to one of the first 8 words of a 2
megabyte page of memory. These words will be stored on the first cache line (cache line
0) of Way_0. An access to one of the second 8 words in the same page will be stored on
the second cache line (cache line 1) of Way_0. Later, if an address that maps to cache
line 0 is read from a different portion of memory, it will be stored in Way_1 (since Way_1
has not yet been used). If still another address mapping to cache line 0 is read, the Least
Recently Used tag is used to decide whether the new line will be stored in Way_0 or
Way_1. The least recently used previously cached line must be removed, and the new
line stored in its place. In this example, the way that is overwritten will be Way_0, since
Way_1 was used more recently. If the cache line that must be removed is marked as
“dirty”, it will be written back to memory prior to being overwritten by the new memory line.
Note that the cache can be set to work only for instruction accesses, only for data
accesses, or for both. This is done via the DATA_ENABLE and INSTRUCTION_ENABLE
bits in the CACHE_SETTINGS register.

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User manual Rev. 02 — 1 June 2007 16 of 362
NXP Semiconductors UM10208
Chapter 4: LPC2800 Cache
The cache has 16 configurable pages, each being 2 megabytes in size. The cache treats
these 16 pages as if they occupy the bottom 32 Megabytes of the system memory map,
which is their default mapping. The cache can re-map any of these pages such that the
physical address is above the lower 32 megabytes.
In Figure 4–5, a diagram showing physical memory and a virtual page mapping is given.
On the left of the diagram, memory is shown with no remapping, as issued by the CPU.
On the right, a higher physical address is shown mapped into a lower address for caching
purposes. To accomplish this, a page is used as a virtual page. Accessing this virtual
page, the cache will re-map the AHB bus address to the higher address range during a
cache miss, cache flush or a write access to the virtual page.
Fig 4. Cache operation
Word 0
Word 7
Word 8
Word 15
Read into
cache line 0
Way_0
4K bytes
Word 1
2M
bytes
128 * 8
Words Read into
cache line 1
Second read
into cache line 0
Third read into
cache line 0
Way_1
4K bytes
128 * 8
Words
128 * 8
Words
line 0
line 128
line 1 line 0
line 128
line 1
Memory

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NXP Semiconductors UM10208
Chapter 4: LPC2800 Cache
In Figure 4–5, page 2 of the lower 32 megabytes of address space has been mapped to
an address in the external static memory space by placing a value of 0x104 in the
PAGE_ADDRESS_2 register. Details of this remapping may be found in the descriptions
of the PAGE_ADDRESS registers later in this chapter.
When re-mapping points to a higher page in the memory map, that page may still also be
accessed directly by the CPU using the original absolute address of the page. In that
case, the cache takes no part in the access. This allows both cached and non-cached
access to the same address region if needed.
Each of the 16 configurable cache pages can be individually enabled and disabled, as
well as having a virtual address programmed.
Fig 5. Memory mapping
0x0000_0000
0x0020_0000
0x0040_0000
0x0200_0000
Page 0
Page 1
Page 2
Page 16
First
32 M
bytes
Above
32 M
bytes External
SRAM
0x0000_0000
0x0200_0000
Memory
(address as seen
by the AHB bus)
First
32 M
bytes
Above
32 M
bytes
Memory
(address as issued
by the CPU)
0x0040_0000
0x2080_0000 External
SRAM
0x2080_0000
Address remapped
by value in
ADDRESS_PAGE_2

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User manual Rev. 02 — 1 June 2007 18 of 362
NXP Semiconductors UM10208
Chapter 4: LPC2800 Cache
4.1 Cache enabling and function
Following reset, the cache is disabled. The address, data, and control signals of the CPU
AHB bus is routed directly to the multilayer AHB matrix. The response from whichever
functional block is targeted by the address is routed directly to the CPU.
The cache can be enabled by setting the DATA_ENABLE and/or
INSTRUCTION_ENABLE bits in the CACHE_SETTINGS register.
4.1.1 Cache function details
For each page of the cache which is enabled, the following points apply:
•If data is read, and not in the cache (a cache miss), a line of eight 32-bit words is read
from the AHB bus. In the meantime, the CPU is stalled (and in low power mode if
clock gating is enabled.)
•If data is read and is found in the cache (a cache hit), data is read from cache with 0
wait states.
•If data is written and the location is not in the cache (a cache miss), the data is written
directly to memory.
•If data is written, and the location is in the cache because this location has been read
before (a cache hit), then data is written to the cache with 0 wait states, and the line is
marked as dirty.
•If a dirty line is about to be discarded because of a cache miss (the cache line needs
to be reused for a different memory region), the old line is first written back to memory
(a cache line flush).
•When a cache line is read from memory and stored in the cache (in Way_0 or
Way_1), the cache controller will mark the other half of the cache line at the same
address as Least Recently Used (LRU) in its tag memory.
5. Register description
The cache controller includes the registers shown in Table 4–5. These registers are
accessible in the APB2 address space. It is recommended that the clock gating option be
enabled in the CGU for the APB interface of the CPU in order to reduce power
consumption. Each register is described in more detail in the following sections.
Note: the APB interface of the CPU configuration hardware must be set to run at the same
BASE_CLK frequency as the AHB interface of the CPU before any register is written.
Table 5. Cache and memory mapping registers
Address Register name Description Reset
value Access
0x8010 4000 CACHE_RST_STAT Monitors the reset state of the cache. 0 RO
0x8010 4004 CACHE_SETTINGS Controls the overall configuration of the cache. 0 R/W
0x8010 4008 CACHE_PAGE_CTRL Allows individual enabling or disabling of caching for the
16 configurable pages. 0R/W
0x8010 400C C_RD_MISSES If cache performance analysis is enabled in the
CACHE_SETTINGS register, this register indicates the
number of times that a cache line is read from memory
(cache read misses).
0RO

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User manual Rev. 02 — 1 June 2007 19 of 362
NXP Semiconductors UM10208
Chapter 4: LPC2800 Cache
5.1 Cache Reset Status register (CACHE_RST_STAT, 0x8010 4000)
The read-only CACHE_RST_STAT register monitors the reset status of the cache
controller. If the CACHE_RST bit in the CACHE_SETTINGS register is set and then
cleared by software, this bit indicates the status of the ongoing reset. The reset of the
cache tag memory will take 128 CPU clock-cycles to complete. Table 4–6 shows the bit
definitions for the CACHE_RST_STAT register.
0x8010 4010 C_FLUSHES If cache performance analysis is enabled in the
CACHE_SETTINGS register, this register indicates the
number of times that a dirty cache line has been written
back to memory (cache flushes).
0RO
0x8010 4014 C_WR_MISSES If cache performance analysis is enabled in the
CACHE_SETTINGS register, this register indicates the
number of times that a write occurs to an address not in
the cache (cache write misses).
0RO
0x8010 4018 PAGE_ADDRESS_0 Re-mapping address for page 0. 0 R/W
0x8010 401C PAGE_ADDRESS_1 Re-mapping address for page 1. The reset value points
this page to the Boot ROM. 0x1 R/W
0x8010 4020 PAGE_ADDRESS_2 Re-mapping address for page 2. The reset value points
this page to the on-chip SRAM. 0x2 R/W
0x8010 4024 PAGE_ADDRESS_3 Re-mapping address for page 3. The reset value points
this page to the on-chip SRAM. 0x2 R/W
0x8010 4028 PAGE_ADDRESS_4 Re-mapping address for page 4. The reset value points
this page to on-chip Flash memory. 0x82 R/W
0x8010 402C PAGE_ADDRESS_5 Re-mapping address for page 5. The reset value points
this page to external static memory bank 0. 0x100 R/W
0x8010 4030 PAGE_ADDRESS_6 Re-mapping address for page 6. The reset value points
this page to external static memory bank 0. 0x100 R/W
0x8010 4034 PAGE_ADDRESS_7 Re-mapping address for page 7. The reset value points
this page to external SDRAM. 0x180 R/W
0x8010 4038 PAGE_ADDRESS_8 Re-mapping address for page 8. The reset value points
this page to external SDRAM. 0x180 R/W
0x8010 403C PAGE_ADDRESS_9 Re-mapping address for page 9. 0x400 R/W
0x8010 4040 PAGE_ADDRESS_10 Re-mapping address for page 10. 0x401 R/W
0x8010 4044 PAGE_ADDRESS_11 Re-mapping address for page 11. 0x102 R/W
0x8010 4048 PAGE_ADDRESS_12 Re-mapping address for page 12. 0x104 R/W
0x8010 404C PAGE_ADDRESS_13 Re-mapping address for page 13. 0x106 R/W
0x8010 4050 PAGE_ADDRESS_14 Re-mapping address for page 14. 0xE R/W
0x8010 4054 PAGE_ADDRESS_15 Re-mapping address for page 15. 0xF R/W
0x8010 4058 CPU_CLK_GATE Controls gating of the CPU clock when the CPU is
stalled. 0R/W
Table 5. Cache and memory mapping registers
Address Register name Description Reset
value Access

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Chapter 4: LPC2800 Cache
5.2 Cache Settings register (CACHE_SETTINGS, 0x8010 4004)
The CACHE_SETTINGS register controls the general setup of the cache, allows resetting
of the entire cache, and controls the cache performance analysis feature. Table 4–7
shows the bit definitions for the CACHE_SETTINGS register.
Table 6. Cache Reset Status register (CACHE_RST_STAT, 0x8010 4000)
Bit Symbol Description Reset
value
0 CACHE_STATUS 0: Cache reset is complete.
1: Cache reset is ongoing.
When the cache is reset, software should poll
CACHE_STATUS until it is 0.
0
31:1 - Reserved. The value read from a reserved bit is not defined. -
Table 7. Cache Settings register (CACHE_SETTINGS, 0x8010 4004)
Bit Symbol Description Reset
value
0 CACHE_RST Cache controller reset control. This bit resets the cache
hardware internally, clearing all tags so that the entire
cache is considered empty. This takes 128 CPU clock
cycles to complete. The reset progress can be followed
by reading register CACHE_RST_STAT.
0 : De-assert reset to the Flash controller.
1 : Assert reset to the Flash controller.
Note: the cache MUST be reset before it is enabled. It is
recommended to include this procedure at system
startup.
0
1 DATA_ENABLE Enables use of the cache for storing data.
0 : All storage of data in the cache is disabled. This
applies to all 16 pages.
1 : Storage of data in the cache is enabled. This applies
to all pages enabled via the CACHE_PAGE_CTRL
register.
0
2 INSTRUCTION_ENABLE Enables use of the cache for storing instructions.
0 : All storage of instructions in the cache is disabled.
This applies to all 16 pages.
1 : Storage of instructions in the cache is enabled. This
applies to all pages enabled via the
CACHE_PAGE_CTRL register.
0