NXP Semiconductors LPC2880 User manual

UM10208
LPC2880/LPC2888 User manual
Rev. 02 — 1 June 2007 User manual
Document information
Info Content
Keywords LPC2880, LPC2888, LPC288x, ARM, ARM7, embedded, 32-bit,
microcontroller, USB 2.0, USB HS
Abstract LPC288x User manual

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User manual Rev. 02 — 1 June 2007 2 of 362
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10208
LPC288x User manual
Revision history
Rev Date Description
02 20070601 Various editorial and content updates to the following chapters:
•The format of this user manual has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Universal Asynchronous Receiver-Transmitter (UART):
The UART baud rate is derived from the UART baud rate clock (UART_CLK).
•External Memory Controller (EMC):
SDRAM Usage notes added (Section 8–12).
•Clock Generation Unit (CGU) and power control:
CGU Usage notes added including a section on how to achieve low-power operation
(Section 7–5).
•USB Device controller:
–DMA mode transfer section was improved (Section 17–6.4).
–Endpoint configuration table added (Table 17–232).
–Section 17–8.6 on interrupt handling was further elaborated.
•I/O pinning:
Section 25–2.5 “Pin structure”added.
•DC-to-DC converter:
Section 6–2 “General operation”was improved.
•SD/MMC interface:
Status register contents were corrected (Table 23–345). Descriptions on bits 17 and 19
were swapped.
•General Purpose DMA controller (GPDMA):
Register locations for registers DMA3EXTEN and DMA5EXTEN were corrected
(Table 15–196).
•Dual-channel 16-bit Digital-to-Analog Converter (DDAC):
–Description of Dual DAC was improved.
–Section 22–6.2 “Power-up procedure”was corrected.
•Dual-channel 16-bit Analog-to-Digital converter (DADC):
Bits 0-7 of Decimator Control register were corrected (Table 21–306).
•I2S output module (DAO):
DAO pin description was corrected (Table 20–292).
•Boot process:
Part Identification register (Table 3–4) was moved to this chapter from chapter “System
control ”.
•Chapter “System control” removed.
•Chapter “General Purpose I/O (GPIO)” added.
01 20060905 LPC288x User manual

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User manual Rev. 02 — 1 June 2007 3 of 362
1. Introduction
The LPC288x is an ARM7-based microcontroller for portable applications requiring low
power and high performance. It includes a USB 2.0 High Speed device interface, an
external memory interface that can interface to SDRAM and Flash, an MMC/SD memory
card interface, A/D and D/A converters, and serial interfaces including UART, I2C, and I2S.
Architectural enhancements like multi-channel DMA, processor cache, simultaneous
operations on multiple internal buses, and flexible clock generation help ensure that the
LPC288x can handle more demanding applications than many competing devices. The
chip can be powered from a single battery, from the USB, or from regulated 1.8 and 3.3V.
2. Features
•ARM7TDMI processor with 8 kB cache operating at up to 60 MHz
•1 MB on-chip Flash Program Memory with 128-bit access for high performance
•64 kB SRAM
•32 kB ROM
•On-chip DC-DC converter can generate all required voltages from a single battery or
from USB power
•Multiple internal buses allow simultaneous GP DMA, USB DMA, and program
execution from on-chip Flash without contention.
•External memory controller supports Flash, SRAM, ROM, and SDRAM.
•Advanced Vectored Interrupt Controller, supporting up to 30 vectored interrupts
•Innovative Event Router allows interrupt, power-up, and clock-start capabilities from
up to 105 sources
•Multi-channel GP DMA controller that can be used with most on-chip peripherals as
well as for memory-to-memory transfers.
•Serial Interfaces:
–Hi-Speed or Full-speed USB 2.0 Device (480 or 12 Mbits/s) with on-chip PHYsical
layer
–UART with fractional baud rate generation, flow control, IrDA support, and FIFOs
–I2C Interface
–I2S (Inter-IC Sound) interface for independent stereo digital audio input and output
•Secure Digital (SD) / MultiMediaCard (MMC) memory card interface
•10 bit A/D Converter with 5-channel input multiplexing
•16 bit stereo A/D and D/A converters with gain control and optional DMA
•Advanced clock generation and power control reduce power consumption
•Two 32-bit Timers with selectable prescalers
•8-bit LCD interface bus
•Real Time Clock can be clocked by 32 kHz oscillator or another source
•Watchdog Timer with interrupt and/or reset capabilities
UM10208
Chapter 1: Introductory information
Rev. 02 — 1 June 2007 User manual

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User manual Rev. 02 — 1 June 2007 4 of 362
NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
•180 pin TFBGA package
3. Applications
•Portable, battery powered devices
•USB devices
4. Architectural overview
The LPC288x includes an ARM7TDMI CPU with an 8kB cache, an AMBA Advanced
High-performance Bus (AHB) interfacing to high speed on-chip peripherals and internal
and external memory, and four AMBA Advanced Peripheral Buses (APBs) for connection
to other on-chip peripheral functions. The LPC288x permanently configures the
ARM7TDMI processor for little-endian byte order.
The LPC288x includes a multi-layer AHB and four separate APBs, in order to minimize
interference between the USB controller, other DMA operations, and processor activity.
Bus masters include the ARM7 itself, the USB block, and the general purpose DMA
controller.
Lower speed peripheral functions are connected to the APBs. Four AHB-to-APB bridges
interface the APBs to the AHB.
5. ARM7TDMI processor
The ARM7TDMI is a general purpose 32 bit microprocessor that offers high performance
and very low power consumption. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, and the instruction set and related decode mechanism
are much simpler than those of microprogrammed Complex Instruction Set Computers.
This simplicity results in a high instruction throughput and impressive real-time interrupt
response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI processor has two instruction sets:
•The standard 32 bit ARM instruction set.
•A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.

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User manual Rev. 02 — 1 June 2007 5 of 362
NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
THUMB code be as little as 65% of the code size of ARM, and 160% of the performance
of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI processor is described in detail on the ARM website.
6. On-Chip flash memory system
The LPC2888 includes a 1 MB Flash memory system. This memory may be used for both
code and data storage. Programming of the Flash memory may be accomplished in
several ways. It may be programmed In System via the USB port. The application
program may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage and field firmware upgrades.
The Flash is 128 bits wide and includes buffering to allow 3 out of 4 sequential read
operations to operate without wait states.
7. On-Chip Static RAM
The LPC288x includes 64 kB of static RAM that may be used for code and/or data
storage.
8. On-Chip ROM
The LPC288x includes 32 kB of Read Only Memory that may be used for code and/or
constant storage. Execution begins in on-chip ROM after a Reset.
Philips provides a standard boot code in this ROM that reads the state of the Mode inputs
and accordingly does one of the following:
1. starts execution in internal Flash,
2. starts execution in external memory,
3. performs a hardware self-test, or
4. downloads code from the USB interface into on-chip RAM and transfers control to the
downloaded code.

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 6 of 362
NXP Semiconductors UM10208
Chapter 1: LPC2800 Introductory information
9. Block diagram
(1) LPC2888 only
Fig 1. LPC288x block diagram
MULTI-LAYER AHB
AIN[4:0]
Px.y
WATCHDOG
TIMER
SD/MMC CARD
INTERFACE
GENERAL
PURPOSE I/O
SYSTEM
CONTROL
EVENT
ROUTER
register
interface
DC-TO-DC
CONVERTER
START,
STOP
SCL, SDA
MCLK
MD[3:0], MCMD
DATI
BCKI, WSI
AOUTL,
AOUTR
AINL, AINR
DATO
BCKO, DCLKO,
WSO
+1.5 V
or +5 V
3.3 V,
1.8 V
XTALI
XTALO
X32I
X32O
CLOCK
GENERATION
UNIT
OSCILLATOR
AND PLLs
ARM7TDMI-S
JTAG DEBUG
INTERFACE
8 kB CACHE
JTAG_TRST JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_SEL
FLASH
INTERFACE
1 MB
FLASH(1)
SRAM
INTERFACE
64 kB
SRAM
ROM
INTERFACE
BOOT
ROM
REAL-TIME
CLOCK
OSCILLATOR
FIFO FIFO I2S-BUS
INPUT
FIFO I2S-BUS
OUTPUT
DUAL ANALOG
INPUT
FIFO
DUAL ANALOG
OUTPUT
EXTERNAL
MEMORY
CONTROLLER
A[20:0],
D[15:0],
etc.
VECTORED
INTERRUPT
CONTROLLER
HS USB
WITH DMA
DP, DM, VBUS,
RREF, CONNECT
LPC2880/2888
AHB TO APB
BRIDGE 0
AHB TO APB
BRIDGE 3
AHB TO APB
BRIDGE 1
AHB TO APB
BRIDGE 2
GP DMA
CONTROLLER
10-BIT A/D
CONVERTER
UART WITH
IrDA
TXD, RTS
RXD, CTS
LCD
INTERFACE LCD bus
I2C-BUS
INTERFACE
32-BIT
TIMER 0
32-BIT
TIMER 1
002aac296

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User manual Rev. 02 — 1 June 2007 7 of 362
1. Memory map and peripheral addressing
ARM processors have a single 4 GB address space. The following table shows how this
space is used on the LPC288x. Addresses not shown in this table are not used.
1.1 Memory map
The LPC2880/2888 memory map incorporates several distinct regions, as shown in
Figure 2–2. When an application is running, the CPU interrupt vectors are remapped to
allow them to reside in on-chip SRAM.
UM10208
Chapter 2: LPC2800 Memory addressing
Rev. 02 — 1 June 2007 User manual
Table 1. LPC288x memory usage
Address range General use Address range details and description
0x0000 0000 to
0x0FFF FFFF Cacheable area 0x0020 0000 - 0x0020 7FFF Internal ROM (32 kB)
0x0040 0000 - 0x0040 FFFF Internal RAM (64 kB)
(other addresses) Software can map other internal and external
memory into this area, to improve its effective
access time.
0x1000 0000 to
0x1FFF FFFF Internal Memory 0x1040 0000 - 0x104F FFFF Flash (1 MB)
0x2000 0000 to
0x5FFF FFFF External Memory 0x2000 0000 - 0x201F FFFF and 0x4000 0000 - 0x401F FFFF Static memory bank 0, 2 MB, STCS0
0x2400 0000 - 0x241F FFFF and
0x4400 0000 - 0x441F FFFF Static memory bank 1, 2 MB, STCS1
0x2800 0000 - 0x281F FFFF and
0x4800 0000 - 0x481F FFFF Static memory bank 2, 2 MB, STCS2
0x3000 0000-0x33FF FFFFand
0x5000 0000 - 0x53FF FFFF Dynamic memory bank 0, 64 MB
0x8000 0000 to
0x8FFF FFFF Peripherals See Table 2–2 Includes AHB Peripherals and 4 APBs

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 8 of 362
NXP Semiconductors UM10208
Chapter 2: LPC2800 Memory mapping
Fig 2. Memory map
remapped area
0x0000 0000
0.0 GB
2.0 GB
4.0 GB
0x0FFF FFFF
0x2000 0000
0x8000 0000
0x7FFF FFFF
0x1FFF FFFF
0xFFFF FFFF
0x1000 0000
internal memory
external memory
(first instance)
peripherals
static memory bank 2, 2 MB 0x2800 0000 to 0x281F FFFF
reserved 0x2420 0000 to 0x27FF FFFF
dynamic memory bank 0, 64 MB 0x3000 0000 to 0x33FF FFFF
exception vectors 0x0000 0000 to 0x0000 001F
static memory bank 1, 2 MB 0x2400 0000 to 0x241F FFFF
static memory bank 0, 2 MB 0x2000 0000 to 0x201F FFFF
reserved 0x1050 0000 to 0x1FFF FFFF
internal ROM (32 kB) 0x0020 0000 to 0x0020 7FFF
reserved 0x0050 0000 to 0x0FFF FFFF
internal RAM (64 kB) 0x0040 0000 to 0x0040 FFFF
reserved 0x2020 0000 to 0x23FF FFFF
internal flash (1 MB) 0x1040 0000 to 0x104F FFFF
reserved 0x1000 0000 to 0x0000 003F
reserved 0x2820 0000 to 0x2FFF FFFF
reserved 0x3400 0000 to 0x3FFF FFFF
static memory bank 2, 2 MB 0x4800 0000 to 0x481F FFFF
reserved 0x4420 0000 to 0x47FF FFFF
dynamic memory bank 0, 64 MB 0x5000 0000 to 0x53FF FFFF
static memory bank 1, 2 MB 0x4400 0000 to 0x441F FFFF
static memory bank 0, 2 MB 0x4000 0000 to 0x401F FFFF
reserved 0x4020 0000 to 0x43FF FFFF
reserved 0x4820 0000 to 0x4FFF FFFF
reserved 0x5400 0000 to 0x7FFF FFFF
0x4000 0000
0x3FFF FFFF
0x9000 0000
0x8FFF FFFF
external memory
(second instance)
1.0 GB
includes AHB and 4 APB buses 0x8000 0000 to 0x8FFF FFFF
reserved 0x9000 0000 to 0xFFFF FFFF
002aac240

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 9 of 362
NXP Semiconductors UM10208
Chapter 2: LPC2800 Memory mapping
2. Peripheral addressing
Peripheral devices on the LPC288x are distributed among the ARM High-speed Bus
(AHB) and four ARM Peripheral Buses (APBs). The following table indicates which bus
each device is connected to. Addresses not shown in this table are not used.
Table 2. LPC288x Peripheral devices
Address allocation Bus Register addresses (inclusive) Peripheral device
0x8000 0000 - 0x8000 1FFF APB0 0x8000 0000 - 0x8000 1C00 Event Router
0x8000 2000 - 0x8000 23FF APB0 0x8000 2000 - 0x8002 027C Real Time Clock (RTC)
0x8000 2400 - 0x8000 27FF APB0 0x8000 2400 - 0x8000 2430 10 bit Analog to Digital Converter (ADC)
0x8000 2800 - 0x8000 2BFF APB0 0x8000 2800 - 0x8000 283C Watchdog Timer (WDT)
0x8000 3000 - 0x8000 3FFF APB0 0x8000 3000 - 0x8000 31E8 I/O Configuration (IOCONF)
0x8000 4000 - 0x8000 4BFF APB0 0x8000 4000 - 0x8000 443C Clock Generation Unit (CGU) Switchbox
0x8000 4C00 - 0x8000 4FFF APB0 0x8000 4C00 - 0x8000 4CFC Clock Generation Unit (CGU)
0x8000 5000 - 0x8000 53FF APB0 0x8000 5000 - 0x8000 507C System Configuration Registers
0x8000 8000 - 0x8000 8FFF AHB 0x8000 8000 - 0x8000 8258 External Memory Controller (EMC)
0x8002 0000 - 0x8000 03FF APB1 0x8002 0000 - 0x8002 0010 Timer 0
0x8002 0400 - 0x8000 07FF APB1 0x8002 0400 - 0x8002 0410 Timer 1
0x8002 0800 - 0x8002 0BFF APB1 0x8002 0800 - 0x8002 082C I2C Controller
0x8004 0000 - 0x8004 1FFF AHB 0x8004 0000 - 0x8004 10B4 USB Controller
0x8010 0000 - 0x8010 0FFF APB2 0x8010 0000 - 0x8010 00BC Secure Digital / Multimedia Card
Interface (SD/MCI)
0x8010 1000 - 0x8010 1FFF APB2 0x8010 1000 - 0x8010 1034
0x8010 1FD4 - 0x8010 1FEC UART
0x8010 2000 - 0x8010 2FFF APB2 0x8010 2000 - 0x8010 201C
0x8010 2FD8 - 0x8010 2FEC Flash Programming Interface
0x8010 3000 - 0x8010 33FF APB2 0x8010 3000 - 0x8010 3080 LCD Interface
0x8010 3800 - 0x8010 3FFF APB2 0x8010 3800 - 0x8010 38FC
0x8010 3A00 - 0x8010 3A7C
0x8010 3C00 - 0x8010 3C10
GPDMA Controllers
0x8010 4000 - 0x8010 40FF APB2 0x8010 4000 - 0x8010 4058 ARM7 cache control
0x8020 0000 - 0x8020 007F APB3 0x8020 0000 - 0x8020 0078 Streaming Analog Input 1 (SAI1)
0x8020 0180 - 0x8020 01FF APB3 0x8020 0180 - 0x8020 01F8 Streaming Analog Input 4 (SAI4)
0x8020 0200 - 0x8020 027F APB3 0x8020 0200 - 0x8020 027C Streaming Analog Output 1 (SAO1)
0x8020 0280 - 0x8020 028F APB3 0x8020 0280 - 0x8020 02FC Streaming Analog Output 2 (SAO2)
0x8020 0380 - 0x8020 03FF APB3 0x8020 0380 - 0x8020 03BC I2S and Streaming Analog Converters
0x8030 0000 - 0x8030 0FFF AHB 0x8030 0000 - 0x8030 0474 Interrupt Controller

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 10 of 362
1. Introduction
Upon reset, the LPC288x executes code from an internal ROM. This code allows four
possible types of startup. These are:
•Execute code from internal flash memory.
•Execute code from external memory bank 0.
•Download code from USB to memory.
•Test mode. Toggles a port pin to indicate basic device functionality.
2. Operation
Internal pulldowns on the P2.3 and P2.2 pins cause them to read as 0 when unconnected.
This results in the default startup mode being execution from internal Flash memory. One
or two external pullup resistors can cause startup to use one of the other modes, as
shown in Table 3–3.
3. Boot mode descriptions
The boot process is illustrated in figure 1. The following discussion describes each boot
mode in more detail.
Mode 0: Execute user program from internal flash memory
This is the default mode if the P2.3 and P2.2 pins are left unconnected. The Flash
memory begins at address 0x1040_0000. This is the address branched to in this mode.
In order to prevent accidental execution of an unprogrammed Flash, the ROM code
checks for a specific valid user program marker value in memory prior to branching into
the Flash memory. This marker is stored as address 0x104F_F800, 2K bytes below the
top of the 1MB Flash memory. The value expected here is 0xAA55_AA55. If Mode 0 is
selected and the valid user program marker value is not found in the Flash, control is
transferred to Mode 2 (USB download mode).
UM10208
Chapter 3: Boot process
Rev. 02 — 1 June 2007 User manual
Table 3. Boot flow chart
P2.3/Mode2 P2.2/Mode1 Mode selected
0 0 Execute user program from internal flash memory.
0 1 Execute user program from external memory on bank 0.
1 0 Download program from USB port to memory.
1 1 Test mode.