Dialog Semiconductor DA1468 series User manual

User manual
DA1468x Development kit - Basic
UM-B-066
Abstract
This document outlines the system design, configuration options and supported features of DA1468x
Basic Development Kit, rev-E (224-18-E).

UM-B-066
DA1468x Development kit - Basic
User manual
Revision 1.4
26-March-2018
CFR0012
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© 2018 Dialog Semiconductor
Contents
Abstract................................................................................................................................................ 1
Contents............................................................................................................................................... 2
Figures.................................................................................................................................................. 3
Tables ................................................................................................................................................... 3
1Terms and definitions................................................................................................................... 4
2References..................................................................................................................................... 4
3Introduction.................................................................................................................................... 5
4System overview ........................................................................................................................... 5
4.1 Features................................................................................................................................ 5
4.2 General description............................................................................................................... 6
5Basic development kit system..................................................................................................... 8
5.1 Overview ............................................................................................................................... 8
5.2 DA1468x system................................................................................................................... 9
5.3 DA1468x pin assignment.................................................................................................... 10
5.4 Basic development kit jumper settings................................................................................ 11
5.5 Booting from UART............................................................................................................. 12
5.6 Crystals ............................................................................................................................... 12
5.7 RF port ................................................................................................................................ 13
5.8 QSPI Data Flash memory (U9 or U2) ................................................................................. 14
5.9 Push buttons and user controlled LEDs.............................................................................. 15
5.10 Debugging processor (U4).................................................................................................. 16
5.11 Voltage level translation...................................................................................................... 17
5.12 Leakage currents during power measurement ................................................................... 17
5.13 UART header (J13)............................................................................................................. 17
5.14 Power section...................................................................................................................... 19
5.14.1 Battery options..................................................................................................... 20
6Revision history .......................................................................................................................... 22

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Figures
Figure 1 - DA1468x Basic development kit............................................................................................ 6
Figure 2 - Block diagram of DA1468x Basic development kit................................................................ 7
Figure 3: DA1468x system schematic.................................................................................................... 9
Figure 4: RF matching circuit must be placed as close as possible to the antenna ............................ 13
Figure 5: RF port, printed antenna and RF switch............................................................................... 13
Figure 6: QSPI Data Flash V33 or V18 selectable power supply.......................................................... 14
Figure 7: Push button and general purpose LED schematic................................................................ 15
Figure 8: White LED ............................................................................................................................. 15
Figure 9: Debugging processor............................................................................................................ 16
Figure 10: Level translator circuit........................................................................................................ 17
Figure 11: UART header (J13).............................................................................................................. 18
Figure 12: Full UART hardware configuration ..................................................................................... 18
Figure 13: Basic development kit power section ................................................................................ 19
Figure 14: Location of jumper J9 and LDOs U5, U8............................................................................. 20
Figure 15: Typical CR2032 (non-rechargeable) coin cell battery ........................................................ 20
Figure 16: Coin cell battery placement ............................................................................................... 21
Figure 17: Removing the coin cell battery........................................................................................... 21
Tables
Table 1: Basic development kit pin assignment.................................................................................. 10
Table 2: Default jumper settings on Basic development kit ................................................................ 11
Table 3: Y1 (16 MHz crystal) characteristics....................................................................................... 12
Table 4: Y2 (32 kHz crystal) characteristics........................................................................................ 12
Table 5: Signals using a voltage level translation/isolation chip ......................................................... 17
Table 6: DA1468x pin assignment of UART signal............................................................................. 18
Table 7: DA1468x SoC power options ................................................................................................ 19

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User manual
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1 Terms and definitions
DCR Direct Current Resistance
DCXO Digitally Controlled Crystal Oscillator
HW hardware
IFA Inverted-F Antenna
JTAG Join Test Action Group (test interface)
LED Light Emitting Diode
LDO Low-Dropout
RF Radio Frequency
SMD Surface Mounted Device
SOC System on Chip
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
2 References
[1] DA14681 Datasheet, Dialog Semiconductor
[2] AN-B-041, DA14681 Development kit - Basic: UART with HW handshake, Application note,
Dialog Semiconductor

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DA1468x Development kit - Basic
User manual
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3 Introduction
This document describes the DA14681 Basic Development kit. This kit offers a low cost development
board with basic functionality. The development kit is implemented on a single PCB:
DA14681 Basic: DA14681-00 Basic Kit / 224-18-E
4 System overview
4.1 Features
■Highly integrated Dialog Semiconductor DA1468x SoC
■DA1468x access over UART and/or JTAG without additional external hardware
■Access on all GPIOs provided from the chip, when no sensor board is plugged in
■Push-button for RESET function
■General purpose LED and button
■Current measurement point (pin header)
■Powered from either USB port or coin-cell battery (primary type only, not rechargeable)
■QSPI Flash memory up to 96 MHz clock frequency
■On-board printed inverted-F antenna
■Mechanical switch for conducted RF measurements
■Breakout headers for expansion and signal monitoring
■Integrated programming and debugging interfaces (JTAG/UART)

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4.2 General description
Figure 1 - DA1468x Basic development kit
The Basic development kit is based on the DA1468x SoC in an aQFN60 package. The highlighted
sections of the system are:
1. DA1468x Dialog Semiconductor processor and interfaces.
2. QSPI Flash memory (U9 or U2): only for DA14681 devices.
3. USB port (USB2) with mini-USB connector. This is the evaluation, power supply and debugging
port of the development kit. It provides the power to the development kit and the data bus for the
Segger debugging processor.
4. Debugging processor (U4): This is an Atmel SAM3U2CA microcontroller that establishes the
communication between the Dialog SoC and the user’s PC.
5. Voltage translation (U3): It is used for translating the voltage level of SoC debugging signals to
the voltage level of the debugging processor. In this way any leakage currents are minimised.
6. Breakout headers
a. J3/J4: Most DA1468x GPIO signals are routed here.
b. J6: Ports P1_1 and P2_2 are routed here.
7. Power management section.
J3
J4
J9
J12
J13
J12
J15
U4
U8
U8
U9
USB
PORT
U3
J6

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U4
USB to
UART & JTAG
(SAM3U2A/Segger)
J13
UART
P1_3
P2_3
SWDIO/P0_6
SWCLK/P2_4
USB2
u_tx
u_rx
u_rts
u_cts
P1_5
P1_6
J3/J4
Breakout headers
reset
Key/LEDs
U3
Voltage
translator
(TXB106PW)
UART
bus
swdio
swclk
U1
Dialog
DA1468x/
DA1510x
QSPI
16 MHz
PIFA
Antenna
32 kHz
VLDO3 V
BAT
Figure 2 - Block diagram of DA1468x Basic development kit
The Basic development kit supports, DA14681 SoCs from Dialog Semiconductor. This is achieved by
using the same board layout and populating different versions of the SoC.

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5 Basic development kit system
5.1 Overview
Board name / number:
DA146x DevKT-B_vE / 224-18-E
SoC:
DA1468x in an aQFN60 package
Flash memory:
W25Q80EW (8Mbit) QSPI Flash Memory, WLCSP package - default
W25Q16DW (16M-bit) QSPI Flash Memory, (not populated) - optional
1.8 V power supply (default)
3.0 V power supply (optional)
Clock inputs:
16 MHz crystal
32 kHz crystal
Ports:
USB port for debugging purposes (no charging)
Interfaces:
UART - JLink CDC UART Port (listed under Ports in Device Manager)
JTAG - JLink Driver (listed under Universal Serial Bus Controllers in Device Manager)
Connectivity –Expansion connectors:
DA1468x Sensor board can be plugged directly on breakout headers J3, J4, J6.
Power source selection:
LDO with options for 1.8 V, 3.0 V (default) or 3.3 V (USB powered)
CR2032 coin-cell battery

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5.2 DA1468x system
The DA1468x is a flexible System-on-Chip combining an application processor, memories,
cryptography engine, power management unit, digital and analog peripherals and a radio transceiver.
The DA1468x is based on an ARM®Cortex®-M0 CPU delivering up to 84 DMIPS and provides a
flexible memory architecture, enabling code execution from embedded memory (RAM, ROM) or non-
volatile memory (OTP or external Quad-SPI Flash memory for DA14681). The advanced power
management unit of the DA1468x enables it to run from primary and secondary batteries, as well as
provide power to external devices.
An on-chip PLL enables on-the-fly tuning of the system clock between 32 kHz and 96 MHz to meet
high processing requirements.
Figure 3: DA1468x system schematic
The DA1468x SoC power management subsystem consists of:
VBUS: Battery charger input as well as USB bus voltage. A decoupling capacitor equal or less than
4.7 F is placed close to VBUS pin.
VBAT1: Battery connection. A 1 F decoupling capacitor (C10), is required close to the pin (0402
package, 6.3 V). Voltage range for VBAT1 is 1.7 V to 4.75 V.
VBAT2: Input of the SIMO DC-DC converter. It is shorted externally with VBAT1. A 1 F decoupling
capacitor (C11) is required next to the pin (0402 package, 6.3 V).
V33: Output voltage rail (3.3 V). A ceramic decoupling capacitor of 4.7 F (C3), (0402 package,
6.3 V) is placed. V33 cannot be turned off.
SIMO DC-DC converter outputs: V18, V18P, V12, V14. The inductor needed for DC-DC operation
is placed externally. A low DCR inductor (L1) of 470 nH, 0805 is connected on LX/ LY pins.
V18, V18P: Power rails (1.8 V) for supplying external devices, even when the system is in sleep
mode. Decoupling ceramic capacitors (C4, C5) of 10 F (0603 package, 16 V), are placed as close
R98
10.0k
R2
1
R31 33
R32 33
Y2
32.768KHZ
Z8 10pF
RST
Z1
TBD
Z2 10pF
C1
1.0uF
BT1
s8421-45r
C3
4.7uF
VBUS
C2
4.7uF
V33
VDDIO
R1
0.1
C11
1.0uF
U1
DA14681_QFN60
ADC3/P0_7
A34
QSPI_D3/P0_4
A4
LY B5
USBN/P1_1 A17
RST
A21
SWDIO/ADC4/P0_6
B8
RFIOp B20
QSPI_D2/P0_3
A1
SOCN B9
QSPI_CS/P0_5
A5
VBAT2 B6
QSPI_VDDIO B2
V12 B3
XTAL_32Kp/P2_0 A23
XTAL_32Km/P2_1 B13
XTAL16Mp A30
XTAL16Mm A29
SOCP A18
V14_RF B18
VDD1V8P B4
LX A11
VDD1V8 A8
V14 A6
QSPI_D1/P0_2
A3 QSPI_D0/P0_1
A2 QSPI_CLK/P0_0
B1
VBUS B7
LED1 B10
USBP/P2_2 A16
V33 A15
VBAT1 A13
ADC0/P1_2
A27 ADC5/P1_0
B15
ADC2/P1_3
B23
ADC1/P1_4
A26
ADC6/P1_5
A28
NTC/P1_6
B12
P1_7
A25
P2_3
A35
P3_0
A37
P3_1
A12
P3_4
A9
P3_5
A20
P3_6
A22
P3_7
B14
P4_0
A24
P4_1
B16
P4_2
B17
P4_3
A31
P4_4
A32
P4_5
A33
P4_6
B22
P4_7
A36
P3_2
A10
P3_3
A7
LED2 A19
LED3 B11
SWCLK/ADC7/P2_4
A14
RFIOm B19
GND
PAD
ESDN
B21
P2_0
P2_1
R6 NP
R5 NP
Y1
16MHz
C7
4.7uF
C6
4.7uF
V14
V12
C8
4.7uFC4
10uF C5 10uF
V18
V18P
C10
1.0uF
Z9
TBD
VBAT-
VBAT+
X16m
SOCn
LED3
LED2
SOCp
LED1
X16p
Z3
TBD
VLDO
P2_2
P1_1
TP30
RST
TP12
VBAT
R92
NP
TP32
V14
TP31
V12
TP44
VDDIO J10
R94
NP.2.2k
TP50
TP51TP53
R3
33
SWCLK_P2_4
P2_3
P44
P45
P46
P47
P35
P34
P40
P41
P42
P43
P32
P31
P30
P37
P36
P03
P02
P01
P00
P33
P12
P10
P07
P06
P05
P04
P17
P16
P15
P14
P13
P23
J1
LP1
BLM18EG471SN1D
R34 33
J5
MM8130-2600RB8
1 2
3 4 5 6
L1
470nH
R99
10M
ANT1
Antenna IFA ty pe

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User manual
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as possible to the V18, V18P pins. V18 is assigned to the external Flash memory. The current
delivery capability of the V18, V18P power rails in active mode is 75 mA, whereas in sleep mode it is
2 mA.
V12: Power rail that supplies the digital core of the DA1468x and delivers up to 50 mA at 1.2 V when
in active mode. A 4.7 F decoupling capacitor (C6), is used (0402 package, 6.3 V).
V14: Power rail that delivers up to 20 mA at 1.4 V and should not be used for supplying external
devices. A 4.7 F decoupling capacitor (C7) is placed close to the V14 pin (0402 package, 6.3 V).
V14_RF: Supply voltage input. It is shorted to V14 on the PCB layout. V14_RF powers the RF
circuits via a number of dedicated internal LDOs. A 4.7 F decoupling capacitor (C8) is placed as
close to the V14_RF pin as possible.
VDDIO: QSPI Flash interface supply voltage. It is connected to the same power rail as the Flash
memory. A 1 F decoupling capacitor (C1) is added. (0402 package, 6.3 V).
5.3 DA1468x pin assignment
All available signals are utilised or extracted on the breakout connectors.
Table 1 provides the pin assignment of the breakout connectors on the Basic development board and
the related pin name on the aQFN60 package of the DA1468x.
Table 1: Basic development kit pin assignment
AQFN60 pin
name
Development kit
signal
Header pin
Comments
P0_0
FL_CLK
J3.4
Only for DA14681SoC.
P0_1
FL_D0
J3.6
P0_2
FL_D1
J3.8
P0_3
FL_D2
J3.10
P0_4
FL_D3
J3.12
P0_5
FL_CS
J3.14
P0_6
SWDIO
J3.16
P0_7
GPIO
J3.18
P1_0
GPIO
J4.4
P1_1
GPIO
J6.2
P1_2
GPIO
J4.6
P1_3
UTX
J4.8
P1_4
GPIO
J4.10
P1_5
LED (D2)
J4.12
Also RTS (through jumper on J13)
P1_6
BUTTON (K1)
J4.14
Also CTS (through jumper on J13)
P1_7
GPIO
J4.16
P2_0
XTAL32P
Option to connect to J4.19 (place R5)
P2_1
XTAL32M
Option to connect to J4.21 (place R6)
P2_2
GPIO
J6.4
P2_3
URX
J3.19
P2_4
SWCLK
J3.20
P3_0
GPIO
J3.3
P3_1
GPIO
J3.5

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AQFN60 pin
name
Development kit
signal
Header pin
Comments
P3_2
GPIO
J3.7
P3_3
GPIO
J3.9
P3_4
GPIO
J3.11
P3_5
GPIO
J3.13
P3_6
GPIO
J3.15
P3_7
GPIO
J3.17
P4_0
GPIO
J4.17
P4_1
GPIO
J4.15
P4_2
GPIO
J4.13
P4_3
GPIO
J4.11
P4_4
GPIO
J4.9
P4_5
GPIO
J4.7
P4_6
GPIO
J4.5
P4_7
GPIO
J4.3
LED1
LED1
On-board LED, not monitored on a break-out
header pin.
LED2
LED2
J4.20
LED3
LED3
J4.18
5.4 Basic development kit jumper settings
Table 2: Default jumper settings on Basic development kit
Header
Jumper position
Function
J1
Not mounted
Pin header for current monitoring. Either measure directly the
voltage drop on R2, or remove R2 and insert an ampere meter
probe on the 2-pin header.
J16
Not mounted, No
jumper allowed
Monitoring for system voltages V12 (core) V14 (Analog/RF).
J9
Mounted 1-2
Mounted 1-2: VLDO produces 3.0 V.
Mounted 2-3: VLDO produces 3.3 V.
Not Mounted: VLDO produces 1.8 V.
J10
Mounted 2-3
Mounted 2-3: DA1468x supplied from VLDO.
Mounted 1-2: DA1468x supplied from battery.
J12
Mounted 1-2 & 3-4
Mounted: connects JTAG signals to debugging processor.
J13
Mounted 1-2 & 3-4
UART connection to Segger JLink serial port. To enable UART
hardware handshakes (RTS/CTS), mount instead the provided
jumper block.
J14
Mounted
P1_5 to LED D2.
Remove jumper to use for RTS or other purpose.
J15
Mounted
Mounted: P1_6 to K1 (button).
Remove jumper to use for CTS or other purpose.

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5.5 Booting from UART
There is only one boot loader option for booting from UART using pins P1_3 (UTX) and P2_3 (URX).
Please note that UART-booting does not support hardware handshake signals (RTS/CTS).
The settings for UART booting are:
Baud rate 57600 Bd
8 bits
No parity
1 stop bit
For more details on booting with UART hardware handshakes enabled, check application note AN-D-
041 (Ref. [2]).
5.6 Crystals
DA1468x SoC has two Digitally Controlled Crystal Oscillators (DCXO), one at 16 MHz (XTAL16M)
and a second at 32.768 kHz (XTAL32K). The 32.768 kHz oscillator has no trimming capabilities and
is used as the clock of the Extended/Deep Sleep modes. The 16 MHz oscillator can be trimmed.
The crystals used on the basic development kit are specified in Table 3 and Table 4.
Table 3: Y1 (16 MHz crystal) characteristics
Reference designator
Value
Part Number
7M-16.000MEEQ-T
Frequency
16 MHz
Accuracy
±10 ppm
Load Capacitance (CL)
10 pF
Shunt Capacitance (C0)
3 pF
Equivalent Series Resistance (ESR)
100 Ω
Drive Level (PD)
50 W
Table 4: Y2 (32 kHz crystal) characteristics
Reference designator
Value
Part Number
ABS07-32.768KHZ-7-T
Frequency
32.768 kHz
Accuracy
±20 ppm
Load Capacitance (CL)
7 pF
Shunt Capacitance (C0)
0.9 pF to 1.2 pF
Equivalent Series Resistance (ESR)
70 kΩ
Drive Level (PD)
0.5 W

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5.7 RF port
DA1468x provides a single-ended RFIO port, matched to 50 . The RF port consists of the RFIOp
and RFIOm pins, where RFIOm is connected to ground. A copper trace with an impedance of 50 
interconnects the RF port and the antenna. A pi-network (Z1, Z2, Z3) is added for antenna matching
purposes.
Figure 4: RF matching circuit must be placed as close as possible to the antenna
The Basic development kit provides an SMD RF switch in series with the printed IFA antenna. The
SMD RF switch is used for conducted RF evaluation/testing. The RF switch type is MM8130-2600
supplied by Murata. Verification of the circuit performance is accomplished by inserting an external
plug in the board-mounted receptacle. This action re-directs the circuit from normal condition to the
plug side. Removing the plug restores the circuit back to its normal condition. Murata offers several
options for a mating plug, MXHS83QH3000 is one possible pigtail option.
Figure 5: RF port, printed antenna and RF switch

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5.8 QSPI Data Flash memory (U9 or U2)
The DA1468xBasic development kit includes an external QSPI Data Flash memory from Winbond.
The W25Q80EW Flash memory supports the standard Serial Peripheral Interface (SPI), Dual/Quad
I/O SPI as well as 2-clock instruction cycle Quad Peripheral Interface (QPI), Serial Clock, Chip
Select, Serial Data I/O0 (DI), I/O1(D0), I/O2 (/WP) and I/O3(/HOLD). QSPI supply is selectable (V33
or V18) and the same supply voltage is also connected to the DA1468x VDDIO pin.
Please note that there are two package options available on the Basic development board. Only one
of these must be assembled:
U9 (default): W25Q80EW. 8 Mbit, lower power and form factor option.
U2 (optional): W25Q16DWSSIG. 16 Mbit QSPI Data Flash memory in a SOIC package.
Figure 6: QSPI Data Flash V33 or V18 selectable power supply
The DA14681 uses the external Flash memory for directly executing code with some help from the
internal cache, or simply for mirroring the contents in RAM during booting (option selectable via the
binary image header).
Termination resistors are placed between the processor and Flash memory. These resistors are not
required, but they are placed there to mitigate any signal integrity issues when additional loads are
present (e.g. logic analyser probes on the breakout headers).
R22
10.0k
R27
0
R26
NP
C9
100nF
P0_4
P0_0
P0_1
U2
W25Q16DWSSIG
CS
1
VCC
8
DO
2
HOLD
7
WP
3
CLK
6
GND
4
DIO
5
DUAL QUAD SPI FLASH
VDDIO
V33
VDDIO
FL_CS
V18
P0_2
P0_3
P0_5
U9
W25Q80EWBYIG
VCC
A1
/CS
A2
/HOLD
B1
DO
B2
CLK
C1
/WP
C2
DI
D1
GND
D2
R35
0

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5.9 Push buttons and user controlled LEDs
Figure 7: Push button and general purpose LED schematic
K1 is connected to P1_6 through a jumper on header J8. Please note that via header J13, P1_6 is
also connected to CTS.
K2 is connected to the RESET line of the SoC.
D1 (White LED): driven from LED1. LED1 is controlled directly from the DA1468x SoC.
D2 (Orange LED): driven from P1_5 through header J5. Please notice that via header J13, P1_5 is
connected also to RTS.
Figure 8: White LED
K1 R7
1.00k
GENERAL PURPOSE BUTTON
P1_6
J8
D2
LO T67K-K1M2-24-Z
21 R6
330
P1_5
J5
TP34
GPLED
GENERAL PURPOSE LED
D1
LUW JLSH-5B8B-I4Q7-EG-LP
2
1
R5
33
VBAT+
WHITE LED
C81
1.0uF
TP35
LED1
LED1

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5.10 Debugging processor (U4)
The debugging port of the DA1468x Basic development kit is USB2. Two debugging ports (JTAG and
UART) are used on the DA1468x SoC.
The USB-to-JTAG and USB-to-UART functions are implemented by the SAM3U2CA processor (U4),
running the Segger JLink-OB firmware. The functions served by U4 are:
Connectivity of PC to DA1468x JTAG port.
Connectivity of PC to DA1468x UART port (full UART is possible but must be enabled on the PC
driver).
Hardware RESET capability through T_RESET signal. Note that the signal T_RESET is active LOW
and therefore is inverted by U7 before reaching the RST pin on DA1468x.
The JTAG operating status is indicated via LED D3.
The SAM3U2CA chip is supplied with 3.3 V from U8. The U8 power status is indicated by LED D5.
J7 is the programming port of U4. The user does not need to access this port. It is only used in
production for programming the Segger firmware and serial number.
Headers J13 and J12, for UART and JTAG respectively, interconnect the debugging processor with
the DA1468x processor.
Figure 9: Debugging processor

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DA1468x Development kit - Basic
User manual
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© 2018 Dialog Semiconductor
5.11 Voltage level translation
The debugging processor U4 is supplied with 3.3 V. When the SoC I/O voltage rail is significantly
less than 3.3 V, a miscommunication may occur, e.g. when a discharged battery supplies the SoC.
To avoid this problem a voltage translation circuitry has been added. The selected chip (TXB0106) is
a 6-bit Bidirectional Voltage Level Translator with automatic direction detection.
Please note that this arrangement presumes that JTAG and UART pins on the DA1468x are always
kept on the default (V33) I/O supply and not for some reason switched to the (optional) V18P levels.
Table 5: Signals using a voltage level translation/isolation chip
Pin name
Signal name
P0_6
SWDIO
P2_4
SWCLK
P1_3
UTX
P2_3
URX
P1_5
RTS
P1_6
CTS
Figure 10: Level translator circuit
5.12 Leakage currents during power measurement
Leakage currents can occur through the UART and JTAG interface pins during sleep mode. For
measuring the real power consumption during sleep modes (especially Hibernation mode), the UART
and JTAG can be isolated from the rest of the (debugging) circuit by removing the jumpers from J13
and J12 for UART and JTAG respectively.
5.13 UART header (J13)
J13 interconnects DA1468x SoC UART signals with U4, the debugging processor.
R33
100.0k
J13
12 34
6 5
78 910
P2_3
P1_6
P1_3
P1_5
U7
NC7SZ04P5X
NC
1
I
2
GND
3O4
VCC 5
T_SWDIO
T_SWCLK
T_RTS
T_CTS
T_TX
T_RX
TP79 3.3V
JTAG
J12
1 2
3 4
TP49
SWCLK
SWDIO
SWCLK
TP47
SWDIO
SWCLK_P2_4
SWDIO_P0_6
T_RESET
R96
NP
R97
0V33BUF
3.3V
U3
TXB0106PWR
A1
1VCCA
2
A2
3
A3
4
A4
5
A5
6
A6
7
OE
8GND 9
B6 10
B5 11
B4 12
B3 13
B2 14
VCCB 15
B1 16
RST C14
1nF
C13
100pF
C12
100nF
C15
100nF
SWDIO
SWCLK
CTS
RTS
TX
RX
VOLTAGE LEVEL TRANSLATOR
VBUS2
-
+
U6
LMV321AS5X
1
3
4
52
V33
LP3
BLM18EG471SN1D
R4 0
RESET
T_RESET
R72
0

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DA1468x Development kit - Basic
User manual
Revision 1.4
26-March-2018
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Figure 11: UART header (J13)
By default, only UTX and URX signals are placed/enabled. RTS and CTS are multiplexed with other
functions. For a full UART functionality, a jumper block must be placed on top of J13. For more
details, please refer to application note AN-B-041 (Ref. [2]).
Table 6: DA1468x pin assignment of UART signal
aQFN60 pin name
Development kit signal
Also used for
P1_3
UTX
P2_3
URX
P1_5
RTS
LED via J14
P1_6
CTS
K1 push button via J15
Full UART configuration is supported by connecting RTS and CTS, with a special jumper block
placed on top of J13. In this configuration, jumpers should be removed from J14 and J15. In this way
signals P1_5 and P1_6 are removed from LED D2 and key K1 (see Figure 12)
Please note that full handshake UART is not supported for booting. For more details, refer to
application note AN-B-041 (Ref. [2]).
Figure 12: Full UART hardware configuration
J13
12 34
6 5
78 910
P2_3
P1_6
P1_3
P1_5
CTS
RTS
TX
RX

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DA1468x Development kit - Basic
User manual
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5.14 Power section
USB2
J3/J4
Breakout headers
U1
Dialog Semi
DA1468x/
DA1510x
U6
LDO
Coin
Cell
2032
VLDO
BAT1
J10 VBAT
VBUS
SOCP
R1
U4
Debugging
processor
U8
3.3V
Figure 13: Basic development kit power section
DA1468x basic development kit can be supplied either from USB port or Coin Cell battery. For USB
port power options are:
Through VLDO voltage regulator U5. The voltage regulator feeds VBAT pin of SoC.
Though VBUS pin of SoC. In this case, nothing must be connected on the VBAT port.
Power input is set from header J10 jumper position.
Table 7: DA1468x SoC power options
J10 Header
DA1468x SoC power input
Comments
Mounted 1-2
VBAT supplied from Coin Battery
CR2032 coin cell battery.
Mounted 2-3
VBAT supplied from VLDO
3.3 V, 3.0 V or 1.8 V
USB port: Mini-USB connector. This is the evaluation, power supply and debugging port of the
development kit. It provides power to the development kit and the data bus for the Segger debugging
processor.
U5: This LDO can generate an output voltage of 3.3 V, 3.0 V or 1.8 V. For 1.8 V remove the jumper
on header J9 (see Figure 14). By default the output voltage (VLDO) is 3.0 V.

UM-B-066
DA1468x Development kit - Basic
User manual
Revision 1.4
26-March-2018
CFR0012
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© 2018 Dialog Semiconductor
Figure 14: Location of jumper J9 and LDOs U5, U8
All voltages can be monitored by probing breakout headers J3 and J4.
Note: The coin cell battery does not supply the debugging processor. So when the USB cable is
unplugged, no debugging ports will be available (JTAG or UART).
5.14.1 Battery options
The Basic development kit uses a CR2032 coin cell battery (primary, non-rechargeable battery). It is
possible to externally connect other voltage sources or batteries, as long as the voltage is within the
operating range of VBAT. Please note that charging a rechargeable battery is not supported.
Figure 15: Typical CR2032 (non-rechargeable) coin cell battery