Nxp semiconductors Lpc824m201jhi33 User manual

UM10800

LPC82x User manual

Rev. 1.2 — 5 October 2016 User manual

Document information

Info Content

Keywords LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20,

LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820

Abstract LPC82x User manual

User manual Rev. 1.2 — 5 October 2016 2 of 487

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10800

LPC82x User manual

Revision history

Rev Date Description

1.2 20161005 LPC82x User manual.

Modifications: •Updated Table 383 “Error codes”: added error codes 0x0006 0009 and 0x0006 000A.

•Added bits: 24 - ADC_RST_N; 29 - DMA_RST_N to Table 23 “Peripheral reset control register

(PRESETCTRL, address 0x4004 8004) bit description”.

•Added Section 12.5.7 “Channel chaining”.

1.1 20160524 LPC82x User manual.

Modifications: •Removed internal comments from Section 16.6.24 “SCT event enable registers 0 to 7”

•Changed main clock to system clock in the first paragraph in Section 26.5.1.1 “Param0: system PLL

input frequency and Param1: expected system clock”.

•Updated Section 25.6.2 “IAP commands”.

•Updated Table 308 “LPC82x flash configuration”: corrected the page numbers of sectors 21 - 31.

•Updated Section 16.6 “Register description” to fix the polarity for REGMODE.

–REGMODEn = 0: Registers operate as match and reload registers.

–REGMODEn = 1: Registers operate as capture and capture control registers.

•Changed signature generation start address (corresponds to AHB byte address bits[20:4]) to

signature generation start address (corresponds to AHB byte address bits[18:2]).

•Added a note to Table 236 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit

description” and Table 237 “SCT DMA 1 request register (DMAREQ1, address 0x5000 C060) bit

description”.

•Changed the ISP entry pin in Section 31.5.2 “Debug connections for SWD” to PIO0_20; was

PIO0_1.

•Added reserved blocks in Table 222 “Register overview: State Configurable Timer SCT/PWM (base

address 0x5000 4000)”: 0x220 to 0x2FF before EV0_STATE 0x340 to 0x4FF before OUT0_SET

1 20140918 Initial revision. LPC82x User manual.

User manual Rev. 1.2 — 5 October 2016 3 of 487

1.1 Introduction

The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and

8 KB of SRAM.

The peripheral complement of the LPC82x includes a CRC engine, four I2C-bus

interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,

self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a

DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through

a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.

Remark: For additional documentation, see Section 35.2 “References”.

1.2 Features

•System:

–ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to

30 MHz with single-cycle multiplier and fast single-cycle I/O port.

–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

–System tick timer.

–AHB multilayer matrix.

–Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

–Micro Trace Buffer (MTB)

•Memory:

–Up to 32 KB on-chip flash programming memory with 64 Byte page write and

erase. Code Read Protection (CRP) supported.

–8 KB SRAM.

•ROM API support:

–bootloader.

–On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power

profiles) and integer divide.

–Flash In-Application Programming (IAP) and In-System Programming (ISP).

•Digital peripherals:

–High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to

32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter. GPIO direction

control supports independent set/clear/toggle of individual bits.

–High-current source output driver (20 mA) on four pins.

–High-current sink driver (20 mA) on two true open-drain pins.

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Chapter 1: LPC82x Introductory information

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Chapter 1: LPC82x Introductory information

–GPIO interrupt generation capability with boolean pattern-matching feature on

eight GPIO inputs.

–Switch matrix for flexible configuration of each I/O pin function.

–CRC engine.

–DMA with 18 channels and 9 trigger inputs.

•Timers:

–State Configurable Timer (SCTimer/PWM) with input and output functions

(including capture and match) for timing and PWM applications.

–Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

–Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,

low-frequency internal oscillator, or an external clock input in the always-on power

domain.

–Windowed Watchdog timer (WWDT).

•Analog peripherals:

–One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports

two independent conversion sequences.

–Comparator with four input pins and external or internal reference voltage.

•Serial peripherals:

–Three USART interfaces with pin functions assigned through the switch matrix and

one common fractional baud rate generator.

–Two SPI controllers with pin functions assigned through the switch matrix.

–Four I2C-bus interfaces. One I2C supports Fast-mode plus with 1 Mbit/s data rates

on two true open-drain pins and listen mode. Three I2Cs support data rates up to

400 kbit/s on standard digital pins.

•Clock generation:

–12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

–Crystal oscillator with an operating range of 1 MHz to 25 MHz.

–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

–PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input, or the internal RC oscillator.

–Clock output function with divider that can reflect all internal clock sources.

•Power control:

–Integrated PMU (Power Management Unit) to minimize power consumption.

–Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

–Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

and I2C peripherals.

–Timer-controlled self-wake-up from Deep power-down mode.

–Power-On Reset (POR).

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Chapter 1: LPC82x Introductory information

–Brownout detect (BOD).

•Unique device serial number for identification.

•Single power supply (1.8 V to 3.6 V).

•Operating temperature range -40 °C to +105 °C.

•Available in a HVQFN33 (5x5) package.

1.3 Ordering options

1.4 General description

1.4.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in

the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points.

The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO

access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1.

The core includes a single-cycle multiplier and a system tick timer (SysTick).

Table 1. Ordering information

Type number Package

Name Description Version

LPC824M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 5 5 0.85 mm n/a

LPC822M101JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 5 5 0.85 mm n/a

LPC824M201JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

LPC822M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Table 2. Ordering options

Type number Flash/

KB SRAM/

KB USART I2CSPI ADC

channels Comparator GPIO Package

LPC824M201JHI33 32 8 3 4 2 12 Y 29 HVQFN33

LPC822M101JHI33 16 4 3 4 2 12 Y 29 HVQFN33

LPC824M201JDH20 32 8 3 4 2 5 Y 16 TSSOP20

LPC822M101JDH20 16 4 3 4 2 5 y 16 TSSOP20

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Chapter 1: LPC82x Introductory information

1.5 Block diagram

Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or

have DMA request lines.

Fig 1. LPC82x block diagram

SRAM

4/8 KB

ARM

CORTEX-M0+

TEST/DEBUG

INTERFACE

FLASH

16/32 KB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

RESET, CLKIN

clocks and

controls

LPC82xM

aaa-014399

slave

slave slave

ROM

slave

CRC

slave master

PIN INTERRUPTS/

PATTERN MATCH

AHB-LITE BUS

IRC

WDOsc

BOD

POR

SPI0/1

USART0/1/2

SDA

SCL

SCT_PIN[3:0]

29 x

PIO0

29 x

WWDT

IOCON

PMU

SELF

WAKE-UP TIMER

MULTI-RATE TIMER

I2C0/1/2/3

SCTIMER/

PWM

SWITCH

MATRIX

SCT_OUT[6:0]

COMPARATOR

XTALIN

XTALOUT

ACMP_O

SYSCON

RXD, CTS

TXD, RTS

ACMP_I[4:1]

VDDCMP

ADC

ADC_[11:0]

SCK, SSEL

MISO, MOSI

ALWAYS-ON POWER DOMAIN

XTAL

SCLK

CLKOUT

SWCLK, SWD

INPUT MUX

DMA

User manual Rev. 1.2 — 5 October 2016 7 of 487

2.1 How to read this chapter

The memory mapping is identical for all LPC82x parts. Different LPC82x parts support

different flash and SRAM memory sizes.

2.2 General description

The LPC82x incorporates several distinct memory regions. Figure 2 shows the overall

map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals.

Each peripheral is allocated 16 KB of space simplifying the address decoding.

The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and

sleep mode control, are located on the private peripheral bus.

The GPIO port and pin interrupt/pattern match registers are accessed by the ARM

Cortex-M0+ single-cycle I/O enabled port (IOP).

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Chapter 2: LPC82x memory mapping

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Chapter 2: LPC82x memory mapping

2.2.1 Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC82x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4.

The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.

Fig 2. LPC82x Memory mapping

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 8000

0x4005 C000

0x4006 0000

0x4006 4000

0x4006 8000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

MRT

reserved

12-bit ADC

self wake-up timer

reserved

WWDT

analog comparator

PMU

30 - 31 reserved

0x4002 C000

0x4003 0000

0x4003 4000

DMA TRIGMUX

input mux

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1FFF 0000

0x1FFF 3000

0x2000 0000

0x5000 0000

0x5000 4000

0xFFFF FFFF

reserved

0x4000 0000

0x4008 0000

APB peripherals

CRC

0x5000 8000

SCTimer/PWM

0x5000 C000

0xA000 0000

GPIO

0xA000 4000

0xA000 8000

GPIO PINT

0x1000 1000

4 KB SRAM0

0x1001 2000

4 KB SRAM1

0x1000 0000

LPC82x

0x0000 8000

32 KB on-chip flash

12 KB boot ROM

0x1400 0000

0x1400 1000

4 KB MTB registers

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

DMA

reserved

flash controller

SPI0

reserved

switch matrix

IOCON

system control (SYSCON)

19 reserved

0x4005 4000

20 I2C0

21 I2C1

23 SPI1

24 reserved

0x4006 C000

0x4007 0000

USART0

26 USART1

27 USART2

0x4007 4000

28 I2C2

0x4007 8000

29 I2C3

reserved

0xE000 0000

0xE010 0000

private peripheral bus

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3.1 How to read this chapter

The bootloader is identical for all parts.

3.2 Features

•12 KB on-chip boot ROM

•Contains the bootloader with In-System Programming (ISP) facility and the following

APIs:

–In-Application Programming (IAP) of flash memory

–Power profiles for optimizing power consumption and system performance

–USART driver

–ADC driver

–SPI driver

–I2C driver

–Integer divide routines

3.3 Basic configuration

The clock to the ROM is enabled by default. No configuration is required to use the ROM

APIs.

3.4 Pin description

When the ISP entry pin is pulled LOW on reset, the part enters ISP mode and the ISP

command handler starts up. In ISP mode, pin PIO0_0 is connected to function U0_RXD

and pin PIO0_4 is connected to function U0_TXD on the USART0 block.

3.5 General description

3.5.1 Bootloader

The bootloader controls initial operation after reset and also provides the means to

accomplish programming of the flash memory via USART. This could be initial

programming of a blank device, erasure and re-programming of a previously programmed

device, or programming of the flash memory by the application program in a running

system.

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Chapter 3: LPC82x Boot ROM

Rev. 1.2 — 5 October 2016 User manual

Table 3. Pin location in ISP mode

ISP entry pin USART RXD USART TXD

PIO0_12 PIO0_0 PIO0_4

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Chapter 3: LPC82x Boot ROM

The bootloader code is executed every time the part is powered on or reset. The

bootloader can execute the ISP command handler or the user application code. A LOW

level after reset at the ISP entry pin is considered as an external hardware request to start

the ISP command handler via USART.

For details on the boot process, see Section 3.6.2 “Boot process”.

Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and

the memory content in this area is retained during reset. SRAM memory is not retained

when the part powers down or enters Deep power-down mode.

Assuming that power supply pins are at their nominal levels when the rising edge on

RESET pin is generated, it may take up to 3 ms before the ISP entry pin is sampled and

the decision whether to continue with user code or ISP handler is made. The bootloader

performs the following steps (see Figure 4):

1. If the watchdog overflow flag is set, the bootloader checks whether a valid user code

is present. If the watchdog overflow flag is not set, the ISP entry pin is checked.

2. If there is no request for the ISP command handler execution (ISP entry pin is

sampled HIGH after reset), a search is made for a valid user program.

3. If a valid user program is found then the execution control is transferred to it. If a valid

user program is not found, the bootloader attempts to load a valid user program via

the USART interface.

Remark: The sampling of pin the ISP entry pin can be disabled through programming

flash location 0x0000 02FC (see Section 25.5.3 “Code Read Protection (CRP)”).

3.5.2 ROM-based APIs

Once the part has booted, the user can access several APIs located in the boot ROM to

access the flash memory, optimize power consumption, and operate the USART and I2C

peripherals.

The structure of the boot ROM APIs is shown in Figure 3.

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Chapter 3: LPC82x Boot ROM

Fig 3. Boot ROM structure

Ptr to ROM Driver table

Reserved

…

Ptr to Device Table n

Ptr to Function 2

Ptr to Function 0

Ptr to Function 1

…

Ptr to Function n

Device n

ROM Driver Table

0x1FFF 1FF8

+0x0

+0x4

+0x8

+0x10

+0x14

+0xC

Device 3

Power profiles API function table

IAP calls

Ptr to IAP

0x1FFF 1FF1

Pointer to power profiles

function table

+0x18

Device 7

SPI driver routines function table

Device 8

ADC driver routines function table

Device 9

USART driver routines function table

Reserved

+0x1C

Pointer to SPI driver function table

+0x20

Pointer to ADC driver function table

+0x24

Pointer to USART driver

routines function table

+0x28

Reserved

+0x2C

Reserved

Device 4

Integer Divide routines function table

Pointer to 32-bit integer divide routines

Pointer to I2C driver routine function

table

Device 5

I2C driver routines function table

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Chapter 3: LPC82x Boot ROM

The boot rom structure should be included as follows:

typedef struct {

const uint32_t reserved0; /*!< Reserved */

const uint32_t reserved1; /*!< Reserved */

const uint32_t reserved2; /*!< Reserved */

const PWRD_API_T *pPWRD; /*!< Power API function table base address */

const ROM_DIV_API_T *divApiBase; /*!< Divider API function table base address */

const I2CD_API_T *pI2CD;/*!< I2C driver routines functions table */

const uint32_t reserved5; /*!< Reserved */

const SPID_API_T *pSPID; /*!< SPI driver API function table base address */

const ADCD_API_T *pADCD; /*!< ADC driver API function table base address */

const UARTD_API_T *pUARTD; /*!< USART driver API function table base address */

} LPC_ROM_API_T;

#define ROM_DRIVER_BASE (0x1FFF1FF8UL)

3.6 Functional description

3.6.1 Memory map after any reset

The boot block is 12 KB in size. The boot block is located in the memory region starting

from the address 0x1FFF 0000. The bootloader is designed to run from this memory area,

but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is

described in Section 25.7.2 “Memory and interrupt use for ISP and IAP”. The interrupt

vectors residing in the boot block of the on-chip flash memory also become active after

reset, i.e., the bottom 512 bytes of the boot block are also visible in the memory region

starting from the address 0x0000 0000.

3.6.2 Boot process

During the boot process, the bootloader checks if there is valid user code in flash. The

criterion for valid user code is as follows:

The reserved Cortex-M0+ exception vector location 7 (offset 0x0000 001C in the vector

table) should contain the 2’s complement of the check-sum of table entries 0 through 6.

This causes the checksum of the first 8 table entries to be 0. The bootloader code

checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution

control is transferred to the user code.

Table 4. API calls

API Description Reference

Flash IAP Flash In-Application programming Table 330

Power profiles API Configure system clock and power consumption Table 343

Integer divide routines 32-bit integer divide routines Table 399

I2C driver I2C ROM driver Table 364

SPI driver SPI ROM driver Table 356

ADC driver ADC ROM driver Table 385

UART driver USART ROM driver Table 346

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Chapter 3: LPC82x Boot ROM

If the signature is not valid, the auto-baud routine synchronizes with the host via serial port

USART0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a

response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.

The auto-baud routine measures the bit time of the received synchronization character in

terms of its own frequency (the 12 MHz IRC frequency) and programs the baud rate

generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to

the host. In response, the host should send the same string ("Synchronized<CR><LF>").

The bootloader auto-baud routine looks at the received characters to verify

synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the

host. The host should respond by sending the crystal frequency (in kHz) at which the part

is running. The response is required for backward compatibility of the bootloader code

and, on the LPC800, is ignored. The bootloader configures the part to run at the 12 MHz

IRC frequency.

Once the crystal frequency response is received, the part is initialized and the ISP

command handler is invoked. For safety reasons an "Unlock" command is required before

executing the commands resulting in flash erase/write operations and the "Go" command.

The rest of the commands can be executed without the unlock command. The Unlock

command is required to be executed once per ISP session. The Unlock command is

explained in Table 313 “UART ISP Unlock command”.

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Chapter 3: LPC82x Boot ROM

3.6.3 Boot process flowchart

(1) The boot-code is implementing auto-baud in software.

(2) This step is included for backward compatibility and the response is ignored by the bootloader.

Fig 4. Boot process flowchart

RESET

INITIALIZE

RECEIVE CRYSTAL FREQUENCY (2)

RUN UART ISP COMMAND HANDLER

RUN AUTO-BAUD(1)

CRP1/2/3

ENABLED?

WATCHDOG

FLAG SET?

CRP3/NO_ISP

ENABLED?

ENTER ISP

MODE?

(ISP ENTRY PIN

= LOW)

USER CODE

VALID?

USER CODE

VALID?

AUTO-BAUD

SUCCESSFUL?

EXECUTE INTERNAL

USER CODE

ENABLE DEBUG

yes

nono

boot from

UART

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4.1 How to read this chapter

The NVIC is identical on all LPC82x parts.

4.2 Features

•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.

•Tightly coupled interrupt controller provides low interrupt latency.

•Controls system exceptions and peripheral interrupts.

•The NVIC supports 32 vectored interrupts.

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation using the ARM exceptions SVCall and PendSV (see

Ref. 3).

•Support for NMI.

•ARM Cortex M0+ Vector table offset register VTOR implemented.

4.3 General description

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

4.3.1 Interrupt sources

Table 5 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. Interrupts with the same priority level are

serviced in the order of their interrupt number.

See Ref. 3 for a detailed description of the NVIC and the NVIC register description.

UM10800

Chapter 4: LPC82x Nested Vectored Interrupt Controller

(NVIC)

Rev. 1.2 — 5 October 2016 User manual

Table 5. Connection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

0 SPI0_IRQ SPI0 interrupt See Table 193 “SPI Interrupt Enable read and Set

0x4005 C00C (SPI1)) bit description”.

1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ

2 - Reserved -

3 UART0_IRQ USART0 interrupt See Table 179 “USART Interrupt Enable read and set

0x4006 800C (USART1), 0x4006C00C (USART2)) bit

description”

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

4 UART1_IRQ USART1 interrupt Same as UART0_IRQ

5 UART2_IRQ USART2 interrupt Same as UART0_IRQ

6 - Reserved -

7 I2C1_IRQ I2C1 interrupt See Table 209 “Interrupt Enable Clear register

(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C

(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit

description”.

8 I2C0_IRQ I2C0 interrupt See Table 209 “Interrupt Enable Clear register

(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C

(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit

description”.

9 SCT_IRQ State configurable timer

interrupt EVFLAG SCT event

10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt.

GFLAG0

GFLAG1

GFLAG2

GFLAG3

11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit

12 WDT_IRQ Windowed watchdog timer

interrupt WARNINT - watchdog warning interrupt

13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level

14 FLASH_IRQ flash interrupt -

15 WKT_IRQ Self-wake-up timer interrupt ALARMFLAG

16 ADC_SEQA_IRQ ADC sequence A

completion -

17 ADC_SEQB_IRQ ADC sequence B

completion -

18 ADC_THCMP_IRQ ADC threshold compare -

19 ADC_OVR_IRQ ADC overrun -

20 DMA_IRQ DMA interrupt -

21 I2C2_IRQ I2C2 interrupt See Table 209 “Interrupt Enable Clear register

(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C

(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit

description”.

22 I2C3_IRQ I2C3 interrupt See Table 209 “Interrupt Enable Clear register

(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C

(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit

description”.

23 - Reserved -

24 PININT0_IRQ Pin interrupt 0 or pattern

match engine slice 0

interrupt

PSTAT - pin interrupt status

25 PININT1_IRQ Pin interrupt 1 or pattern

match engine slice 1

interrupt

PSTAT - pin interrupt status

Table 5. Connection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

4.3.2 Non-Maskable Interrupt (NMI)

The part supports the NMI, which can be triggered by an peripheral interrupt or triggered

by software. The NMI has the highest priority exception other than the reset.

You can set up any peripheral interrupt listed in Table 5 as NMI using the NMISRC

NMI exception and normal interrupt, disable the interrupt in the NVIC when you configure

it as NMI.

4.3.3 Vector table offset

The vector table contains the reset value of the stack pointer and the start addresses, also

called exception vectors, for all exception handlers. On system reset, the vector table is

located at address 0x0000 0000. Software can write to the VTOR register in the NVIC to

relocate the vector table start address to a different memory location. For a description of

the VTOR register, see the ARM Cortex-M0+ documentation (Ref. 3).

26 PININT2_IRQ Pin interrupt 2 or pattern

match engine slice 2

interrupt

PSTAT - pin interrupt status

27 PININT3_IRQ Pin interrupt 3 or pattern

match engine slice 3

interrupt

PSTAT - pin interrupt status

28 PININT4_IRQ Pin interrupt 4 or pattern

match engine slice 4

interrupt

PSTAT - pin interrupt status

29 PININT5_IRQ Pin interrupt 5 or pattern

match engine slice 5

interrupt

PSTAT - pin interrupt status

30 PININT6_IRQ Pin interrupt 6 or pattern

match engine slice 6

interrupt

PSTAT - pin interrupt status

31 PININT7_IRQ Pin interrupt 7 or pattern

match engine slice 7

interrupt

PSTAT - pin interrupt status

Table 5. Connection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

User manual Rev. 1.2 — 5 October 2016 18 of 487

NXP Semiconductors UM10800

Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

4.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

Table 6. Register overview: NVIC (base address 0xE000 E000)

Name Access Address

offset Description Reset

value Reference

ISER0 RW 0x100 Interrupt Set Enable Register 0. This register allows enabling

interrupts and reading back the interrupt enables for specific

peripheral functions.

0Table 7

- - 0x104 Reserved. - -

ICER0 RW 0x180 Interrupt Clear Enable Register 0. This register allows disabling

interrupts and reading back the interrupt enables for specific

peripheral functions.

0Table 8

- - 0x184 Reserved. 0 -

ISPR0 RW 0x200 Interrupt Set Pending Register 0. This register allows changing the

interrupt state to pending and reading back the interrupt pending

state for specific peripheral functions.

0Table 9

- - 0x204 Reserved. 0 -

ICPR0 RW 0x280 Interrupt Clear Pending Register 0. This register allows changing the

interrupt state to not pending and reading back the interrupt pending

state for specific peripheral functions.

0Table 10

- - 0x284 Reserved. 0 -

IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the

current interrupt active state for specific peripheral functions. 0Table 11

- - 0x304 Reserved. 0 -

IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority