Cypress Semiconductor CY62138FV30 User manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-08029 Rev. *E Revised March 26, 2007
CY62138FV30 MoBL®
2-Mbit (256K x 8) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Functional Description [1]
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE1
HIGH or CE2LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO0through IO7) is then written into the location
specified on the address pins (A0through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO0through IO7) are placed
in a high impedance state when the device is deselected (CE1
HIGH or CE2LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2HIGH and WE
LOW).
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
WE
OE
A13
A14
A15 A16
ROW DECODER
COLUMN DECODER
256K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A17
CE1
CE2
A12
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
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Document #: 001-08029 Rev. *E Page 2 of 13
CY62138FV30 MoBL®
Pin Configuration [2]
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (µA)
f = 1 MHz f = fmax
Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max
CY62138FV30LL 2.2 3.0 3.6 45 1.6 2.5 13 18 1 5
A15
V
CC
A13
A
12
A5
CE2
WE A7
IO4
IO5
A4
IO6
IO7
V
SS
A
11
A10
A1
V
SS
IO0
A2
A8
A
6
A3
A0
V
CC
IO1
IO 2
IO 3
A
17
NC
A16
CE1
OE
A9A14
D
E
B
A
C
F
G
H
NC
Top View
36-Ball VFBGA
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC/TSOP II
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
VSS
VCC
CE
2
WE
OE
CE1
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO2
IO1
GND
IO7
IO4
IO5
IO6
IO0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
A17
A10
IO3
A1
A0
A3
A2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO2
IO1
GND
IO7
IO4
IO5
IO6
IO0
CE1
A11
A59
10
32
1
2
3
4
5
6
7
8
CE2
A15
A17
A10
IO3
A1
A0
A3
A2
26
25
26
27
Note
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.
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Document #: 001-08029 Rev. *E Page 3 of 13
CY62138FV30 MoBL®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Supply Voltage to Ground
Potential........................................................... –0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State [4, 5].......................................... –0.3V to 3.9V
DC Input Voltage [4, 5] .......................................–0.3V to 3.9V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Product Range Ambient
Temperature VCC [6]
CY62138FV30LL Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions 45 ns Unit
Min Typ [3] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 V
IOH = –1.0 mA, VCC >2.70V 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 V
IOL = 2.1 mA, VCC >2.70V 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3V V
VCC= 2.7V to 3.6V 2.2 VCC + 0.3V V
VIL Input LOW Voltage VCC = 2.2V to 2.7V For BGA package –0.3 0.6 V
VCC= 2.7V to 3.6V –0.3 0.8 V
VCC = 2.2V to 3.6V For other packages –0.3 0.6 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage Current GND < VO <VCC,
output disabled
–1 +1 µA
ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
13 18 mA
f = 1 MHz 1.6 2.5
ISB1 Automatic CE Power Down
Current CMOS Inputs
CE1> VCC – 0.2V or CE2< 0.2V,
VIN > VCC – 0.2V, VIN <0.2V),
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60V
15µA
ISB2 [7] Automatic CE Power Down
Current CMOS Inputs
CE1> VCC – 0.2V or CE2 <0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
15µA
Capacitance (For all packages) [8]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ.)
10 pF
COUT Output Capacitance 10 pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Only chip enables (CE1and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
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Document #: 001-08029 Rev. *E Page 4 of 13
CY62138FV30 MoBL®
Thermal Resistance [8]
Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 x 4.5
inch, two layer printed circuit
board
44.53 38.49 44.16 59.72 50.19 °C/W
ΘJC Thermal Resistance
(Junction to Case)
24.05 17.66 11.97 15.38 14.59 °C/W
AC Test Loads and Waveforms
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ [3] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR [7] Data Retention Current VCC = 1.5V,
CE1> VCC − 0.2V or CE2< 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
14µA
tCDR [8] Chip Deselect to Data Retention Time 0 ns
tR [9] Operation Recovery Time tRC ns
Data Retention Waveform [10]
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE
Notes:
9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
10. CE is the logical combination of CE1and CE2. When CE1is LOW and CE2 is HIGH, CE is LOW; when CE1is HIGH or CE2is LOW, CE is HIGH.
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Document #: 001-08029 Rev. *E Page 5 of 13
CY62138FV30 MoBL®
Switching Characteristics (Over the Operating Range) [11]
Parameter Description
45 ns
Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to Low-Z [12] 5ns
tHZOE OE HIGH to High-Z [12,13] 18 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z [12] 10 ns
tHZCE CE1 HIGH or CE2 LOW to High-Z [12, 13] 18 ns
tPU CE1 LOW and CE2 HIGH to Power Up 0ns
tPD CE1 HIGH or CE2 LOW to Power Down 45 ns
Write Cycle [14]
tWC Write Cycle Time 45 ns
tSCE CE1 LOW and CE2 HIGH to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z [12, 13] 18 ns
tLZWE WE HIGH to Low-Z [12] 10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the ““AC Test Loads and Waveforms” on page 4” .
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
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Document #: 001-08029 Rev. *E Page 6 of 13
CY62138FV30 MoBL®
Switching Waveforms
Read Cycle 1 (Address transition controlled) [15, 16]
Read Cycle No. 2 (OE controlled) [10, 16, 17]
Write Cycle No. 1 (WE controlled) [10, 14, 18, 19]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
20
Notes:
15. The device is continuously selected. OE, CE1= VIL, CE2= VIH.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE1transition LOW and CE2transition HIGH.
18. Data IO is high impedance if OE = VIH.
19. If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
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Document #: 001-08029 Rev. *E Page 7 of 13
CY62138FV30 MoBL®
Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]
Write Cycle No. 3 (WE controlled, OE LOW) [10, 19]
Truth Table
CE1CE2WE OE Inputs/Outputs Mode Power
H X X X High-Z Deselect/Power Down Standby (ISB)
X L X X High-Z Deselect/Power Down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H H H High-Z Output Disabled Active (ICC)
L H L X Data in Write Active (ICC)
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
ADDRESS
CE
DATA IO
WE
DATA VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA IO
NOTE
20
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Document #: 001-08029 Rev. *E Page 8 of 13
CY62138FV30 MoBL®
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free) Industrial
CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free)
CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free)
CY62138FV30LL-45ZXI 51-85056 32-pin TSOP I (Pb-free)
CY62138FV30LL-45SXI 51-85081 32-pin SOIC (Pb-free)
Package Diagrams
Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(36X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85149-*C
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Document #: 001-08029 Rev. *E Page 9 of 13
CY62138FV30 MoBL®
Figure 2. 32-pin TSOP II, 51-85095
Package Diagrams (continued)
51-85095-**
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Document #: 001-08029 Rev. *E Page 10 of 13
CY62138FV30 MoBL®
Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081
Package Diagrams (continued)
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
51-85081-*B
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Document #: 001-08029 Rev. *E Page 11 of 13
CY62138FV30 MoBL®
Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056
Package Diagrams (continued)
51-85056-*D
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Document #: 001-08029 Rev. *E Page 12 of 13
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62138FV30 MoBL®
Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85094-*D
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Document #: 001-08029 Rev. *E Page 13 of 13
CY62138FV30 MoBL®
Document History Page
Document Title: CY62138FV30 MoBL®, 2-Mbit (256K x 8) Static RAM
Document Number: 001-08029
REV. ECN NO. Issue
Date
Orig. of
Change Description of Change
** 463660 See ECN NXR New data sheet
*A 467351 See ECN NXR Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
Changed ball A3 from NC to CE2in 36-ball FBGA pin out
*B 566724 See ECN NXR Converted from Preliminary to Final
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed
pin 24 from CE1to OE and pin 22 from CE to CE1)
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 µA to 1 µA
Changed the ISB2(max) value from 2.5 µA to 5 µA
Changed the ICCDR(typ) value from 0.5 µA to 1 µA and ICCDR(max) value from 2.5
µA to 4 µA
*C 797956 See ECN VKN Added 32-pin SOIC package
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical
characteristics table
*D 809101 See ECN VKN Corrected typo in the Ordering Information table
*E 940341 See ECN VKN Added footnote #7 related to ISB2 and ICCDR
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