Cypress Semiconductor CY62158E User manual

CY62158E MoBL®
8-Mbit (1M x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05684 Rev. *D Revised June 16, 2008
Features
■Very high speed: 45 ns
❐Wide voltage range: 4.5V – 5.5V
■Ultra low active power
❐Typical active current:1.8 mA @ f = 1 MHz
❐Typical active current: 18 mA @ f = fmax
■Ultra low standby power
❐Typical standby current: 2 μA
❐Maximum standby current: 8 μA
■Easy memory expansion with CE1, CE2 and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Offered in Pb-free 44-Pin TSOP II package
Functional Description
The CY62158E MoBL®is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE1 HIGH or
CE2LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight IO
pins (IO0through IO7) is then written into the location specified
on the address pins (A0through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the IO pins.
The eight input and output pins (IO0through IO7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2HIGH and WE
LOW). See the Truth Table on page 8 for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
WE
OE
A13
A14
A15 A16
ROW DECODER
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A17
CE1
CE2
A12
A18 A19
Logic Block Diagram
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 2 of 10
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (μA)
f = 1 MHz f = fmax
Min Typ [2] Max Typ [2] Max Typ [2] Max Typ [2] Max
CY62158ELL 4.5 5.0 5.5 45 1.8 3 18 25 2 8
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19
23
28
25
24
22
21
27
26
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
10
A
11
A
12
A
13
A
15
A
16
A
14
OE
CE
2
A
8
CE
1
WE
NC
NC
IO
0
IO
1
IO
2
IO
3
NC
NC NC
NC
IO
4
IO
5
IO
6
IO
7
NC
NC
V
CC
V
CC
V
SS
V
SS
A
9
10
A
19
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 3 of 10
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential–0.5V to VCC(max) + 0.5V
DC Voltage Applied to Outputs
in High-Z State [3, 4] ........................–0.5V to VCC(max) + 0.5V
DC Input Voltage [3, 4].....................–0.5V to VCC(max) + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Device Range Ambient
Temperature VCC [5]
CY62158ELL Industrial –40°C to +85°C 4.5V – 5.5V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -45 UnitMin Typ [2] Max
VOH Output HIGH Voltage IOH = –1 mA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5V V
VIIL Input LOW Voltage VCC = 4.5V to 5.5V –0.5 0.8 V
IIX Input Leakage Current GND <VI< VCC –1 +1 μA
IOZ Output Leakage Current GND <VO <VCC, Output Disabled –1 +1 μA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18 25 mA
f = 1 MHz 1.8 3 mA
ISB1 Automatic CE Power down
Current — CMOS Inputs CE1> VCC− 0.2V, CE2 <0.2V VIN >VCC – 0.2V, VIN < 0.2V)
f = fMAX (Address and Data Only),
f = 0 (OE, and WE), VCC = VCCmax
28μA
ISB2 [6] Automatic CE Power-down
Current — CMOS Inputs CE1> VCC – 0.2V or CE2< 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCCmax
28μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75.13 °C/W
ΘJC Thermal Resistance
(Junction to Case) 8.95 °C/W
Notes
3. VIL(min) = –2.0V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.
6. Only chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 4 of 10
Figure 2. AC Test Loads and Waveforms
Parameters 5.0V Unit
R1 1838 Ω
R2 994 Ω
RTH 645 Ω
VTH 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [2] Max Unit
VDR VCC for Data Retention 2 V
ICCDR [6] Data Retention Current VCC = VDR
CE1> VCC −0.2V, CE2< 0.2V,
VIN > VCC −0.2V or VIN < 0.2V
8μA
tCDR [7] Chip Deselect to Data
Retention Time 0ns
tR [8] Operation Recovery Time tRC ns
Figure 3. Data Retention Waveform
3V
VCC
OUTPUT
R2
100 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
VCC(min)
VCC(min)
tCDR VDR >2.0 V
DATA RETENTION MODE
tR
CE1
VCC
CE2
or
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 5 of 10
Switching Characteristics
Over the Operating Range [9]
Parameter Description 45 ns Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to Low Z [10] 5ns
tHZOE OE HIGH to High Z [10, 11] 18 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z [10] 10 ns
tHZCE CE1 HIGH or CE2 LOW to High Z [10, 11] 18 ns
tPU CE1 LOW and CE2 HIGH to Power Up 0 ns
tPD CE1 HIGH or CE2 LOW to Power Down 45 ns
Write Cycle [12]
tWC Write Cycle Time 45 ns
tSCE CE1 LOW and CE2 HIGH to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High Z [10, 11] 18 ns
tLZWE WE HIGH to Low Z [10] 10 ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
10.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12.The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals
can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 6 of 10
Switching Waveforms
Figure 4 shows address transition controlled read cycle waveforms.[13, 14]
Figure 4. Read Cycle No. 1
Figure 5 shows OE controlled read cycle waveforms.[14, 15]
Figure 5. Read Cycle No. 2
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE1
ADDRESS
CE2
DATA OUT
SUPPLY
CURRENT
VCC
Notes
13.Device is continuously selected. OE, CE1= VIL, CE2= VIH.
14.WE is HIGH for read cycle.
15.Address valid before or similar to CE1transition LOW and CE2transition HIGH.
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 7 of 10
Figure 6 shows WE controlled write cycle waveforms.[12, 16, 17]
Figure 6. Write Cycle No. 1
Figure 7 shows CE1or CE2controlled write cycle waveforms.[12, 16, 17]
Figure 7. Write Cycle No. 2
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
t
HZOE
VALID DATA
NOTE 18
CE1
ADDRESS
CE2
WE
DATA IO
OE
tWC
VALID DATA
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
CE1
ADDRESS
CE2
WE
DATA IO
OE
Notes
16.Data IO is high impedance if OE = VIH.
17.If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
18.During this period, the IOs are in output state. Do not apply input signals.
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 8 of 10
Figure 8 shows WE controlled, OE LOW write cycle waveforms.[17]
Figure 8. Write Cycle No. 3
Truth Table
CE1CE2WE OE Inputs/Outputs Mode Power
HXXXHigh Z Deselect/Power Down Standby (ISB)
XLXXHigh Z Deselect/Power Down Standby (ISB)
L H H L Data Out Read Active (ICC)
LHHHHigh Z Output Disabled Active (ICC)
L H L X Data in Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62158ELL-45ZSXI 51-85087 44-Pin TSOP II (Pb-free) Industrial
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
NOTE 18
CE1
ADDRESS
CE2
WE
DATA IO
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CY62158E MoBL®
Document #: 38-05684 Rev. *D Page 9 of 10
Package Diagrams
Figure 9. 44-Pin TSOP II, 51-85087
51-85087-*A
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Document #: 38-05684 Rev. *D Revised June 16, 2008 Page 10 of 10
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY62158E MoBL®
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this SourceCode except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CY62158E MoBL®8-Mbit (1M x 8) Static RAM
Document Number: 38-05684
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 270350 See ECN PCI New Data Sheet
*A 291271 See ECN SYT Converted from Advance Information to Preliminary
Changed input pulse level from VCC to 3V in the AC Test Loads and Waveforms
Modified footnote #9 to include timing reference level of 1.5V and input pulse
level of 3V
*B 1462592 See ECN VKN/AESA Converted from preliminary to final
Removed 35 ns speed bin
Removed “L” parts
Removed 48-Ball VFBGA package
Changed ICC(max) spec from 2.3 mA to 3 mA at f=1 MHz
Changed ICC(typ) spec from 16 mA to 18 mA at f=fMAX
Changed ICC(max) spec from 28 mA to 25 mA at f=fMAX
Changed ISB1(typ) and ISB2(typ) spec from 0.9 μA to 2 μA
Changed ISB1(max) and ISB2(max) spec from 4.5 μA to 8 μA
Changed ICCDR(max) spec from 4.5 μA to 8 μA
Changed tLZOE spec from 3 ns to 5 ns
Changed tLZCE spec from 6 ns to 10 ns
Changed tHZCE spec from 22 ns to 18 ns
Changed tPWE spec from 30 ns to 35 ns
Changed tSD spec from 22 ns to 25 ns
Changed tLZWE spec from 6 ns to 10 ns
Added footnote# 6 related to ISB2 and ICCDR
Updated Ordering information table
*C 2428708 See ECN VKN/PYRS Corrected typo in the Ordering Information table
*D 2516494 See ECN PYRS Corrected ECN number
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