Cypress Semiconductor CY7C1019D User manual

CY7C1019D
1-Mbit (128K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05464 Rev. *E Revised February 22, 2007
Features
• Pin- and function-compatible with CY7C1019B
• High speed
—t
AA = 10 ns
• Low active power
—I
CC = 80 mA @ 10 ns
• Low CMOS standby power
—I
SB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019B
• Available in Pb-free 32-pin 400-Mil wide Molded SOJ and
32-pin TSOP II packages
Functional Description [1]
The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected. The eight input
and output pins (IO0through IO7) are placed in a
high-impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Whenthewriteoperationisactive(CELOW,andWELOW).
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight IO pins (IO0
through IO7) is then written into the location specified on the
address pins (A0through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the IO pins.
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A10
A11
A12
A13 A14
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A15 A16
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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CY7C1019D
Document #: 38-05464 Rev. *E Page 2 of 11
Pin Configuration
Selection Guide
–10 (Industrial) Unit
Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum Standby Current 3 mA
Top View
SOJ/TSOPII
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15 17 18
A
7
A
1
A
2
A
3
CE
IO
0
IO
1
V
CC
A
13
A
16
A
15
OE
IO
7
IO
6
A
12
A
11
A
10
A
9
IO
2
A
0
A
4
A
5
A
6
IO
4
V
CC
IO
5
A
8
IO
3
WE
V
SS
A
14
V
SS
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Document #: 38-05464 Rev. *E Page 3 of 11
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND [2] ... –0.5V to +6.0V
DC Voltage Applied to Outputs
in High-Z State [2]...................................–0.5V to VCC + 0.5V
DC Input Voltage [2]................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40°C to +85°C 5V ±0.5V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions –10 (Industrial) Unit
Min Max
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage [2] –0.5 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage Current GND < VI <VCC, Output Disabled –1 +1 µA
ICC VCC Operating Supply Current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz 80 mA
83 MHz 72 mA
66 MHz 58 mA
40 MHz 37 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fmax 10 mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 3mA
Note
2. VIL (min) = –2.0Vand VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
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Capacitance [3]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 5.0V 6 pF
COUT Output Capacitance 8 pF
Thermal Resistance [3]
Parameter Description Test Conditions 400-Mil
Wide SOJ TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 56.29 62.22 °C/W
ΘJC Thermal Resistance
(Junction to Case) 38.14 21.43 °C/W
AC Test Loads and Waveforms [4]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns
30 pF*
OUTPUT
Z = 50 Ω
50Ω
1.5V (b)
(a)
5V
OUTPUT
5 pF
(c)
R1 480Ω
R2
255Ω
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
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Switching Characteristics (Over the Operating Range) [5]
Parameter Description –10 (Industrial) Unit
Min Max
Read Cycle
tpower [6] VCC(typical) to the first access 100 µs
tRC Read Cycle Time 10 ns
tAA Address to Data Valid 10 ns
tOHA Data Hold from Address Change 3 ns
tACE CE LOW to Data Valid 10 ns
tDOE OE LOW to Data Valid 5 ns
tLZOE OE LOW to Low Z 0 ns
tHZOE OE HIGH to High Z [7, 8] 5ns
tLZCE CE LOW to Low Z [8] 3ns
tHZCE CE HIGH to High Z [7, 8] 5ns
tPU [9] CE LOW to Power-Up 0 ns
tPD [9] CE HIGH to Power-Down 10 ns
Write Cycle [10, 11]
tWC Write Cycle Time 10 ns
tSCE CE LOW to Write End 7 ns
tAW Address Set-Up to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 7 ns
tSD Data Set-Up to Write End 6 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low Z [8] 3ns
tHZWE WE LOW to High Z [7, 8] 5ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured when the outputs enter a
high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. This parameter is guaranteed by design and is not tested.
10.The internal write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V 3mA
tCDR [3] Chip Deselect to Data Retention Time 0 ns
tR [12] Operation Recovery Time tRC ns
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [13, 14]
Read Cycle No. 2 (OE Controlled) [14, 15]
4.5V4.5V
tCDR
VDR> 2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
Notes
12.Full device operation requires linear VCC ramp from VDR to VCC(min) >50 µs or stable at VCC(min) > 50 µs.
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for Read cycle.
15.Address valid prior to or coincident with CEtransition LOW.
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Write Cycle No. 1 (CE Controlled) [16, 17]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [16, 17]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
tSCE
CE
WE
DATA IO
ADDRESS
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
DATAIN VALID
NOTE 18
CE
ADDRESS
WE
DATA IO
OE
Notes
16.Data IO is high impedance if OE= VIH.
17.If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18.During this period the IOs are in the output state and input signals should not be applied.
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Document #: 38-05464 Rev. *E Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17]
Truth Table
CE OE WE IO0–IO7Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
10 CY7C1019D-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1019D-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free)
Please contact your local Cypress sales representative for availability of these parts.
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
NOTE 18
CE
ADDRESS
WE
DATA IO
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Package Diagrams
Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033)
51-85033-*B
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CY7C1019D
Document #: 38-05464 Rev. *E Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 2. 32-pin Thin Small Outline Package Type II (51-85095)
All product or company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85095-**
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CY7C1019D
Document #: 38-05464 Rev. *E Page 11 of 11
Document History Page
Document Title: CY7C1019D, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05464
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in the Ordering Information
*B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
*C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns
*D 520647 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2
*E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA
for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
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