Cypress Semiconductor CYW4343W User manual

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CYW4343W
Single-Chip 802.11 b/g/n MAC/Baseband/Radio
with Bluetooth 4.1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-14797 Rev. *J Revised August 18, 2020
CYW4343W Sing le-Chip 802.11 b/g/n MAC/Baseba nd/Radio with B luetooth 4.1
The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet
of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE
802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support. In addition, it integrates a power amplifier (PA) that meets the output
power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal
transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.
The WLAN host interface supports SPI (gSPI)[1] and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when
operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface.
Using advanced design techniques and process technology to reduce active and idle power, the CYW4343W is designed to address
the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit
that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while
maximizing battery life.
The CYW4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative WLAN and Bluetooth coexistence.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
IEEE 802.11x Key Features
■Single-band 2.4 GHz IEEE 802.11b/g/n.
■Support for 2.4 GHz TurboQAM® data rates (256-QAM) and
20 MHz channel bandwidth.
■Integrated iTR switch supports a single 2.4 GHz antenna
shared between WLAN and Bluetooth.
■Supports explicit IEEE 802.11n transmit beamforming
■Tx and Rx Low-density Parity Check (LDPC) support for
improved range and power efficiency.
■Supports standard SDIO v2.0 and gSPI[1] host interfaces.
■Supports Space-Time Block Coding (STBC) in the receiver.
■Integrated ARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field-upgrade with
future features. On-chip memory includes 512 KB SRAM and
640 KB ROM.
■OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as to
future devices.
Bluetooth Features
■Complies with Bluetooth Core Specification Version 4.1 with
provisions for supporting future specifications.
■Bluetooth Class 1 or Class 2 transmitter operation.
■Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference.
■Interface support — Host Controller Interface (HCI) using a
high-speed UART interface and PCM for audio data.
■Low-power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values.
Note
1. SPI availability may depend on module design. Check with the module manufacturer to confirm.
Broadcom Part Number Cypress Part Number
BCM4343W CYW4343W
BCM4343WKUBG CYW4343WKUBG

Document Number: 002-14797 Rev. *J Page 2 of 109
CYW4343W
General Features
■Supports a battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
■Programmable dynamic power management.
■4 Kbit One-Time Programmable (OTP) memory for storing
board parameters.
■Can be routed on low-cost 1 x 1 PCB stack-ups.
■74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA
package (4.87 mm × 2.87 mm, 0.4 mm pitch).
■153-bump WLCSP package (115 μm bump diameter, 180 μm
bump pitch).
■Security:
❐WPA and WPA2 (Personal) support for powerful encryption
and authentication.
❐AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
❐Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
❐Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS).
■Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. CYW4343W System Block Diagram
VDDIO VBAT
2.4 GHz WLAN +
Bluetooth TX/RX
WLAN
Host I/F
Bluetooth
Host I/F
WL_REG_ON
SDIO/SPI
WL_IRQ
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
BPF
CLK_REQ
PCM
CYW4343W

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CYW4343W
Contents
1. Overview..................................................................... 5
1.1 Overview ............................................................. 5
1.2 Features .............................................................. 6
1.3 Standards Compliance ....................................... 7
2. Power Supplies and Power Management................ 8
2.1 Power Supply Topology ...................................... 8
2.2 CYW4343W PMU Features ................................ 8
2.3 WLAN Power Management .............................. 11
2.4 PMU Sequencing ..............................................11
2.5 Power-Off Shutdown ......................................... 12
2.6 Power-Up/Power-Down/Reset Circuits ............. 12
3. Frequency References............................................ 13
3.1 Crystal Interface and Clock Generation ............ 13
3.2 TCXO ................................................................ 13
3.3 External 32.768 kHz Low-Power Oscillator ...... 15
4. WLAN System Interfaces ........................................ 16
4.1 SDIO v2.0 ......................................................... 16
4.2 Generic SPI Mode ............................................17
4.3 SPI Protocol ...................................................... 18
4.4 gSPI Host-Device Handshake .......................... 21
5. Wireless LAN MAC and PHY .................................. 24
5.1 MAC Features ................................................... 24
5.2 PHY Description ............................................... 26
6. WLAN Radio Subsystem......................................... 28
6.1 Receive Path .................................................... 29
6.2 Transmit Path ................................................... 29
6.3 Calibration ......................................................... 29
7. Bluetooth Subsystem Overview............................. 30
7.1 Features ............................................................ 30
7.2 Bluetooth Radio ................................................ 31
8. Bluetooth Baseband Core ...................................... 32
8.1 Bluetooth 4.1 Features ..................................... 32
8.2 Link Control Layer ............................................. 32
8.3 Test Mode Support ...........................................33
8.4 Bluetooth Power Management Unit .................. 33
8.5 BBC Power Management ................................. 35
8.6 Packet Loss Concealment ................................ 35
8.7 Adaptive Frequency Hopping ........................... 36
8.8 Advanced Bluetooth/WLAN Coexistence ......... 36
8.9 Fast Connection (Interlaced Page and
Inquiry Scans) ................................................... 36
9. Microprocessor and Memory Unit for Bluetooth.. 37
9.1 RAM, ROM, and Patch Memory ....................... 37
9.2 Reset ................................................................ 37
10. Bluetooth Peripheral Transport Unit ..................... 38
10.1 PCM Interface ................................................... 38
10.2 UART Interface ................................................. 43
10.3 I2S Interface ...................................................... 44
11. CPU and Global Functions ..................................... 47
11.1 WLAN CPU and Memory Subsystem ............... 47
11.2 One-Time Programmable Memory ................... 47
11.3 GPIO Interface .................................................. 47
11.4 External Coexistence Interface ......................... 47
11.5 JTAG Interface ................................................. 49
11.6 UART Interface ................................................ 49
12. WLAN Software Architecture .................................. 50
12.1 Host Software Architecture ................................50
12.2 Device Software Architecture ............................50
12.3 Remote Downloader ..........................................50
12.4 Wireless Configuration Utility .............................50
13. Pinout and Signal Descriptions .............................. 51
13.1 Ball Map .............................................................51
13.2 WLBGA Ball List in Ball Number Order with
X-Y Coordinates .................................................53
13.3 WLCSP Bump List in Bump Order with
X-Y Coordinates .................................................55
13.4 WLBGA Ball List Ordered By Ball Name ...........60
13.5 WLCSP Bump List Ordered By Name ...............61
13.6 Signal Descriptions ............................................63
13.7 WLAN GPIO Signals and Strapping Options .....71
13.8 Chip Debug Options ..........................................71
13.9 I/O States ...........................................................72
14. DC Characteristics ................................................... 75
14.1 Absolute Maximum Ratings ...............................75
14.2 Environmental Ratings ......................................75
14.3 Electrostatic Discharge Specifications ...............76
14.4 Recommended Operating Conditions and
DC Characteristics .............................................76
15. WLAN RF Specifications.......................................... 78
15.1 2.4 GHz Band General RF Specifications .........78
15.2 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................79
15.3 WLAN 2.4 GHz Transmitter Performance
Specifications .....................................................82
15.4 General Spurious Emissions Specifications ......83
16. Bluetooth RF Specifications.................................... 84
17. Internal Regulator Electrical Specifications .......... 90
17.1 Core Buck Switching Regulator .........................90
17.2 3.3V LDO (LDO3P3) ..........................................91
17.3 CLDO .................................................................92
17.4 LNLDO ...............................................................93
18. System Power Consumption................................... 94
18.1 WLAN Current Consumption .............................94
18.2 Bluetooth Current Consumption ........................95
19. Interface Timing and AC Characteristics ............... 96
19.1 SDIO Default Mode Timing ................................96
19.2 SDIO High-Speed Mode Timing ........................97
19.3 JTAG Timing ......................................................98
20. Power-Up Sequence and Timing............................. 99
20.1 Sequencing of Reset and
Regulator Control Signals ..................................99
21. Package Information .............................................. 102
21.1 Package Thermal Characteristics ....................102
22. Mechanical Information ......................................... 103
23. Ordering Information.............................................. 107
24. Additional Information ........................................... 107
24.1 Acronyms and Abbreviations ...........................107
24.2 IoT Resources .................................................107
Document History Page ............................................... 108
Sales, Solutions, and Legal Information .................... 109

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CYW4343W
Worldwide Sales and Design Support ..................... 109
Products .................................................................. 109
PSoC® Solutions .....................................................109
Cypress Developer Community ............................... 109
Technical Support ................................................... 109

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CYW4343W
1. Overview
1.1 Overview
The CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution
with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is designed to
address the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnection of all the major physical blocks in the CYW4343W and their associated external interfaces, which are described in greater detail in
subsequent sections.
Figure 2. CYW4343W Block Diagram
Common and
Radio Digital
SW REG
LD O x2
LPO
XTAL OSC.
BPF
WLAN
SDIO
JTAG*
ARM
CM 3
Backplane
BT-W LAN
ECI
WDT
OTP
GPIO
UART
JTA G *
RAM
ROM
PM U
Control
MAC
LNPPHY
Radio
BT Clock Control
Sleep-
tim e
Keeping
Clock
Management PM U PM U
Ctrl
POR
IF
PLL
BT PHY
Modem
Digital
Demod.
& Bit
Sync
Digital
Mod.
BPL
Buffer
APU
BT Clock/
Hopper
LCU
RX/TX
Buffer
WiMax Coex
PTU
UART
Debug
UART
I2S/PCM
GPIO
Wake/
Sleep Ctrl
I/O Port Control
AHB Bus Matrix
Cortex
M3
ETM
JTAG*
SDP
RAM
ROM
Patch
InterCtrl
DM A
Bus Arb
ARM IP
WD Timer
SW Tim er
GPIO
Ctrl
APB
RF
PA
Digital
I/O
SDIO/gSPI
Debug
IEEE 802.11a/b/g/n
GPIO
UART
2.4 GHz
2.4 G H z
PA
Shared LNA
Power
Supply
Sleep CLK
XTAL
WiMax
Coex.
BlueRF
Inte rface
LPO XO
Buffer
XTAL
VBAT
VREGs
BT_REG_ON
AHB to APB
Bridge
AHB
Supported over SDIO or BT PCM
JT A G s u p p o rte d o v e r S D IO or B T P C M
* Via GPIO configuration, JTAG is supported over SDIO or BT PCM
POR W L_REG_O N gSPI

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CYW4343W
1.2 Features
The CYW4343W supports the following WLAN and Bluetooth features:
■IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch
■Bluetooth v4.1 with integrated Class 1 PA
■Concurrent Bluetooth, and WLAN operation
■On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■Simultaneous BT/WLAN reception with a single antenna
■WLAN host interface options:
❐SDIO v2.0, including default and high-speed timing.
■BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces.
■ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions.
■I2S/PCM for BT audio
■HCI high-speed UART (H4 and H5) transport support
■Wideband speech support (16 bits, 16 kHz sampling PCM, through I2S and PCM interfaces)
■Bluetooth SmartAudio® technology improves voice and music quality to headsets.
■Bluetooth low power inquiry and page scan
■Bluetooth Low Energy (BLE) support
■Bluetooth Packet Loss Concealment (PLC)

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CYW4343W
1.3 Standards Compliance
The CYW4343W supports the following standards:
■Bluetooth 2.1 + EDR
■Bluetooth 3.0
■Bluetooth 4.1 (Bluetooth Low Energy)
■IEEE 802.11n—Handheld Device Class (Section 11)
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
The CYW4343W will support the following future drafts/standards:
■IEEE 802.11r — Fast Roaming (between APs)
■IEEE 802.11k — Resource Management
■IEEE 802.11w — Secure Management Frames
■IEEE 802.11 Extensions:
■IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)
■IEEE 802.11i MAC Enhancements
■IEEE 802.11r Fast Roaming Support
■IEEE 802.11k Radio Resource Measurement
The CYW4343W supports the following security features and proprietary protocols:
■Security:
❐WEP
❐WPA™ Personal
❐WPA2™ Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐WAPI
❐AES (Hardware Accelerator)
❐TKIP (host-computed)
❐CKIP (SW Support)
■Proprietary Protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
■IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.

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CYW4343W
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4343W. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW4343W.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out
of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down
only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the
dynamic demands of the digital baseband.
The CYW4343W allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 provides the CYW4343W with all required voltage, further reducing leakage currents.
Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.
Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.
2.2 CYW4343W PMU Features
The PMU supports the following:
■VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3
■1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
■1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep
■Additional internal LDOs (not externally accessible)
■PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
■PMU input supplies automatic sensing and fast switching to support A4WP operations.
Figure 3 and Figure 4 show the typical power topology of the CYW4343W.

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CYW4343W
Figure 3. Typical Power Topology (1 of 2)
Mini PMU
VSEL1
WL RF—LOGEN
W L RF— RX LNA
WL RF—ADC REF
WL RF—TX
WL RF—AFE and TIA
WL RF—XTAL
Internal VCOLDO
80 mA (NMOS)
Internal RXLDO
10 mA (NMOS)
Internal ADCLD O
10 mA (NMOS)
Internal TXLDO
80 mA (PMOS)
Internal AFELDO
80 mA (NMOS)
LNLDO
(100 mA)
1.2V
1.2V
1.2V
1.2V
CL LDO
Peak: 200 mA
Avg: 80 mA
(Bypass in deep-
sleep)
Core Buck
Regulator
Peak: 370 mA
Avg: 170 mA
LPLDO1
(5 mA)
2.2 uH
0603
1.35V
1.1V
1.2V
1.2V
SR_VDDBAT5V
VDD1P35
LDO_VDD_1P5
4.7 uF
0402
SR_PVSS
SR_VLX
WPTLDO
(40 m A) 1.3V
SYS_VDDIO (40 m A)
o_wpt_resetb
o_wl_resetbWL_REG_ON
WPT_1P8 (40 m A)
o_bt_resetbBT_REG_ON
WCC_VDDIO
WCC_VDDIO (40 m A)
PMU_VSS
GND
SR_VBAT5V
VBAT
Int_SR_VBAT
1.2V
VBAT:
Operational: 3.0—4.8V
Performance: 3.0—4.8V
Absolute M axim um : 5.5V
VDDIO
Operational: 1.8—3.3V
SYS_VDDIO
WPT_1P8
600 @
100 MHz
2.2 uF
0402
0.1 uF
0201
WLRF_XTAL_
VDD1P2
W L RF— TX M ixer an d PA
(not all versions)
WL RF—RFPLL PFD and MMD
10 mA average,
> 10 mA at start-up
VOUT_LNLDO
2.2 uF
0402
VDDC1
VDDC2
(AVS)
VOUT_CLDO
1.3V, 1.2V,
or 0.95V
WLAN/BT/CLB/Top, Always On
WL OTP
W L Digital and PHY
WL VDDM (SROMs & AOS)
BT VDDM
BT Digital
Mini PMU is placed
in W L radio
VBAT
Supply ball Supply bump/pad
Ground ball Ground bump/pad
External to chip
Power switch
No pow er switch
No dedicated power switch, but internal power-
down modes and block-specific power switches
BT/WLAN reset
balls
(320 m A)
SW1
CYW4343W

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CYW4343W
Figure 4. Typical Power Topology (2 of 2)
1.8V, 2.5V, and 3.3V
1 uF
0201
4.7 uF
0402
LDO3P3 with
Back-Power
Protection
(Peak 450-800 mA
200 mA Average)
VOUT_3P3
3.3V
LDO_
VDDBAT5V
WPT_3P3
VBAT WLRF_PA_VDD
SW2
Peak: 92 mA
Average: 75 mA
Resistance: 1 ohm
BT_PAVDD
2.5V Cap-less
LNLDO
(10 mA)
WL RF—PA (2.4 GHz)
WL OTP 3.3V
WL RF—ADC, AFE, LOGEN,
LNA, NMOS Mini-PMU LDOs
BT Class 1 PA
Peak: 70 mA
Average: 15 mA
6.4 mA
480 to 800 mA
Supply ball
External to chip
Power switch
No power switch
No dedicated power switch, but internal power-
down modes and block-specific power switches
Placed inside WL Radio
1 uF
0201
22
ohm
WL BBPLL/DFLL
6.4 mA
CYW4343W

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CYW4343W
2.3 WLAN Power Management
The CYW4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW4343W integrated RAM is a high volatile memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW4343W includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4343W into various
power management states appropriate to the operating environment and the activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up
sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer
are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for
the current mode. Slower clock speeds are used wherever possible.
The CYW4343W WLAN power states are described as follows:
■Active mode— All WLAN blocks in the CYW4343W are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The
32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake
up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states
in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To
avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-
up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.
■Power-down mode—The CYW4343W is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a
computation of required resources and a table that describes the relationship between resources and the time required to enable and
disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■enabled
■disabled
■transition_on
■transition_off
The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on
or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements
on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If
the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that
the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either
the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■Computes the required resource set based on requests and the resource dependency table.
■Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■Compares the request with the current resource status and determines which resources must be enabled or disabled.
■Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
■Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

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CYW4343W
2.5 Power-Off Shutdown
The CYW4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW4343W is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW4343W to be effectively off while keeping the I/O pins powered so that they do not
draw extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW4343W, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW4343W to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW4343W has two signals (see Ta b l e 2 ) that enable or disable the Bluetooth and WLAN circuits and the internal regulator
blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences,
see Power-Up Sequence and Timing.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal Description
WL_REG_ON
This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW4343W regulators. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kΩ pull-down resistor that is
enabled by default. It can be disabled through programming.
BT_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
CYW4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.

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CYW4343W
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to
differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW4343W can use an external crystal to provide a frequency reference. The recommended configuration for the crystal
oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
The CYW4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can
operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal
interfaced directly to the CYW4343W.
The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Tab le 3 .
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase
noise requirements listed in Ta b l e 3 .
If the TCXO is dedicated to driving the CYW4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor
with value ranges from 200 pF to 1000 pF as shown in Figure 6.
Figure 6. Recommended Circuit to Use with an External Dedicated TCXO
12 – 27 pF
12 – 27 pF
WLRF_XTAL_XON
WLRF_XTAL_XOP
C
C
R
Note: Resistor value determined by crystal drive level.
See reference schematics for details.
TCXO
NC
200 pF – 1000 pF
WLRF_XTAL_XOP
WLRF_XTAL_XON

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CYW4343W
Table 3. Crystal Oscillator and External Clock Requirements and Performance
Parameter Conditions/Notes Crystal External Frequency
Reference
Min. Typ. Max. Min. Typ. Max. Units
Frequency – – 37.4a
a. The frequency step size is approximately 80 Hz. The CYW4343W does not auto-detect the reference clock frequency; the frequency is
specified in the software and/or NVRAM file.
––– –MHz
Crystal load capacitance – – 12 – – – – pF
ESR – – – 60 – – – Ω
Drive level External crystal must be able to tolerate
this drive level.
200 – – – – – μW
Input Impedance (WLRF_X-
TAL_XOP)
Resistive – – – 10k 100k – Ω
Capacitive – – – – – 7 pF
WLRF_XTAL_XOP input
voltage AC-coupled analog signal – – – 400b
b. To use 256-QAM, a 800 mV minimum voltage is required.
– 1260 mVp-p
WLRF_XTAL_XOP input low
level DC-coupled digital signal –– – 0 – 0.2 V
WLRF_XTAL_XOP input high
level DC-coupled digital signal – – – 1.0 – 1.26 V
Frequency tolerance
Initial + over temperature ––20 – 20 –20 – 20 ppm
Duty cycle 37.4 MHz clock – – – 40 50 60 %
Phase Noisec, d, e
(IEEE 802.11 b/g)
c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in
MHz.
d. Phase noise is assumed flat above 100 kHz.
e. The CYW4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.
37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz
Phase Noisec, d, e
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz
Phase Noisec, d, e
(256-QAM)
37.4 MHz clock at 10 kHz offset – – – – – –140 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –147 dBc/Hz

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3.3 External 32.768 kHz Low-Power Oscillator
The CYW4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table
4.
Note: The CYW4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.
■To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Table 4. External 32.768 kHz Sleep-Clock Specifications
Parameter LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy ±200 ppm
Duty cycle 30–70 %
Input signal amplitude 200–3300 mV, p-p
Signal type Square wave or sine wave –
Input impedancea
a. When power is applied or switched off.
>100 kΩ
<5 pF
Clock jitter <10,000 ppm

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4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high
speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt
signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks
from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 22 for details.
Three functions are supported:
■Function 0 standard SDIO function. The maximum block size is 32 bytes.
■Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.
■Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)
Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode SD 1-Bit Mode gSPI Mode
DATA0 Data line 0 DATA Data line DO Data output
DATA1 Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt
DATA2 Data line 2 NC Not used NC Not used
DATA3 Data line 3 NC Not used CS Card select
CLK Clock CLK Clock SCLK Clock
CMD Command line CMD Command line DI Data input
SD Host
CMD
DAT[3:0]
CLK
CYW4343W
SD Host
CMD
CLK
DATA
IRQ
CYW4343W

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4.2 Generic SPI Mode
In addition to the full SDIO mode, the CYW4343W includes the option of using the simplified generic SPI (gSPI) interface/protocol.
Characteristics of the gSPI mode include:
■Up to 50 MHz operation
■Fixed delays for responses and data from the device
■Alignment to host gSPI frames (16 or 32 bits)
■Up to 2 KB frame size per transfer
■Little-endian and big-endian configurations
■A configurable active edge for shifting
■Packet transfer through DMA for WLAN
gSPI mode is enabled using the strapping option pins. See Ta ble 22 for details.
Figure 9. Signal Connections to SDIO Host (gSPI Mode)
SD Host
DI
SCLK
DO
IRQ
CS
CYW4343W

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4.3 SPI Protocol
The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 10 and
Figure 11 show the basic write and write/read commands.
Figure 10. gSPI Write Protocol
Figure 11. gSPI Read Protocol

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4.3.1 Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 12.
Figure 12. gSPI Command Structure
4.3.1.1 Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The fol-
lowing bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.
4.3.1.2 Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge
of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows
data to be ready for the first clock edge without relying on asynchronous delays.
4.3.1.3 Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read
command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval
between the command/address is not fixed.
4.3.2 Status
The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information
about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of inter-
rupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus
timing for read/write transactions with and without status notification are as shown in Figure 13 below and Figure 14. See Table 6 for
information on status-field details.
SPID Command Structure
C A F1 F0 Address – 17 bits Packet length – 11 bits*
31 30 29 28 27 11 10 0
Function No: 00 – Func 0: All SPI-specific registers
01 – Func 1: Registers and memories belonging to other blocks in the chip (64 bytes max)
10 – Func 2: DMA channel 1. WLAN packets up to 2048 bytes.
11 – Func 3: DMA channel 2 (optional). Packets up to 2048 bytes.
Access : 0 – Fixed address
1 – Incremental address
* 11’h0 = 2048 bytes
Command : 0 – Read
1 – Write