Cypress 256K (32K x 8) CY62256 User manual

256K (32K x 8) Static RAM
CY62256
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05248 Rev. *B Revised August 27, 2002
Features
• High speed: 55 ns and 70 ns
• Voltage range: 4.5V–5.5V operation
• Low active power (70 ns, LL version)
—275 mW (max.)
• Low standby power (70 ns, LL version)
—28 µW (max.)
•Easy memory expansion with CE and OE features
•TTL-compatible inputs and outputs
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1,
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
Functional Description[1]
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers.This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
throughA14). Readingthe device isaccomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remainin a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
512 x 512
ARRA
Y
I/O7
I/O6
I/O5
I/O4
A10
A13 A11 A12
A
A14
A1
0
Logic Block Diagram
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines”on http://www.cypress.com.

CY62256
Document #: 38-05248 Rev. *B Page 2 of 11
Pin Configurations
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)...........................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[2]....................................–0.5V to VCC + 0.5V
DC Input Voltage[2] ................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
Narrow SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A 7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
Reverse Pinout
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A 7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
DIP
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Industrial –40°C to +85°C 5V ±10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions CY62256−55 CY62256−70 UnitMin. Typ.[3] Max. Min. Typ.[3] Max.
VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.5V 2.2 VCC +0.5V V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 V
IIX Input Leakage Current GND <VI< VCC –0.5 +0.5 –0.5 +0.5 µA
IOZ Output Leakage Current GND <VO <VCC,Output Disabled –0.5 +0.5 –0.5 +0.5 µA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 28 55 28 55 mA
L255025 50 mA
LL 25 50 25 50 mA
ISB1 Automatic CE
Power-down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX 0.5 2 0.5 2mA
L0.40.60.4 0.6 mA
LL 0.3 0.5 0.3 0.5 mA
Notes:
2. VIL (min.)= −2.0V for pulse durations of less than 20 ns.
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and aretakenatnominalconditions
(TA= 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

CY62256
Document #: 38-05248 Rev. *B Page 3 of 11
ISB2 Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC, CE > VCC −0.3V
VIN > VCC −0.3V, or VIN <
0.3V, f = 0
15 1 5 mA
L250250 µA
LL 0.1 5 0.1 5µA
Indust’l Temp Range LL 0.1 10 0.1 10 µA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Output Capacitance 8pF
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions CY62256−55 CY62256−70 UnitMin. Typ.[3] Max. Min. Typ.[3] Max.
AC Test Loads and Waveforms
Data Retention Characteristics
Parameter Description Conditions[5] Min. Typ.[3] Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current L VCC = 3.0V, CE > VCC −0.3V,
VIN > VCC −0.3V, or VIN < 0.3V 250 µA
LL 0.1 5µA
LL Ind’l0.1 10 µA
tCDR[4] Chip Deselect to Data Retention Time 0ns
tR[4] Operation Recovery Time tRC ns
Data Retention Waveform
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. No input may exceed VCC + 0.5V.
3.0V
5V
OUTPUT
R1 1800Ω
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
5V
OUTPUT
R1 1800 Ω
R2
990Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.77V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
639Ω
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC

CY62256
Document #: 38-05248 Rev. *B Page 4 of 11
Switching Characteristics Over the Operating Range[6]
Parameter Description
CY62256−55 CY62256−70
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low-Z[7] 5 5 ns
tHZOE OE HIGH to High-Z[7, 8] 20 25 ns
tLZCE CE LOW to Low-Z[7] 5 5 ns
tHZCE CE HIGH to High-Z[7, 8] 20 25 ns
tPU CE LOW to Power-up 0 0ns
tPD CE HIGH to Power-down 55 70 ns
Write Cycle[9, 10]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-up to Write End 45 60 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-up to Write Start 0 0ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0ns
tHZWE WE LOW to High-Z[7, 8] 20 25 ns
tLZWE WE HIGH to Low-Z[7] 5 5 ns
Switching Waveforms
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified withCL= 5 pF as in (b) of AC Test Loads. Transition is measured±500 mV from steady-state voltage.
9. The internalWrite time of the memory is defined by the overlap of CELOWandWELOW.BothsignalsmustbeLOW toinitiateaWriteandeithersignalcanterminate
a Write by going HIGH. The data input set-up and hold timing shouldbe referencedto the rising edge ofthe signal that terminates the Write.
10. The minimum Write cycle time for Write cycle #3 (WEcontrolled, OE LOW) is the sum of tHZWE and tSD
11. Device is continuously selected. OE, CE = VIL.
12. WEis HIGH for Read cycle.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1
[11, 12]

CY62256
Document #: 38-05248 Rev. *B Page 5 of 11
Notes:
13. Address valid prior to or coincident with CEtransition LOW.
14. Data I/O is high impedance if OE= VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the outputremainsin a high-impedance state.
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
Read Cycle No. 2 [12, 13]
tHD
tSD
tPWE tSA
tHA tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN VALID
NOTE
Write Cycle No. 1 (WE Controlled) [9, 14, 15]
16
tWC
tAW
tSA tHA
tHD tSD
tSCE
WE
DATA I/O
ADDRESS
CE
DATAIN VALID
Write Cycle No. 2 (CE Controlled) [9, 14, 15]

CY62256
Document #: 38-05248 Rev. *B Page 6 of 11
Note:
16. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA tAW
tWC
CE
WE
tHZWE
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW) [10, 15]
NOTE 16

CY62256
Document #: 38-05248 Rev. *B Page 7 of 11
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED t AA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I
CC
NORMALIZED I , I
CC SB
ICC
ICC
VCC =5.0V VCC =5.0V
TA=25°C
VCC =5.0V
TA=25°C
ISB
TA=25°C
0.6
0.8
0
AA
1.3
1.2
VIN =5.0V
TA=25°C
1.4
VCC =5.0V
VIN =5.0V
−55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.0
0.5
0.0
-0.5
ISB
3.0
STANDBY
VCC =5.0V
VIN =5.0V
ISB2 µA

CY62256
Document #: 38-05248 Rev. *B Page 8 of 11
Typical DC and AC Characteristics (continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED I PO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 5.0 0.0 1000 0.50
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VIN =0.5V
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High-Z Deselect/Power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High-Z Deselect, Output Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Name Package Type Operating Range
55 CY62256LL−55SNI SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Industrial
CY62256LL−55ZI Z28 28-lead Thin Small Outline Package
70 CY62256−70SNC SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial
CY62256L−70SNC
CY62256LL−70SNC
CY62256L–70SNI Industrial
CY62256LL−70SNI
CY62256LL−70ZC Z28 28-lead Thin Small Outline Package Commercial
CY62256LL−70ZI Z28 Industrial
CY62256−70PC P15 28-lead (600-Mil) Molded DIP Commercial
CY62256L−70PC P15
CY62256LL−70PC P15
CY62256LL−70ZRI ZR28 28-lead Reverse Thin Small Outline Package Industrial

CY62256
Document #: 38-05248 Rev. *B Page 9 of 11
Package Diagrams
51-85017-A
28-lead (600-mil)Molded DIP P15
51-85092-*B
28-lead (300-mil) SNC (Narrow Body) SN28

CY62256
Document #: 38-05248 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nordoes it convey or implyany license underpatent or otherrights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
51-85071-*G
51-85074-*F
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28