Cypress CY62128EV30 User manual

CY62128EV30
MoBL® 1 Mbit (128K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05579 Rev. *D Revised March 28, 2008
Features
■Very high speed: 45 ns
❐Temperature ranges:
• Industrial: –40°C to +85°C
• Automotive-A: –40°C to +85°C
• Automotive-E: –40°C to +125°C
■Wide voltage range: 2.20V – 3.60V
■Pin compatible with CY62128DV30
■Ultra low standby power
❐Typical standby current: 1 μA
❐Maximum standby current: 4 μA
■Ultra low active power
❐Typical active current: 1.3 mA @ f = 1 MHz
■Easy memory expansion with CE1, CE2and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin
STSOP packages
Functional Description
The CY62128EV30[1] is a high performance CMOS static RAM
module organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE1HIGH or CE2LOW). The eight
input and output pins (IO0through IO7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE1 LOW and CE2HIGH and WE
LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins is then written into the location specified on the Address pin
(A0through A16).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the IO pins.
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
A12
SENSE AMPS
POWER
DOWN
WE
OE
A13
A14
A15 A16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A10
A11
CE1
CE2
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
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CY62128EV30
Document #: 38-05579 Rev. *D Page 2 of 11
Pin Configuration[2]
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
26
25
26
27
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15 17 18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
IO 7
IO 6
IO 5
IO 4
A2
NC
IO 0
IO 1
IO 2
CE1
OE
A10
IO 3
A1
A0
A11
CE2
Table 1. Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = 1 MHz f = fmax
Min Typ[3] Max Typ[3] Max Typ[3] Max Typ[3] Max
CY62128EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 1.3 2.0 11 16 1 4
CY62128EV30LL Auto-E 2.2 3.0 3.6 55 1.3 4.0 11 35 1 30
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
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CY62128EV30
Document #: 38-05579 Rev. *D Page 3 of 11
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[4, 5] .........................–0.3V to VCC(max) + 0.3V
DC Input Voltage[4,5].......................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62128EV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to
3.6V
Auto-E –40°C to +125°C
Electrical Characteristics
(Over the Operating Range)
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Typ[3] Max Min Typ[3] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 2.0 V
IOH = –1.0 mA, VCC >2.70V
2.4 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 0.4 V
IOL = 2.1 mA, VCC >2.70V 0.4 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC +
0.3V 1.8 VCC + 0.3V V
VCC= 2.7V to 3.6V 2.2 VCC +
0.3V 2.2 VCC + 0.3V V
VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND <VI< VCC –1 +1 –4 +4 μA
IOZ Output Leakage Current GND <VO <VCC,Output Disabled –1 +1 –4 +4 μA
ICC VCC Operating Supply
Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
11 16 11 35 mA
f = 1 MHz 1.3 2.0 1.3 4.0 mA
ISB1 Automatic CE
Power down
Current — CMOS Inputs
CE1> VCC−0.2V, CE2< 0.2V
VIN >VCC–0.2V, VIN <0.2V)
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
14 135μA
ISB2[7] Automatic CE
Power down
Current — CMOS Inputs
CE1> VCC – 0.2V, CE2< 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
14 130μA
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
7. Only chip enables (CE1and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Document #: 38-05579 Rev. *D Page 4 of 11
Capacitance
(For all packages)[8]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Note
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) >100 μs.
Thermal Resistance
Parameter Description Test Conditions TSOP I SOIC STSOP Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 °C/W
ΘJC Thermal Resistance
(Junction to Case) 3.42 25.86 3.59 °C/W
Figure 1. AC Test Loads and Waveforms
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalentto: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics
(Over the Operating Range)
Parameter Description Conditions Min Typ[3] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR[7] Data Retention Current VCC = 1.5V,
CE1> VCC − 0.2V or CE2< 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
Ind’l/Auto-A 3 μA
Auto-E 30 μA
tCDR[8] Chip Deselect to Data Retention
Time 0ns
tR[9] Operation Recovery Time tRC ns
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Document #: 38-05579 Rev. *D Page 5 of 11
Data Retention Waveform [10]
Switching Characteristics
(Over the Operating Range)[10, 11]
Parameter Description 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to Low Z[12] 55ns
tHZOE OE HIGH to High Z[12,13] 18 20 ns
tLZCE CE LOW to Low Z[12] 10 10 ns
tHZCE CE HIGH to High Z[12, 13] 18 20 ns
tPU CE LOW to Power Up 00ns
tPD CE HIGH to Power Up 45 55 ns
Write Cycle[14]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Setup to Write End 35 40 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 35 40 ns
tSD Data Setup to Write End 25 25 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[12, 13] 18 20 ns
tLZWE WE HIGH to Low Z[12] 10 10 ns
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE
Notes
10.CE is the logical combination of CE1and CE2. When CE1is LOW and CE2 is HIGH, CE is LOW; when CE1is HIGH or CE2is LOW, CE is HIGH.
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13.tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
14.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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Document #: 38-05579 Rev. *D Page 6 of 11
Switching Waveforms
Figure 2. Read Cycle 1 (Address transition controlled) [15, 16]
Figure 3. Read Cycle No. 2 (OE controlled) [10, 16, 17]
Figure 4. Write Cycle No. 1 (WE controlled) [10, 15, 18, 19]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
20
Notes
15.The device is continuously selected. OE, CE1= VIL, CE2= VIH.
16.WE is HIGH for read cycle.
17.Address valid before or similar to CE1transition LOW and CE2transition HIGH.
18.Data IO is high impedance if OE = VIH.
19.If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20.During this period, the IOs are in output state. Do not apply input signals.
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Document #: 38-05579 Rev. *D Page 7 of 11
Figure 5. Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]
Figure 6. Write Cycle No. 3 (WE controlled, OE LOW) [10, 19]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
ADDRESS
CE
DATA IO
WE
DATA VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA IO
NOTE
20
Table 2. Truth Table for CY62128EV30
CE1CE2WE OE Inputs/Outputs Mode Power
H X X X High Z Deselect/Power Down Standby (ISB)
X L X X High Z Deselect/Power Down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H H H High Z Output Disabled Active (ICC)
L H L X Data in Write Active (ICC)
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CY62128EV30
Document #: 38-05579 Rev. *D Page 8 of 11
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62128EV30LL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) Industrial
CY62128EV30LL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free)
CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free)
45 CY62128EV30LL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free) Automotive-A
55 CY62128EV30LL-55ZXE 51-85056 32-pin TSOP Type I (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 7. 32-Pin (450 Mil) Molded SOIC, 51-85081
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
51-85081-*B
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Document #: 38-05579 Rev. *D Page 9 of 11
Figure 8. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056
Package Diagrams (continued)
51-85056-*D
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Document #: 38-05579 Rev. *D Page 10 of 11
Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
Package Diagrams (continued)
51-85094-*D
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