Cypress CY62137EV30 User manual

2-Mbit (128K x 16) Static RAM
CY62137EV30
MoBL®
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05443 Rev. *B Revised February 14, 2006
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62137CV30
• Ultra-low standby power
—Typical standby current: 1µA
—Maximum standby current: 7µA
•Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Byte power-down feature
• Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII
package
Functional Description[1]
The CY62137EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can also be put into standby mode reducing power
consumption by more than 99% when deselected (CE HIGH
or both BLE and BHE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0through
I/O7), is written into the location specified on the address pins
(A0through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8through I/O15) is written into the location
specified on the address pins (A0through A16).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
L
og
i
c
Bl
oc
k
Di
agram
128K x 16
RAM Array I/O
0
– I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
– I/O
15
CE
WE
BHE
A
16
A
0
A
1
A
9
Power -Down
Circuit BHE
BLE
CE
A
10
BLE
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 2 of 12
Pin Configurations[2, 3]
VFBGA (Top View) 44 TSOP II (Top View)
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = 1MHz f = fmax
Min. Typ.[7] Max. Typ.[7] Max. Typ.[7] Max. Typ.[7] Max.
CY62137EV30-45LL 2.2V 3.0V 3.6V 45 ns 2 2.5 15 20 1 7
Note:
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
Vss
A7
I/O0
BHE
NC
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
NC
Vcc
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
VCC
A16
A15
A14
A13
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12 NC
NC
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to 3.9V (VCC(MAX) + 0.3V)
DC Voltage Applied to Outputs
in High-Z State[4, 5]...............–0.3V to 3.9V (VCC MAX + 0.3V)
DC Input Voltage[4, 5]........... –0.3V to 3.9V (VCC MAX + 0.3V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Device Range Ambient Temperature VCC[6]
CY62137EV30-45LL Industrial –40°Cto+85°C 2.2Vto3.6V
Electrical Characteristics Over the Operating Range
Parameter Description
Test Conditions 45 ns
UnitMin. Typ.[7] Max.
VOH Output HIGH Voltage IOH = –0.1 mA VCC = 2.20V 2.0 V
IOH = –1.0 mA VCC = 2.70V 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA VCC = 2.20V 0.4 V
IOL = 2.1mA VCC = 2.70V 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3 V
VCC= 2.7V to 3.6V 2.2 VCC + 0.3 V
VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V
VCC= 2.7V to 3.6V –0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage
Current GND <VO <VCC,Output Disabled –1 +1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
15 20 mA
f = 1 MHz 2.0 2.5
ISB1 Automatic CE
Power-down Current
— CMOS
Inputs
CE1> VCC – 0.2V, CE2 <0.2V
VIN > VCC – 0.2V, VIN <0.2V)
f = fMAX (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
17µA
ISB2 Automatic CE
Power-down Current
— CMOS Inputs
CE1> VCC – 0.2V or CE2< 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
17µA
Notes:
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. VIH(max)=VCC+0.75V for pulse durations less than 20ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 4 of 12
Capacitance (for all packages)[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Thermal Resistance
Parameter Description Test Conditions BGA TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)[8] Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75 77 °C/W
ΘJC Thermal Resistance
(Junction to Case)[8] 10 13 °C/W
AC Test Loads and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[7] Max. Unit
VDR VCC for Data Retention 1 V
ICCDR Data Retention Current VCC= 1V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
0.8 3 µA
tCDR[8] Chip Deselect to Data
Retention Time 0ns
tR[9] Operation Recovery Time tRC ns
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Data Retention Waveform[10]
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs or stable at VCC(min.) >100 µs.
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 5 of 12
Switching Characteristics Over the Operating Range [11]
Parameter Description
45 ns
UnitMin. Max.
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to LOW Z[12] 5ns
tHZOE OE HIGH to High Z[12, 13] 18 ns
tLZCE CE LOW to Low Z[12] 10 ns
tHZCE CE HIGH to High Z[12, 13] 18 ns
tPU CE LOW to Power-Up 0 ns
tPD CE HIGH to Power-Down 45 ns
tDBE BLE/BHE LOW to Data Valid 45 ns
tLZBE BLE/BHE LOW to Low Z[12] 5ns
tHZBE BLE/BHE HIGH to HIGH Z[12, 13] 18 ns
Write Cycle[14]
tWC Write Cycle Time 45 ns
tSCE CE LOW to Write End 35 ns
tAW Address Set-Up to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tBW BLE/BHE LOW to Write End 35 ns
tSD Data Set-Up to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[12, 13] 18 ns
tLZWE WE HIGH to Low-Z[12] 10 ns
Notes:
10.BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
12.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
13.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high- impedance state.
14.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 6 of 12
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[15, 16]
Read Cycle No. 2 (OE Controlled)[16, 17]
Notes:
15.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
16.WE is HIGH for read cycle.
17.Address valid prior to or coincident with CE and BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tLZBE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
tHZBE
BHE/BLE tLZOE
ADDRESS
tDBE
tDOE
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 7 of 12
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
Write Cycle No. 2 (CE Controlled)[14, 18, 19]
Notes:
18.Data I/O is high impedance if OE = VIH.
19.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
20.During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN
NOTE20
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
CE
ADDRESS
WE
DATA I/O
OE
NOTE 20
BHE/BLE tBW
tSA
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 20
tBW
BHE/BLE
DATA I/O
ADDRESS
tSD
tSA
tHA tAW
tWC
CE
WE
DATAIN
NOTE 20
tBW
BHE/BLE
tSCE
tPWE
tHZWE tHD
tLZWE
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 9 of 12
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-down Standby (ISB)
X X X H H High Z Deselect/Power-down Standby (ISB)
L H L L L Data Out (I/OO–I/O15) Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15) Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62137EV30LL-45BVXI 51-85150 48-ballVeryFinePitch BGA (6mm ×8mm ×1 mm) (Pb-free) Industrial
45 CY62137EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 10 of 12
Package Diagrams
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
48-pin VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150-*D
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-Pin TSOP II (51-85087)
51-85087-*A
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CY62137EV30
MoBL®
Document #: 38-05443 Rev. *B Page 12 of 12
Document History Page
Document Title: CY62137EV30 MoBL®2-Mbit (128K x 16) Static RAM
Document Number: 38-05443
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 203720 See ECN AJU New Data Sheet
*A 234196 See ECN AJU Changed ICC MAX at f=1MHz from 1.7 mA to 2.0 mA
Changed ICC TYP from 12 mA (35 ns speed bin) and 10 mA (45 ns speed
bin) to 15 mA and 12 mA respectively
Changed ICC MAX from 20 mA (35 ns speed bin) and 15 mA (45 ns speed
bin) to 25 mA and 20 mA respectively
Changed ISB1 and ISB2 TYP from 0.6 µA to 0.7 µA
Changed ISB1 and ISB2 MAX from 1.5 µA to 2.5 µA
Changed ICCDR from 1 µA to 2 µA
Fixed typos on TSOP II pinout:
Pin 18-22: address lines
Pin 23: NC
Added Pb-free information
*B 427817 See ECN NXR Converted from Advanced Information to Final.
Removed 35 ns Speed Bin
Removed “L” version
Changed ball E3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC
Changed ISB1 and ISB2 Typ. values from 0.7 µA to 1 µA and Max. values from
2.5 µA to 7 µA.
Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2 µA to 3 µA.
Added ICCDR typical value.
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and tBW from 40 ns to 35 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Updated the Ordering Information table and replaced the Package Name
column with Package Diagram.
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