Cypress CY2048WAF User manual

Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
CY2048WAF
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-07738 Rev. *A Revised December 12, 2005
Features
• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output
• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
oscillator output
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Benefits
• Enables fine-tuning of output clock frequency by
adjusting CLoad of the crystal
• Allows multiple programming opportunities to correct
errors, and control excess inventory
• Enables programming of output frequency after
packaging
• PPM clock output error can be adjusted in package
• Provides flexibility inoutputconfigurationsandtesting
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs
•Enables encapsulation in small-size, surface-mount
packages
Block Diagram
Die Pad Description
Horizontal Scribe
Vertical
Scribe
Y (max)
X(max)
6
OUT
2
3
4
VDD
XIN
PD#/OE 5
7C80330A
1
XOUT
die#/rev
VSS
Notes:
X(max): 980 µm, Y(max): 988 µm
Bond pad opening: 85 µm x 85 µm
Pad pitch: 175 µm (min.)
Scribe: X = 70 µm, Y = 86 µm
Wafer thickness: 11 mils (Typ.)
PD#/OE
VSS
VDD
(SDATA/VPP)
XIN
XOUT
CRYSTAL
OUT
/ 1, 2, 4, 8, 16
OSCILLATOR
CONFIGURATION
(SCL)
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Document #: 38-07738 Rev. *A Page 2 of 7
Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0))
Name PadNumber Description X coordinate (µm) Y coordinate (µm)
VDD 1Voltage Supply –360.8 353.7
XOUT 2Oscillator Drain –360.8 134.1
XIN 3Oscillator Gate –360.8 –42.6
PD#/OE 4Programmable power-down or output enable pin –360.8 –275.9
VPP High voltage for programming NV memory
SDATA Serial data pin used for programming in test mode
OUT 6Clock output 360.0 353.7
SCL Serial clock for programming in test mode
VSS 5Ground 360.0 –354.5
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Document #: 38-07738 Rev. *A Page 3 of 7
Absolute Maximum Conditions
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to VDD + 0.5
Output Short Circuit Current.....................................± 50 mA
Storage Temperature (Non-condensing) .... –55°C to +125°C
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
ESD (Human Body Model) MIL-STD-883.................> 2000V
Note:
1. Not 100% tested.
Crystal Specifications[1]
Parameter Description Comments Min. Typ. Max. Unit
FNOM Nominal crystal frequency Fundamental mode, AT cut 10 – 48 MHz
R1Equivalent series resistance (ESR) Fundamental mode – – 40 Ω
R3/R1Ratio of third overtone mode ESR to
fundamental mode ESR Ratio used because typical R1values are much less than the maximum spec 4.5 – – –
C0Crystal shunt capacitance – – 5 pF
C1Crystal motional capacitance 2 – – fF
Operating Conditions
Parameter Description Min. Typ. Max. Unit
VDD Operating Voltage 2.7 – 3.6 V
TJJunction Temperature –40 – 125 °C
CXIN Capacitance XIN, all tuning caps OFF – 10 – pF
CXOUT Capacitance XOUT, all tuning caps OFF – 10 – pF
CLAll tuning Caps OFF 4 5 6 pF
All tuning Caps ON 9.2 10 11.4 pF
COUT Output Load Capacitance – – 15 pF
tRAMP Power-up time for VDD to reach minimum specified
voltage (power ramps must be monotonic) 0.05 – 500 ms
TSStart up time, 90% VDD to valid frequency on output – – 10 ms
DC Electrical Specifications TJ = –40 to 125°C over the operating range
Parameter Description Condition Min. Typ. Max. Unit
VIL Input Low Voltage CMOS Levels – – 20 %VDD
VIH Input High Voltage CMOS Levels 80 – – %VDD
VOL Output Low Voltage VDD = 2.7V–3.6V, IOL = 8 mA – – 0.4 V
VOH Output High Voltage VDD = 2.7V–3.6V, IOL = –8 mA VDD–0.4 – – V
IIL Input Low Current Input = VSS –110µA
IIH Input High Current Input = VDD –110µA
IOZL Output Leakage Current Output = VSS –110µA
IOZH Output Leakage Current Output = VDD ––50µA
IDD Power Supply Current No Load, VDD = 3.3V, 48 MHz – – 20 mA
IPD Power Down Current PD# = 0V – – 25 µA
RUP Input Pull-up resistor VIN = VSS 136MΩ
VIN> = 0.8VDD 80 120 150 kΩ
RDN Output Pull-down resistor VIN = 0.5VDD 500 900 1500 kΩ
CIN Input Pin Capacitance PD#/OE pin – – 7 pF
RFCrystal Feedback R XIN = 0 300 – 800 kΩ
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Document #: 38-07738 Rev. *A Page 4 of 7
Notes:
2. TPJ2 measured using DTS-2075, # of events set to 10, 000.
AC Electrical Specifications[1] over the operating range, except as noted
Parameter[1] Description Condition Min. Typ. Max. Unit
FOUT Output Frequency 0.625 – 48 MHz
DC Output Duty Cycle XTAL Buffered or Divided 45 50 55 %
TR Rise Time OutputClockRise Time,Measuredfrom 20%to
80% of VDD, COUT = 15 pF. 2.5 ns
TFFall Time Output Clock Fall Time, Measured from 80% to
20% of VDD, COUT = 15 pF. 2.5 ns
tPJ1 RMS Period Jitter XIN = 10–48 MHz. Measured at VDD/2 – 4 15 ps
tPJ2[2] Peak-to-peak Period Jitter XIN = 10–48 MHz. Measured at VDD/2 – 30 80 ps
DL Crystal drive level 48-MHz crystal, CL= 7 pF, C0= 2 pF,
R1 = 10 Ohms, Temp. = 25°C, VDD = 3.6V 350–400 µW
–R Negative Resistance Measured at 48 MHz, CL= 10 pF, C0= 5 pF – – –150 Ω
FDRIFT Output Frequency Drift 3.0V ± 10%, 3.3V ± 10% for Temp. = 25°C –2 – 2 ppm
Phase Noise, Temp = 25°C, VDD = 3.3V,
FNOM = 10MHz, XCAP = 7F (Hex)
Offset dBc/Hz (Typ)
10 Hz –90
100 Hz –115
1 kHz –130
10 kHz –140
100 kHz –140
1 MHz –140
Crystal Oscillator Tuning Capacitor Values
Capacitor Bit Capacitance (pF) per Side
C75.000
C62.500
C51.250
C40.625
C30.313
C20.156
C10.078
C00.039
XOUT
C0C1C2C3C4C5C6C7 C7C6C5C4C3C2C1C0
XIN
CXIN CXOUT
Figure 1. Programmable Load Capacitance
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Document #: 38-07738 Rev. *A Page 5 of 7
Timing Parameters over the operating range
Parameter Description Min. Max. Unit
TSTP,SYNC Time from falling edge on PD# to stopped output, synchronous mode, T=1/Fout 1.5T + 350 ns
TSTP,ASYNC Time from falling edge on PD# to stopped output, asynchronous mode 350 ns
TPU,SYNC Time from rising edge on PD# to output at valid frequency, synchronous mode,
T=1/F
out 3ms
TPU,ASYNC Time from rising edge on PD# to output at valid frequency, asynchronous mode 3 ms
TPZX,SYNC Time from rising edge on OE to running output, synchronous mode, T=1/Fout 1.5T + 350 ns
TPZX,ASYNC Time from rising edge on OE to running output, asynchronous mode 350 ns
TPXZ,SYNC Time from falling edge on OE to high impedance output, synchronous mode,
T=1/F
out 1.5T + 350 ns
TPXZ,ASYNC Time from falling edge on OE to high impedance output, asynchronous mode 350 ns
Figure 2. Power-down Timing
CLOC
K
ASYN
C
CLOC
K
SYNC
P
D
T
TSTP
TPU
TSTP
Weakly pulled LOW
Weakly pulled LOW
CLOCK
A
SYNC
CLOCK
SYNC
OE
T T
PZX
T
PZX
Weakly pulled LOW
Weakly pulled LOW
T
PXZ
T
PXZ
Figure 3. Output Enable Timing
tRAMP
TS
VDD - 10%
0V
POWER
OUT
Figure 4. VDD Power-up Timing
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Document #: 38-07738 Rev. *A Page 6 of 7
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Voltage and Timing Definitions
All product or company names mentioned in this document may be the trademarks of their respective holders.
Test and Measurement Set-up
0.1 µF
VDD Output
CLOAD
GND
DUT
Ordering Information
Ordering Code Package Type Operating Range (TJ)
CY2048WAF[3] Wafer Industrial,–40 °C to 125°C
Note:
3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information and support.
Clock
Output
VDD
50% of VDD
0V
t1
t2
Figure 5. Duty Cycle Definition
Clock
Output
tRtF
VDD
80% of V
DD
20% of V
DD
0V
Figure 6.
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CY2048WAF
Document #: 38-07738 Rev. *A Page 7 of 7
Document History Page
Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
Document Number: 38-07738
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 319840 See ECN RGL New data sheet
*A 413511 See ECN RGL Minor Change: Pls. post in the web
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