Cypress EZ-PD CCG3 User manual

www.cypress.com Document No. 002-00210 Rev. *A 1
AN200210
Getting Started with EZ-PD™ CCG3
Author: Vihang Trivedi
Associated Part Family: CYPD3xxx
Associated Software: EZ-PDTM Configuration Utility
Related Application Notes: AN210403
AN200210 introduces the USB Type-C EZ-PD™ CCG3 controller. It provides a brief overview of the CCG3
architecture and its features and applications and covers the evaluation kit in detail along with the development and
debugging tools that can be used. It also references CCG3 resources to help you ramp up quickly with your product
designs.
Contents
1Introduction...............................................................1
1.1 EZ-PD CCG3 Features....................................1
1.2 CCG3 Block Diagram ......................................2
1.3 Prerequisites....................................................2
1.4 CCG3 Design Flow..........................................3
1.5 CCG3 Resources.............................................5
2CCG3 Hardware Details...........................................5
2.1 CY4531 EZ-PD CCG3 EVK.............................5
2.2 CY4500 EZ-PD Protocol Analyzer...................6
3CCG3 Firmware Details and Build Environment.......7
3.1 CCG3 Firmware Architecture Overview...........8
3.2 Flash Memory Organization.............................9
3.3 Firmware Build Environment..........................10
3.4 Firmware Configurable Features ...................13
3.5 Firmware Operation.......................................14
3.6 Programming Firmware in CCG3 Devices.....14
4Software Tools for CCG3 Application Firmware
Development and Debugging..........................................15
4.1 EZ-PD Configuration Utility............................15
4.2 EZ-PD Analyzer Utility...................................17
5CCG3 Configuration Parameter Modification
Example..........................................................................18
5.1 Test CY4531 CCG3 EVK Setup with the
Default Configuration and Type-C Power Adapter.....19
5.2 Modify Configuration Parameters Using EZ-PD
Configuration Utility....................................................21
5.3 Program CCG3 Device with Updated
Configuration Parameters Using the EZ-PD
Configuration Utility....................................................26
5.4 Re-test CY4531 CCG3 EVK Setup with
Modified Configuration and Type-C Power Adapter...30
Document History............................................................32
Worldwide Sales and Design Support.............................33
Products..........................................................................33
PSoC® Solutions ............................................................33
Cypress Developer Community.......................................33
Technical Support...........................................................33
1 Introduction
EZ-PD CCG3 belongs to Cypress’s family of USB Type-C microcontrollers that complies with the latest USB Type-C
and Power Delivery (PD) standards. It consists of a dual bank of 64 KB of flash memory, 8 KB of SRAM memory, a
crypto engine for authentication, and a pair of VCONN field-effect transistors (FETs). In addition, with the integrated
Billboard controller, over-voltage protection (OVP), and over-current protection (OCP), it helps to reduce the need for
additional components and the overall cost of a Type-C ecosystem. Typical applications using CCG3 include power
adapters, power banks, Type-C dongles, notebooks, Thunderbolt hosts and cables, monitors, and docks.
1.1 EZ-PD CCG3 Features
32-bit MCU subsystem
48-MHz ARM®Cortex®-M0 processor
Dual 64-KB flash memory with fail-safe firmware updates

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USB Type-C support with PD
Integrated transceiver, supporting one Type-C port
Integrated upstream facing port—UFP (RD), downstream facing port—DFP (RP), and electronically marked
cable assembly—EMCA (RA) termination resistors
Compliance with USB PD, supporting all standard power profiles
Integrated digital blocks
Four timers, counters, and pulse-width modulators (PWMs) and up to 20 general-purpose I/Os (GPIOs)
Four serial communication blocks (SCBs) for configurable master/slave I2C, SPI, or UART
Integrated USB Billboard controller with Billboard Device Class support
Integrated crypto engine with USB authentication support
Integrated analog blocks
20-V operation
Two VBUS gate drivers
2x2 Crossbar switch
1.2 CCG3 Block Diagram
Figure 1 shows a block diagram of the CCG3 architecture. For more details, refer to the CCG3 datasheet.
Figure 1.CCG3 Architecture Block Diagram
1.3 Prerequisites
This section lists the hardware and software required to get started with CCG3 devices.

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1.3.1 Hardware
CY4531 EZ-PD CCG3 Evaluation Kit (EVK)
PC/laptop with Windows 7 or later platforms; PC with at least one USB port (USB 3.0 port) and Windows 7 or
later recommended
Type-C power adapter that supports a 9-V or higher power profile
Note: The CCG3 device works with all Type-C power adapters that support power profiles from 5 V to 20 V. This
power profile requirement relates to the CY4531 CCG3 EVK architecture.
CY4500 EZ-PDTM Protocol Analyzer (optional; required only for firmware debugging)
MiniProg3 device (optional; required only to program the CCG3 device with a file in .hex format)
1.3.2 Software
EZ-PD CCGx Software Development Kit (SDK) (Version 2.2 or later)
EZ-PD Configuration Utility (version 1.00 or later)
PSoC Creator™ 3.3 SP2 or later with PSoC Programmer 3.24.2 or later (required only if modifying base firmware
functionality)
1.4 CCG3 Design Flow
This section describes a typical design flow users would go through during the Type-C application design right from
the conceptual stage to manufacturing using CCG3 devices. It also covers how each of the hardware, software, and
firmware resources described in this Application Note is used through the design flow. Figure 2 shows a typical
design flow using CCG3 devices.
Once the CCG3 based Type-C application is determined and reference designs have been reviewed, the hardware
and the application development phase of the design flow can be started in parallel. The hardware flow includes
building reference schematics based on the end application and doing the board design to get a few prototypes ready
for the next phase. These reference schematics can be based on the reference designs available on the Cypress’
CCG3 webpage. The CY4531 EZ-PD CCG3 Evaluation Kit (EVK) design can also be reused especially for Type-C
notebook based designs.
The application development flow can get started using the CY4531 EZ-PD CCG3 Evaluation Kit (EVK) in parallel.
The EZ-PD Configuration Utility can be used to make minor updates to the configuration table of the CCG3 device
(for example, Changing PDOs and Vendor ID changes). For making application specific modifications, users can use
the EZ-PD CCGx Software Development Kit (SDK) (Version 2.2 or later).
This EZ-PD CCGx SDK (referred to as CCGx SDK through the rest of the document) along with PSoC®Creator™
(version 3.3 SP2 or later) can be used to build the source projects and create firmware binary files.
Once either configuration changes or firmware changes are made, the EZ-PD Configuration Utility can be used to
update the modified configuration table or to program the CCG3 device. More information on which tool can be used
for what purpose is covered in detail in Table 2.
Once the hardware and application development flow are completed, the existing system design is ready for the test
and validation cycle. The CY4500 EZ-PDTM Protocol Analyzer can be used for testing, firmware debugging, and doing
performance analysis. Mass production and manufacturing can start once the test and validation flow is over and the
system design is final.

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Figure 2. CCG3 Design Flow
Select & Get CCG3 device
START
NO
Select Type-C Application
HARDWARE
DESIGN FLOW
APPLICATION
DEVELOPMENT
DESGN FLOW
Build reference schematic
based on application.
(Refer to CCG3 datasheet or
contact Cypress for reference
design schematics)
Do board design & build
prototypes for test & validation
Minor
Modifications?
Use EZ-PD
Configuration
Utility to make
updates to
Configuration
Table (eg: PDO
changes,
Vendor ID, etc)
Use EZ-PD
Configuration Utility to
update the modified
configuration table, or
program CCG3 device
Start with CCGx SDK.
Make application
specific modifications
to the source project.
Successfully build the
source project with
these modifications to
obtain firmware binary
files.
NO
YES
Perform Test & Validation.
Use CY4500 EZ-PD Protocol
Analyzer & EZ-PD Analyzer
Utility for Test & Debug phase.
Test & Validation
Complete?
YES
Stop
Start production & release
TEST &
VALIDATION FLOW
Get CY4531 CCG3
EVK OR use prototype
hardware
Review associated documentation,
reference designs and application notes
available on https://www.cypress.com/ccg3

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1.5 CCG3 Resources
Table 1 lists the web resources available to help you design end applications using CCG3 devices.
Table 1.CCG3 Design Resources
Category
Available Resources
Datasheet
CCG3 datasheet
Hardware
CY4531 CCG3 EVK –Contains documentation and design files
Application Notes
AN210403 –Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD USB
Type-C Controllers
Programming Specifications
Document
Programming specifications –Provides guidelines on how to program the flash memory of
CCG3 devices
Host PC Software
EZ-PD CCGx SDK
EZ-PD Configuration Utility –GUI-based Windows application to help you configure CCGx
controllers
PSoC Creator 3.3 SP2 or later (firmware development tool)
PSoC Programmer 3.24.2 or later (firmware programming tool)
Debugging Tools
CY4500 EZ-PDTM Protocol Analyzer –Includes EZ-PD Analyzer Utility and documentation
Videos
USB Type-C Essentials, USB Type-C 101 Video Training Series
Other Collateral
CCG3 specific Knowledge Base Articles
Note: A basic introduction to Type-C and how to use Cypress' Type-C products can be found in the USB Type-C 101
Video Training Series of short videos (also listed above).
2 CCG3 Hardware Details
This section discusses the hardware to be used for getting started with the CCG3 device family. It focuses on the
CY4531 EZ-PD CCG3 EVK and the CY4500 EZ-PD Protocol Analyzer.
2.1 CY4531 EZ-PD CCG3 EVK
The CY4531 EZ-PD CCG3 EVK consists of a base board and a daughter card. The CCG3 device is mounted on the
daughter card, which is connected to the base board to enable the CCG3 device’s Type-C port functionality. Figure 3
shows a block diagram of the CY4531 EZ-PD CCG3 EVK architecture.

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Figure 3.CY4531 EZ-PD CCG3 EVK Architecture Block Diagram
PC
USB3.0
DP
USB2.0
CCG Base Board
CCG3
Daughter
Card
DP
Type-C
Port
SS USB
Type-B
Connector
Mux
with Re-
driver
24V DC
power
adapter
USB-
Serial
CC
I2C
Power
Display
Port
Lines
USB
Lines
DP –DisplayPort
PS –Power Supply
USB2 –Used only for programming
Power
Management
CCG3
Power
Control Ckt
The CCG base board consists of a DC input power supply, display multiplexer, DisplayPort, SuperSpeed Type-B
port, and Type-C port. The CCG3 daughter card consists of the CCG3 device and a USB-Serial IC to provide a USB
interface for debugging and programming. The configuration channel (CC) lines of the CCG3 device are connected to
the Type-C port. The display multiplexer is controlled by the CCG3 device over an I2C interface.
The CY4531 EZ-PD CCG3 EVK includes power provider and consumer path control circuitry on the CCG3 daughter
card to showcase EZ-PD CCG3’s ability to switch its power role from a provider to a consumer and vice versa. It
contains over-voltage protection (OVP) and over-current protection (OCP) circuitry for VBUS and supports EZ-PD
CCG3 device programming over SWD and I2C interfaces. The EVK supports PCs, notebooks, tablets, and other
applications that would host a Type-C interface. It is primarily intended as an evaluation vehicle for USB Host
systems that house a Type-C connector. Refer to the CY4531 EZ-PD CCG3 EVK Guide for in-depth information
about EVK use cases and a Type-C notebook application using the EVK.
2.2 CY4500 EZ-PD Protocol Analyzer
Cypress’s CY4500 EZ-PD Protocol Analyzer supports protocol analysis of the USB PD and USB Type-C
specifications. It performs nonintrusive probing, and captures accurate protocol messages on the CC line. This
analyzer consists of Cypress’s programmable MCU (PSoC 5LP), which monitors the data on the CC line and sends
the data to the host application over a USB interface. The Type-C plug and Type-C receptacle on this analyzer
provide a pass-through for the Power Delivery (PD) packets transmitted between each Type-C PD connection. The
processor MCU taps these PD packets without disturbing the system and transfers them over the USB interface to a
PC running the host application. Figure 4 shows the connections between the CY4500 EZ-PD Protocol Analyzer and
the CY4531 CCG3 EVK.

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Figure 4. Connections between CY4500 EZ-PD Protocol Analyzer and CY4531 CCG3 EVK
Micro USB
cable
Type-C
Device
USB 2.0 port
HOST PC
PD traffic captured in EZ-PD Analyzer Utility
Downloading and installing the latest analyzer software setup (CY4500Setup.exe) from the Cypress website
http://www.cypress.com/CY4500 also installs the EZ-PD Analyzer Utility for running the analyzer, required drivers,
and all relevant documentation. An overview of this utility is provided in the EZ-PD Analyzer Utility section.
3 CCG3 Firmware Details and Build Environment
This section provides an overview of the firmware architecture, organization, and operation, and introduces PSoC
Creator and the CCGx SDK which are used as the build environment for firmware development. This section is
followed by a section, which has an overview of the software tools that can be used for development and debugging.
Before covering the in-depth details regarding the firmware build environment and software tools, a brief summary of
which tool can be used for what purpose is provided in Table 2 below. Note that many configuration settings can be
changed without the need for modifying the base firmware using the SDK. For a discussion of how the SDK fits into
the CCG3 ecosystem, see the CCG3 Design Flow section.
Table 2. Firmware, Software Tools & Their Purposes
Tool
Purpose
Output and Its Use
Described in
CCGx SDK
It is the build environment for CCGx
firmware development.
It has application code with Type-C
and USB-PD-compliant firmware,
which can be used for further
development.
Compiling the application source project
generates firmware binaries, which can be
used to program/reprogram respective CCGx
devices.
CCGx SDK section
Firmware
Configurable
Features in
CCGx SDK
Each application firmware in CCGx
SDK contains a set of configurable
features, which can be modified
based on system requirements.
Compiling the application source project
generates firmware binaries, which can be
used to program/re-program respective
CCGx devices.
Firmware
Configurable
Features section
EZ-PD
Configuration
Utility
Used for modifying parameters
stored in the configuration table area
of CCGx device flash.
Also used for programming the
CCGx device flash.
Configuration parameters can be read,
modified, and saved for firmware
development and debugging.
Modified parameters can be updated in
device flash intuitively without firmware
development.
EZ-PD Configuration
Utility section

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3.1 CCG3 Firmware Architecture Overview
Figure 5 shows a block diagram of the CCG3 firmware architecture. The CCG3 firmware architecture allows users to
implement a variety of USB-PD applications using the CCG3 device. It contains the following components:
Hardware Abstraction Layer (HAL): This includes the low-level drivers for various hardware blocks of the
CCG3 device. This includes drivers for the Type-C and USB-PD block, Serial Communication Blocks (SCBs),
GPIOs, flash module, and timer module.
USB Type-C and USB-PD Protocol Stack: This is the complete USB-PD protocol stack that includes the Type-
C and USB-PD port managers, USB-PD protocol layer, the USB-PD policy engine, and the device policy
manager. The device policy manager is designed to allow all policy decisions to be made at the application level,
either on an external Embedded Controller (EC) or in the CCG3 firmware itself.
Application Layer: This is the layer responsible for managing the functions of the PD port, handling alternate
modes, power management, and also manages the Host Processor Interface (HPI). It is further sub-categorized
into the following components:
oPort Management: This module handles all of the PD port management functions including the algorithm
for optimal contract negotiations, source and sink power control, source voltage selection, port role
assignment, and swap request handling.
oAlternate Modes: This module implements the alternate mode handling for CCG as a DFP and UFP. A fully
tested implementation of the DisplayPort alternate mode with CCG as the DFP is provided. The module also
allows users to implement their own alternate mode support in both DFP and UFP modes.
oLow Power: This module attempts to keep the CCG device in the low power standby mode as often as
possible to minimize power consumption.
oHost Processor Interface (HPI): The Host Processor Interface (HPI) is an I2C based control interface that
allows an EC to monitor and control the runtime operation of the CCG3 device. CCG3 implements the HPI
using an I2C interface, with an interrupt line using a GPIO. In a typical CCG3 notebook application, the EC
may communicate with the CCG3 device to negotiate the power with the connected Type-C device based on
the charge level of the internal battery. CCG3 provides this functionality using commands, responses,
events, and asynchronous messages that are modeled as registers. Detailed documentation on CCG3 HPI
Interface is available. Contact your local Cypress FAE or contact Cypress Technical Support for this
information.
Solution Management Layer: This layer consists of the following components:
oExternal Hardware Control: This is a hardware design dependent module that controls the external
hardware blocks such as FETs, regulators, and Type-C switches.
oSolution specific tasks: This is an application layer module where any custom tasks required by the user
solution can be implemented.

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Figure 5.CCG3 Firmware Architecture Diagram
CC
Application Layer
CCG3 Hardware
Hardware Abstraction Layer
Flash SCB GPIOTimer Type-C &
PD
Port
Management Alternate Modes Host Processor I/f
Low Power
(Sleep)
Solution Management Layer
Embedded Controller
(EC)
Type-C
Connector
CCG3 Bootloader
I2C
External HW Control
(FET, Mux, etc) Solution Specific Tasks
Firmware
Hardware
Type-C & USB-PD Stack
3.2 Flash Memory Organization
The CCG3 device has 128 KB of flash divided into two banks of 64 KB each, which allows support for dual firmware
images. Dual firmware images enable firmware updates to be fail-safe; that is, the firmware update does not interrupt
the normal operation of the device. All applications supported by CCG3 support dual firmware images. Figure 6
shows the flash map of the CCG3 device.
Figure 6.CCG3 Firmware Organization

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The I2C bootloader is used to upgrade the CCG3 application firmware. It is allocated in a fixed area. The bootloader
memory area can only be written using the SWD interface. This I2C bootloader uses 5kB of memory. The
configuration table holds the PD configuration for the CCG3 application, and is located at the beginning of each
firmware binary. The size of each configuration table is 1kB. A lot of configurations can be updated by modifying this
table using the EZ-PD Configuration Utility. An overview of this utility is provided in the EZ-PD Configuration Utility
section. The CCG firmware areas FW1 and FW2 are used for the CCG3 firmware application. The metadata area
holds the metadata about both firmware binaries. The firmware metadata follows the definition provided by the PSoC
Creator bootloader component, and includes the firmware checksum, firmware size, and the start address.
3.3 Firmware Build Environment
The tool used for CCG3 firmware development is PSoC Creator, which is a free, Windows-based Integrated Design
Environment (IDE). PSoC Creator 3.3 SP2 or later and the CCGx SDK are required to edit, compile, download, and
debug the firmware for the CCG3 Notebook application, as shown in Figure 7. The PSoC Creator compiler tool chain
is ARM GCC (build 493, provided along with the PSoC Creator build). Refer to the PSoC Creator User Guide for
more details on the PSoC Creator build environment.
Visit the PSoC Creator product page to download and install the latest version of PSoC Creator (3.3 SP2 or later).
This web page also contains links to video training and additional documentation. Within the PSoC Creator tool,
additional help is available via the following documents:
Quick Start Guide: Choose Help > Documentation > Quick Start Guide. This guide gives you the basics for
developing PSoC Creator projects.
System Reference Guide: Choose Help > System Reference Guide. This guide lists and describes the system
functions provided by PSoC Creator.
Document Manager: PSoC Creator provides a Document Manager to help you easily find and review document
resources. To open the Document Manager, choose Help > Document Manager.
Figure 7.PSoC Creator IDE
3.3.1 CCGx SDK
The CCGx Software Development Kit (SDK) is a PSoC Creator project that allows users to harness the capabilities of
Cypress’s CCG families of Type-C Controllers. It provides a Type-C and USB-PD specification compliant firmware
stack along with the necessary drivers and software interfaces required to implement applications using CCG
controllers. The CCGx SDK also includes reference projects implementing standard Type-C applications and
documentation that guides users in customizing existing applications, or creating new ones. For more information on
the CCGx SDK, refer to the CCGx SDK User Guide.

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This Application Note references only the notebook application for CCG3 devices. In general, the CCGx SDK
consists of the following basic components.
Source Code
PD Stack and Host Processor Interface (HPI) in a pre-compiled library form
Firmware sources for other blocks
Reference Application
Integrated UFP (RD), DFP (RP), and EMCA (RA) termination resistors
Compliance with USB PD, supporting all standard power profiles
Firmware Binaries
Application specific .hex and .cyacd files (this application note references the CCG3 notebook application
only)
Supporting Documentation
CCGx SDK User Guide
Firmware API Reference Guide
Release Notes
3.3.2 PSoC Creator Project Structure Overview
The CCGx SDK includes a reference firmware project for a notebook application of the CCG3 device. Figure 8 shows
the PSoC Creator workspace file structure for a CCG3 device–based notebook application. PSoC Creator generates
bootloadable .cyacd files and a Cypress format .hex file every time a project is successfully compiled and built.
In every PSoC Creator project, a system-level design diagram is included. This schematic is located in the
TopDesign.cysch file. The firmware version is controlled by an ‘application type’string and ‘application major’and
‘application minor’numbers. This information is stored in the app_version.h file of the PSoC Creator project. The
application string and the version numbers can be modified by customers based on the updates needed and
requirements.

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Figure 8.PSoC Creator Workspace Structure for CCG3 Notebook Application

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3.4 Firmware Configurable Features
The notebook application firmware in the CCGx SDK has the following configurable features, which can be modified
by individual users based on system requirements. These configurable parameters are located in the config.h file.
Table 3 lists the compile-time configurable features available in the CCG3 notebook application firmware.
Table 3.Configurable Features of CCG3 Notebook Application Firmware (config.h file)
Pre-processor switch
Description
Values
(Default values in bold)
VBUS_OVP_ENABLE
Enable overvoltage Protection handling on VBUS. This
feature can be turned off using the configuration table,
even if it is enabled here.
1 for VBUS OVP enable
0 for VBUS OVP disable
VBUS_OVP_AUTO_CONTROL_ENABLE
Enable automatic FET control by hardware when an OVP
event is detected.
1 for automatic hardware
cut-off
0 for firmware cut-off
SYS_DEEPSLEEP_ENABLE
Enable flag for the low power module, which keeps CCG3
in deep sleep mode at all possible times.
1 for low power enable
0 for low power disable
DFP_ALT_MODE_SUPP
Enable Alternate Mode handling when CCG3 is used as
DFP.
1 for alternate mode
enable
0 for alternate mode disable
DP_DFP_SUPP
Enable DisplayPort Alternate mode when CCG3 is used as
DFP. This requires DFP_ALT_MODE_SUPP.
1 for DisplayPort enable
0 for DisplayPort disable
APP_FW_LED_ENABLE
Enable toggling of the LED to indicate firmware operation.
It is recommended that this be left disabled in production
designs to save power and also to free up the GPIO used
for LED control.
1 for LED enable
0 for LED disable

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3.5 Firmware Operation
The code flow for the application is implemented in the Source Files\Solution\main.c file. Figure 9 shows the flow
diagram of the firmware operation. Based on this, it is clear that the firmware implementation is a simple round-robin
loop that services each of the tasks that the application has to perform. All PD management, HPI command handling,
and Vendor Defined Message (VDM) handling is encapsulated in the task handlers in the CCG3 firmware stack.
Figure 9. CCG3 Notebook Firmware Flow Diagram
LOW POWER MODE
MAIN TASK LOOP
CONFIGURE PERIPHERAL
BLOCKS
FW ENTRY
VALID CONFIGURATION
TABLE
NO
YES
LOAD FLASH CONFIG INFO
INTIALIZE INTERRUPTS
INITIALIZE THE PD MODULES
TYPE-C STATE MACHINE
TASK
PD STATE MACHINE TASK
ENTER LOW POWER MODE
PD IDLE TIMEOUT?
CONFIGURE WAKEUP
SOURCES
WAIT FOR INTERRUPT
(DEEP SLEEP MODE)
DISABLE WAKEUP SOURCES
YES
NO
EXIT LOW POWER MODE
HOST PROCESSOR
INTERFACE TASK
MARK CURRENT FIRMWARE
INVALID
DEVICE RESET
UART FORWARDING TASK
ALTERNATE MODE TASK
More details on the CCGx SDK firmware architecture, firmware APIs, and getting started with the CCG3 SDK can be
found in the CCGx SDK User Guide. The same guide can also be used for customizing the CCG3 firmware
application, that is, modifying and updating the PSoC Creator project for a different hardware design, building and
debugging the project, and programming the modified firmware in the CCG3 device.
3.6 Programming Firmware in CCG3 Devices
There are two methods to program CCG3 devices:
Using EZ-PD Configuration Utility
Using MiniProg3 device and PSoC Creator/PSoC Programmer tool
The EZ-PD Configuration Utility requires a .cyacd file as the input for the firmware binary file to be programmed.
Refer to Chapter 4 of the CY4531 EZ-PD CCG3 Evaluation Kit User Guide for more details on how to program CCG3
devices using the EZ-PD Configuration Utility. The PSoC Creator/PSoC Programmer tool uses a .hex file for
programming all devices. Refer to the knowledge base article KBA96477 for more details on how to program CCG3
devices using PSoC Creator/PSoC Programmer along with a MiniProg3 device.

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4 Software Tools for CCG3 Application Firmware Development and
Debugging
This section provides an overview of the EZ-PD Configuration Utility and the EZ-PD Analyzer Utility. In general, the
tools can be categorized as follows:
Firmware development and programming tools
EZ-PD Configuration Utility: The EZ-PD Configuration Utility is used to read, modify, and update the
configuration parameters of a CCGx device using the I2C interface. It is also used to update the application
firmware of the CCGx device.
PSoC Creator™ (CCG3 devices are supported from version 3.3 SP2 or later): As described in the Firmware
Build Environment section, PSoC Creator is used to modify, debug, and program the firmware into the CCG3
device. This option is required only if the functionality of the CCG3 firmware is being modified from that of the
standard firmware, or if the firmware is being modified for a different hardware design.
Debugging tool for CCGx applications
EZ-PD Analyzer Utility: The EZ-PD Analyzer Utility along with a CY4500 EZ-PD Protocol Analyzer is used to
capture PD messages between the CCG3 device and an attached Type-C device with the firmware
application that is running. An overview of its functionality is provided in the CY4500 EZ-PD Protocol Analyzer
section.
4.1 EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a Windows application that configures the parameters stored in the configuration
table areas of the internal flash memory of the CCGx device. These parameters can be chosen based on customer-
specific application or system requirements. The utility allows you to intuitively select and configure the parameters
for your specific application and thus saves time on firmware development. This utility also allows programming of the
firmware applications.
You can download and install this tool from the Cypress website. After installation, the utility can be executed from
the following location: Windows > Start > All Programs > Cypress > EZ-PD Configuration Utility > EZ-PD
Configuration Utility. Figure 10 shows the utility running on a Windows machine.

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Figure 10.EZ-PD Configuration Utility Start Page
The EZ-PD Configuration Utility can be used to update the application firmware and configure the CCGx device. The
utility shows the target application for the CCG3 device as a dual role port (DRP) notebook. The workflow for
configuring any CCGx device is completed in three stages:
1. Create configuration: Create a new configuration from the File menu of the utility, or read an existing
configuration to be modified.
2. Select parameters: Select the parameters available for the target application such as a notebook.
3. Device configuration: Program the device flash using the Configure Device option.
Refer to the EZ-PD Configuration Utility User Manual for more details on firmware update and configuration of the
device. You can open the user manual by choosing Help > User Manual in the EZ-PD Configuration Utility, as shown
in Figure 11.

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Figure 11.Opening the EZ-PD Configuration Utility User Manual
4.2 EZ-PD Analyzer Utility
The EZ-PD Analyzer Utility is a software application that is run along with a CY4500 EZ-PD Protocol Analyzer. When
this utility is run, it shows PD messages over CC (for example, PR_SWAP, DR_SWAP, and PDOs) as shown in
Figure 12 while the CCG3 device is establishing a PD contract with the connected Type-C device.

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Figure 12.EZ-PD Analyzer Utility Showing PD Packets Captured on CC Line
Whenever a Type-C device is connected to the Type-C port of the CY4531 CCG3 EVK, a PD contract is established
between the CCG3 device and the attached Type-C device. The flow of CC messages as well as source and sink
Power Data Objects (PDOs—used to expose source/sink port’s power capabilities in the CC messages) between the
power port partners can be monitored on the PC by using the EZ-PD Protocol Analyzer and running the EZ-PD
Analyzer Utility. This information helps in debugging the CCG3 firmware if there are any issues (errors, delays, no
contract, and so on) related to establishing the power contract between the CCG3 device and the attached Type-C
device.
5 CCG3 Configuration Parameter Modification Example
Many CCG configuration parameters are stored in the configuration tables in the device’s internal flash memory. You
may need to make changes to these parameters based on system requirements and the end application. This section
provides a simple example of a Type-C ecosystem to describe how to change the configuration parameters using the
EZ-PD Configuration Utility and how to verify the changes using the CY4500 EZ-PDTM Protocol Analyzer.
Consider the example of a Type-C power adapter connected to the CY4531 CCG3 EVK. Assuming this Type-C
power adapter supports a custom PDO, the power contract between it and the CCG3 device of CY4531 CCG3 EVK
will be successfully established only if the CCG3 device supports the same custom PDO. The EZ-PD Configuration
Utility allows you to modify parameters such as the sink or source PDOs without making any changes to the base
firmware so that the CY4531 CCG3 EVK can successfully establish a power contract with the power adapter.
From a top-level perspective, the following are the steps to modify the CCG3 device’s configuration parameters. The
following sections explain each step in detail.
1. Test the CY4531 CCG3 EVK in the default configuration with a Type-C power adapter to identify the established
power contract.
2. Update the configuration parameters (remove a sink PDO supported by the power adapter’s custom PDOs such
as 14.8V, 2A) using the EZ-PD Configuration Utility.
3. Program the updated configuration parameters into the CCG3 device using the EZ-PD Configuration Utility and
verify.
4. Retest the CY4531 CCG3 EVK setup with a Type-C power adapter to verify the updated PDOs using the
CY4500 EZ-PD Protocol Analyzer.

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5.1 Test CY4531 CCG3 EVK Setup with the Default Configuration and Type-C Power Adapter
This section describes the steps to observe the behavior when the CY4531 CCG3 EVK with the default configuration
parameters is connected to a Type-C power adapter. The voltage measured manually at the output header J7 is
verified by using the CY4500 EZ-PD Protocol Analyzer as well.
1. Ensure that the CCG3 device of the CY4531 CCG3 EVK is programmed with the latest default binaries provided
on the CCGx SDK webpage. As shown in Figure 13, ensure jumper J4 is set to 2-3 and jumper J3 is set to 1-2
positions.
2. Connect the Type-C power adapter (Apple 29W power adapter used as reference in this example) to the CY4531
CCG3 EVK, as shown in Figure 13. Connect a multimeter to power output header J7 of the CY4531 CCG3 EVK.
3. When the Apple Type-C power adapter is connected to the Type-C port of the CY4531 CCG3 EVK, the CCG3
device of the CY4531 CCG3 EVK will be able to establish a power contract with the power adapter, as it is
configured for custom PDOs supported by this Type-C power adapter. Due to this, the power adapter will provide
14.8V, which is the established power configuration. This can be verified by measuring the voltage on the power
output header J7 of the CCG baseboard using a multimeter. The output voltage on this header will be about
14.8V, which is the negotiated voltage supported by the Type-C power adapter.
Figure 13.CY4531 CCG3 EVK Connected to Type-C Power Adapter
4. This output voltage can also be verified using the CY4500 EZ-PD Protocol Analyzer and capturing a CC trace.
Ensure that the latest version of the CY4500 EZ-PD Protocol Analyzer is downloaded and installed.
5. Disconnect all connections shown in Figure 13, and connect CY4500 EZ-PD Protocol Analyzer to the PC (USB
host) using a Micro-USB cable.
6. Connect the Type-C plug of the CY4500 EZ-PD Protocol Analyzer to the Type-C port of the CCG3 EVK.
7. Launch the EZ-PD Analyzer Utility from Windows >All Programs >Cypress >EZ-PD Analyzer Utility >
EZ-PD Analyzer Utility and click on the Start Capturing icon shown in Figure 14 to start capturing the CC
traffic.
Jumper
Setting
J4
2-3
J3
1-2

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Figure 14. Start Capturing Traffic in EZ-PD Analyzer Utility
8. Connect the Apple 29W USB-C power adapter to the Type-C receptacle of the CY4500 EZ-PD Protocol Analyzer
(see Figure 15). Observe that the PD traffic is being captured on the EZ-PD Analyzer Utility. The utility running
on the host PC should look similar to that in Figure 16.
Figure 15.Connecting CY4500 EZ-PD Protocol Analyzer to CY4531 CCG3 EVK
Start Capturing
Micro USB
cable
Type-C Power
Adapter
USB 2.0 port
HOST PC
Jumper Setting
J4 2-3
J3 1-2