Cypress EZ-OTG CY7C67200 User manual

EZ-OTG™ Programmable USB
On-The-Go
CY7C67200
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-08014 Rev. *G Revised November 14, 2006
EZ-OTG Features
• Single-chipprogrammableUSBdual-role(Host/Peripheral)
controller with two configurable Serial Interface Engines
(SIEs) and two USB ports
• Supports USB OTG protocol
• On-chip 48-MHz 16-bit processor with dynamically
switchable clock speed
• ConfigurableIOblocksupports avarietyofIO options or up
to 25 bits of General Purpose IO (GPIO)
• 4K × 16 internal mask ROM contains built-in BIOS that
supportsacommunication-readystatewithaccesstoI2C™
EEPROM interface, external ROM, UART, or USB
• 8K x 16 internal RAM for code and data buffering
• 16-bit parallel host port interface (HPI) with DMA/Mailbox
data path for an external processor to directly access all
on-chip memory and control on-chip SIEs
• Fast serial port supports from 9600 baud to 2.0M baud
• SPI supports both master and slave
• Supports 12 MHz external crystal or clock
• 2.7V to 3.6V power supply voltage
• Package option: 48-pin FBGA
Typical Applications
EZ-OTG is a very powerful and flexible dual-role USB
controller that supports a wide variety of applications. It is
primarily intended to enable USB OTG capability in applica-
tions such as:
• Cellular phones
• PDAs and pocket PCs
• Video and digital still cameras
• MP3 players
• Mass storage devices
Timer 0 Timer 1
Watchdog
Control
4Kx16
ROM BIOS 8Kx16 RAM
CY16
16-bit RISC CORE
SIE1
USB-A
SIE2
USB-A
OTG
HOST/
Peripheral
USB Ports
D+,D-
D+,D-
UART I/F
HSS I/F
I2C
EEPROM I/F
HPI I/F
SPI I/F
nRESET
CY7C67200
GPIO [24:0]
PLL
X1
X2
GPIO
SHARED INPUT/OUTPUT PINS
Vbus, ID
Mobile
Power
Booster
Block Diagram
CY7C67200
[+] Feedback

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Document #: 38-08014 Rev. *G Page 2 of 78
Introduction
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first
USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs
toaddUSB host functionality. EZ-OTG hasitsown 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-OTG also has a programmable IO interface block
allowing a wide range of interface options.
Processor Core Functional Overview
An overview of the processor core components are presented
in this section.
Processor
EZ-OTG has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-OTG requires a 12 MHz source for clocking. Either an
external crystal or TTL-level oscillator may be used. EZ-OTG
hasan internalPLLthatproducesa48MHz internalclockfrom
the 12 MHz source.
Memory
EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-OTG BIOS.
The internal RAM can be used for program code or data.
Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors
are hardware interrupts and the following 80 vectors are
software interrupts.
General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a
watchdog timer. All three timers can generate an interrupt to
the EZ-OTG.
Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep
mode pauses all operations and provides the lowest power
state.
Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with
several interface options available. See Table 1 to understand
how the interfaces share pins and can coexist. Below are
some general guidelines:
• I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to HSS, SPI, and UART
Table 1. Interface Options for GPIO Pins
GPIO Pins HPI HSS SPI UART I2C OTG
GPIO31 SCL/SDA
GPIO30 SCL/SDA
GPIO29 OTGID
GPIO24 INT
GPIO23 nRD
GPIO22 nWR
GPIO21 nCS
GPIO20 A1
GPIO19 A0
GPIO15 D15 CTS
GPIO14 D14 RTS
GPIO13 D13 RXD
GPIO12 D12 TXD
GPIO11 D11 MOSI
GPIO10 D10 SCK
GPIO9 D9 nSSI
GPIO8 D8 MISO
GPIO7 D7 TX
GPIO6 D6 RX
GPIO5 D5
GPIO4 D4
GPIO3 D3
GPIO2 D2
GPIO1 D1
GPIO0 D0
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USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have
a single USB transceiver, meeting the USB 2.0 specification
requirements for full and low speed (high speed is not support-
ed). In Host mode, EZ-OTG supports two downstream ports;
each supports control, interrupt, bulk, and isochronous trans-
fers. In Peripheral mode, EZ-OTG supports one peripheral
port with eight endpoints for each of the two SIEs. Endpoint 0
is dedicated as the control endpoint and only supports control
transfers. Endpoints 1 though 7 support Interrupt, bulk (up to
64 bytes per packet), or isochronous transfers (up to 1023
bytes per packet size). EZ-OTG also supports a combination
of Host and Peripheral ports simultaneously, as shown in
Table 2.
USB Features
• USB 2.0 compatible for full and low speed
• Up to two downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must
reside in internal RAM
• Up to eight available peripheral endpoints (1 control
endpoint)
• SupportsControl,Interrupt,Bulk,andIsochronoustransfers
• Internal DMA channels for each endpoint
• Internal pull up and pull down resistors
• Internal Series termination resistors on USB data lines
USB Pins
OTG Interface
EZ-OTG has one USB port that is compatible with the USB
On-The-Gosupplementtothe USB 2.0specification.TheUSB
OTG port has various hardware features to support Session
Request Protocol (SRP) and HostNegotiationProtocol(HNP).
OTG is only supported on USB PORT 1A.
OTG Features
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V < VBUS < 0.8V
• ID Pin Status
• Switchable 2-Kohm internal discharge resistor on VBUS
• Switchable 500-ohm internal pull-up resistor on VBUS
• Individually switchable internal pull-up and pull-down
resistors on the USB data lines
OTG Pins
General Purpose IO Interface
EZ-OTG has up to 25 GPIO signals available. Several other
optional interfaces use GPIO pins as well and may reduce the
overall number of available GPIOs.
GPIO Description
All Inputs are sampled asynchronously with state changes oc-
curring at a rate of up to two 48 MHz clock cycles. GPIO pins
are latched directly into registers, a single flip-flop.
Unused Pin Descriptions
Unused USB pins must be tri-stated with the D+ line pulled
high through the internal pull-up resistor and the D– line pulled
low through the internal pull-down resistor.
Unused GPIO pins must be configured as outputs and driven
low.
UART Interface
EZ-OTG has a built-in UART interface. The UART interface
supports data rates from 900 to 115.2K baud. It can be used
as a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
Table 2. USB Port Configuration Options
Port Configurations Port 1A Port 2A
OTG OTG –
OTG + 1 Host OTG Host
OTG + 1 Peripheral OTG Peripheral
1 Host + 1 Peripheral Host Peripheral
1 Host + 1 Peripheral Peripheral Host
2 Hosts Host Host
1 Host Host –
1 Host – Host
2 Peripherals Peripheral Peripheral
1 Peripheral Peripheral –
1 Peripheral – Peripheral
Table 3. USB Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
DM2A C2
DP2A D3
Table 4. OTG Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
OTGVBUS C1
OTGID F4
CSwitchA D1
CSwitchB D2
[+] Feedback

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UART Features
• Supports baud rates of 900 to 115.2K
•8-N-1
UART Pins
I2C EEPROM Interface
EZ-OTG provides a master-only I2C interface for external se-
rial EEPROMs. The serial EEPROM can be used to store ap-
plication-specific code and data. This I2C interface is only to
be used for loading code out of EEPROM, it is not a general
I2C interface. The I2C EEPROM interface is a BIOS imple-
mentation and is exposed through GPIO pins. Refer to the
BIOS documentation for additional details on this interface.
I2C EEPROM Features
• Supports EEPROMs up to 64 KB (512K bit)
• Auto-detection of EEPROM size
I2C EEPROM Pins
Serial Peripheral Interface
EZ-OTG provides an SPI interface for added connectivity.
EZ-OTG may be configured as either an SPI master or SPI
slave. The SPI interface can be exposed through GPIO pins
or the External Memory port.
SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 kHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communi-
cation in PIO mode
• Programmable delay timing for the active/inactive master
SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
SPI Pins
The SPI port has a few different pin location options as shown
in Table 7. The pin location is selectable via the GPIO Control
register [0xC006].
High-Speed Serial Interface
EZ-OTG provides an HSS interface. The HSS interface is a
programmable serial connection with baud rate from 9600
baud to 2M baud. The HSS interface supports both byte and
block mode operations as well as hardware and software
handshaking. Complete control of EZ-OTG can be accom-
plished through this interface via an extensible API and com-
munication protocol. The HSS interface can be exposed
through GPIO pins or the External Memory port.
HSS Features
• 8-bit, no parity code
• Programmable baud rate from 9600 baud to 2M baud
• Selectable 1- or 2-stop bit on transmit
• Programmable intercharacter gap timing for BlockTransmit
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-OTG internal
memory (DMA transfer)
• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done
interrupts
• Complete access to internal memory
HSS Pins
Table 5. UART Interface Pins
Pin Name Pin Number
TX B5
RX B4
Table 6. I2C EEPROM Interface Pins
Pin Name Pin Number
SMALL EEPROM
SCK H3
SDA F3
LARGE EEPROM
SCK F3
SDA H3
Table 7. SPI Interface Pins
Pin Name Pin Number
nSSI F6 or C6
SCK D5
MOSI D4
MISO C5
Table 8. HSS Interface Pins
Pin Name Pin Number
CTS F6
RTS E4
RX E5
TX E6
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Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides
DMA access to the EZ-OTG internal memory by an external
host, plus a bidirectional mailbox register for supporting
high-level communication protocols. This port is designed to
be the primary high-speed connection to a host processor.
Complete control of EZ-OTG can be accomplished through
this interface via an extensible API and communication
protocol. Other than the hardware communication protocols, a
host processor has identical control over EZ-Host whether
connecting to the HPI or HSS port. The HPI interface is
exposed through GPIO pins.
Note It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as
outputsforatestmode.Ifthesepinsneedtobeusedasinputs,
a series resistor is required (10 ohm to 48 ohm is recom-
mended). Refer to BIOS documentation for addition details.
See section “Reset Pin” on page 9.
HPI Features
• 16-bit data bus interface
• 16 MB/s throughput
• Auto-increment of address pointer for fast block mode
transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status register
HPI Pins
The two HPI address pins are used to address one of four
possible HPI port registers as shown in Table 10 below.
Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by
EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to
Figure 1 below.
Component details:
• D1 and D2: Schottky diodes with a current rating greater
than 60 mA.
• C1: Ceramic capacitor with a capacitance of 0.1 µF.
• C2: Capacitor value must be no more that 6.5 µF since that
is the maximum capacitance allowed by the USB OTG
specification for a dual-role device. The minimum value of
C2is 1µF.Thereareno restrictionsonthetypeof capacitor
for C2.
If the VBUS charge pump circuit is not to be used,
CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-
nected.
Table 9. HPI Interface Pins [1, 2]
Pin Name Pin Number
INT H4
nRD G4
nWR H5
nCS G5
A1 H6
A0 F5
D15 F6
D14 E4
D13 E5
D12 E6
D11 D4
D10 D5
D9 C6
D8 C5
Notes
1. HPI_INT is for the Outgoing Mailbox Interrupt.
2. HPI strobes are negative logic sampled on rising edge.
D7 B5
D6 B4
D5 C4
D4 B3
D3 A3
D2 C3
D1 A2
D0 B2
Table 10.HPI Addressing
HPI A[1:0] A1 A0
HPI Data 0 0
HPI Mailbox 0 1
HPI Address 1 0
HPI Status 1 1
Figure 1. Charge Pump
Table 9. HPI Interface Pins [1, 2] (continued)
Pin Name Pin Number
CSWITCHA
CY7C67200
CSWITCHB
OTGVBUS
D1 D2
C1
C2
VBUS
[+] Feedback

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Document #: 38-08014 Rev. *G Page 6 of 78
Charge Pump Features
• Meets OTG Supplement Requirements, see Table 41, “DC
Characteristics: Charge Pump,” on page 66.
Charge Pump Pins
Booster Interface
EZ-OTG has an on-chip power booster circuit for use with
power supplies that range between 2.7V and 3.6V. The
booster circuit boosts the power to 3.3V nominal to supply
power for the entire chip. The booster circuit requires an
external inductor, diode, and capacitor. During power down
mode, the circuit is disabled to save power. Figure 2 shows
how to connect the booster circuit.
Component details:
• L1: Inductor with inductance of 10 µH and a current rating
of at least 250 mA
• D1: Schottky diode with a current rating of at least 250 mA
• C1: Tantalum or ceramic capacitor with a capacitance of at
least 2.2 µF
Figure 3 shows how to connect the power supply when the
booster circuit is not being used.
Booster Pins
Crystal Interface
The recommended crystal circuit to be used with EZ-OTG is
shown in Figure 4. If an oscillator is used instead of a crystal
circuit, connect it to XTALIN and leave XTALOUT uncon-
nected. For further information on the crystal requirements,
see Table 39, “Crystal Requirements,” on page 65.
Table 11.Charge Pump Interface Pins
Pin Name Pin Number
OTGVBUS C1
CSwitchA D1
CSwitchB D2
Figure 2. Power Supply Connection With Booster
BOOSTVcc
VSWITCH
VCC
AVCC C1
D1
L1
3.3V
2.7V to 3.6V
Power Supply
Figure 3. Power Supply Connection Without Booster
Table 12.Charge Pump Interface Pins
Pin Name Pin Number
BOOSTVcc F1
VSWITCH E2
Figure 4. Crystal Interface
BOOSTVcc
VSWITCH
VCC
AVCC
3.0V to 3.6V
Power Supply
Y1
C1 = 22 pF C2 = 22 pF
CY7C67200
XTALIN
XTALOUT
12MHz
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
[+] Feedback

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Document #: 38-08014 Rev. *G Page 7 of 78
Crystal Pins
Boot Configuration Interface
EZ-OTG can boot into any one of four modes. The mode it
boots into is determined by the TTL voltage level of
GPIO[31:30] at the time nRESET is deasserted. Table 14
shows the different boot pin combinations possible. After a
reset pin event occurs, the BIOS bootup procedure executes
for up to 3 ms. GPIO[31:30] are sampled by the BIOS during
bootup only. After bootup these pins are available to the appli-
cation as GPIOs.
GPIO[31:30] must be pulled high or low, as needed, using
resistors tied to VCC or GND with resistor values between 5K
ohm and 15K ohm. GPIO[31:30] must not be tied directly to
VCC or GND. Note that in Standalone mode, the pull ups on
those two pins are used for the serial I2C EEPROM (if imple-
mented). The resistors used for these pull ups must conform
to the serial EEPROM manufacturer's requirements.
If any mode other then standalone is chosen, EZ-OTG will be
in coprocessor mode. The device will power up with the appro-
priate communication interface enabled according to its boot
pins and wait idle until a coprocessor communicates with it.
See the BIOS documentation for greater detail on the boot
process.
Operational Modes
There are two modes of operation: Coprocessor and
Standalone.
Coprocessor Mode
EZ-OTG can act as a coprocessor to an external host
processor. In this mode, an external host processor drives
EZ-OTG and is the main processor rather then EZ-OTG’s own
16-bit internal CPU. An external host processor may interface
to EZ-OTG through one of the following three interfaces in
coprocessor mode:
• HPI mode, a 16-bit parallel interface with up to 16 MBytes
transfer rate
• HSS mode, a serial interface with up to 2M baud transfer
rate
• SPI mode, a serial interface with up to 2 Mbits/s transfer
rate.
At bootup GPIO[31:30] determine which of these three inter-
faces are used for coprocessor mode. Refer to Table 14 for
details. Bootloading begins from the selected interface after
POR + 3 ms of BIOS bootup.
Standalone Mode
In standalone mode, there is no external processor connected
to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an
EEPROM. Optionally, firmware may also be downloaded via
USB. Refer to Table 14 for booting into standalone mode.
After booting into standalone mode (GPIO[31:30] = ‘11’), the
following pins are affected:
• GPIO[31:30] are configured as output pins to examine the
EEPROM contents.
• GPIO[28:27] are enabled for debug UART mode.
• GPIO[29] is configured as OTGID for OTG applications on
PORT1A.
— If OTGID is logic 1 then PORT1A (OTG) is configured
as a USB peripheral.
— If OTGID is logic 0 then PORT1A (OTG) is configured
as a USB host.
• Ports 1B, 2A, and 2B default as USB peripheral ports.
• All other pins remain INPUT pins.
Table 13.Crystal Pins
Pin Name Pin Number
XTALIN G3
XTALOUT G2
Table 14.Boot Configuration Interface
GPIO31
(Pin 39) GPIO30 (Pin 40) Boot Mode
0 0 Host Port Interface (HPI)
0 1 High Speed Serial (HSS)
1 0 Serial Peripheral Interface (SPI, slave
mode)
1 1 I2C EEPROM (Standalone Mode)
[+] Feedback

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Minimum Hardware Requirements for Standalone Mode – Peripheral Only
Power Savings and Reset Description
The EZ-OTG modes and reset conditions are described in this
section.
Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For
detailed information on Sleep mode; See section “Sleep”.
Sleep mode is used for USB applications to support USB
suspend and non USB applications as the main chip power
down mode.
In addition, EZ-OTG is capable of slowing down the CPU clock
speed through the CPU Speed register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock
speed from 48 MHz to 24 MHz reduces the overall current
draw by around 8 mA while reducing it from 48 MHz to 3 MHz
reduces the overall current draw by approximately 15 mA.
Sleep
Sleep mode is the main chip power down mode and is also
used for USB suspend. Sleep mode is entered by setting the
Sleep Enable (bit 1) of the Power Control register [0xC00A].
During Sleep mode (USB Suspend) the following events and
states are true:
• GPIO pins maintain their configuration during sleep (in
suspend).
• External Memory Address pins are driven low.
• XTALOUT is turned off.
• Internal PLL is turned off.
• Firmware must disable the charge pump (OTG Control
register [0xC098]) causing OTGVBUS to drop below 0.2V.
Otherwise OTGVBUS will only drop to VCC – (2 schottky
diode drops).
• Booster circuit is turned off.
• USB transceivers is turned off.
• CPU suspends until a programmable wakeup event.
Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only
EZ-OTG
CY7C67200
GPIO[30]
GPIO[31] SCL*
SDA*
10k
Bootstrap Options
Bootloading Firmware
*Bootloading begins after POR + 3ms BIOS bootup
Vcc
10k
Vcc
A2
GND
A0
A1 SCL
SDA
VCC
WP
VCC
Up to 64k x8
EEPROM
*GPIO[31:30] 31 30
Up to 2k x8 SCL SDA
>2k x8 to 64k x8 SDA SCL
Int. 16k x8
Code / Data
XOUT
XIN 12MHz
22pf
22pf
nRESET Reset
Logic
*Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
VCC, AVCC,
BoostVCC
VReg
DMinus
DPlus
Standard-B
or Mini-B
D+
VBus
GND
D-
SHIELD
Reserved
GND, AGND,
BoostGND
[+] Feedback

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External (Remote) Wakeup Source
There are several possible events available to wake EZ-OTG
from Sleep mode as shown in Table 15. These may also be
used as remote wakeup options for USB applications. See
section “Power Control Register [0xC00A] [R/W]” on page 13.
Upon wakeup, code begins executing within 200 ms, the time
it takes the PLL to stabilize.
Power-On Reset (POR) Description
Thelengthofthe power-on-reset eventcanbedefinedby(VCC
ramp to valid) + (Crystal start up). A typical application might
utilize a 12-ms power-on-resetevent = ~7 ms+ ~5 ms,respec-
tively.
Reset Pin
The Reset pin is active low and requires a minimum pulse
duration of sixteen 12-MHz clock cycles (1.3 ms). A reset
event restores all registers to their default POR settings. Code
execution then begins 200 ms later at 0xFF00 with an imme-
diate jump to 0xE000, the start of BIOS.
Note It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as out-
puts for a test mode. If these pins need to be used as inputs,
a series resistor is required (10 ohm to 48 ohm is recommend-
ed). Refer to BIOS documentation for addition details.
USB Reset
A USB Reset affects registers 0xC090 and 0xC0B0, all other
registers remain unchanged.
Memory Map
Memory map information is presented in this section.
Mapping
The EZ-OTG has just over 24 KB of addressable memory
mapped from 0x0000 to 0xFFFF. This 24 KB contains both
program and data space and is byte addressable. Figure 6.
shows the various memory region address locations.
Internal Memory
Of the internal memory, 15 KB is allocated for user’s program
and data code. The lower memory space from 0x0000 to
0x04A2 is reserved for interrupt vectors, general purpose
registers, USB control registers, the stack, and other BIOS
variables. The upper internal memory space contains EZ-OTG
control registers from 0xC000 to 0xC0FF and the BIOS ROM
itself from 0xE000 to 0xFFFF. For more information on the
reserved lower memory or the BIOS ROM, refer to the
Programmers documentation and the BIOS documentation.
During development with the EZ-OTG toolset, the lower area
of User's space (0x04A4 to 0x1000) should be left available to
load the GDB stub. The GDB stub is required to allow the
toolset debug access into EZ-OTG.
Figure 6. Memory Map
Table 15.wakeup Sources[3, 4]
Wakeup Source (if enabled) Event
USB Resume D+/D– Signaling
OTGVBUS Level
OTGID Any Edge
HPI Read
HSS Read
SPI Read
IRQ0 (GPIO 24) Any Edge
Notes
3. Read data will be discarded (dummy data).
4. HPI_INT will assert on a USB Resume.registers
HW INTs
SW INTs
0x0000 - 0x00FF
Primary Registers
Swap Registers
USB Registers
HPI Int / Mailbox
Slave Setup Packet
BIOS
USER SPACE
~15K
Internal Memory
Control Registers
0x0100 - 0x011F
0x0120 - 0x013F
0x0140 - 0x0148
0x014A - 0x01FF
0x0200- 0x02FF
LCP Variables
0x0300- 0x030F BIOS Stack0x0310- 0x03FF USB Slave & OTG0x0400- 0x04A2
0x04A4- 0x3FFF
0xC000- 0xC0FF
0xE000- 0xFFFF
[+] Feedback

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Registers
Some registers have different functions for a read vs. a write
access or USB host vs. USB device mode. Therefore,
registers of this type have multiple definitions for the same
address.
The default register values listed in this data sheet may be
altered to some other value during BIOS initialization. Refer to
the BIOS documentation for Register initialization information.
Processor Control Registers
There are eight registers dedicated to general processor
control. Each of these registers is covered in this section and
is summarized in Table 16.
CPU Flags Register [0xC000] [R]
Figure 7. CPU Flags Register
Register Description
The CPU Flags register is a read only register that gives
processor flags status.
Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Inter-
rupts are enabled.
1: Enabled
0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation
results in a negative answer.
1: MS result bit is ‘1’
0: MS result bit is not ‘1’
Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition has
occurred. An overflow condition can occur if an arithmetic
result was either larger than the destination operand size (for
addition) or smaller than the destination operand should allow
for subtraction.
1: Overflow occurred
0: Overflow did not occur
Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted
in a carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted
in a ‘0’.
1: Zero occurred
0: Zero did not occur
Table 16.Processor Control Registers
Register Name Address R/W
CPU Flags Register 0xC000 R
Register Bank Register 0xC002 R/W
Hardware Revision Register 0xC004 R
CPU Speed Register 0xC008 R/W
Power Control Register 0xC00A R/W
Interrupt Enable Register 0xC00E R/W
Breakpoint Register 0xC014 R/W
USB Diagnostic Register 0xC03C W
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write --------
Default 00000000
Bit # 76543210
Field
...Reserved Global
Interrupt
Enable
Negative
Flag Overflow Flag Carry Flag Zero Flag
Read/Write - - - R R R R R
Default 0 0 0 X X X X X
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