Cypress AN204772 User manual

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www.cypress.com Document No. 002-04772 Rev. *B 1
AN204772
F²MC-16FX Family, Hardware Set Up
This application note describes how to set up a hardware environment for Cypress 16FX MCUs.
Contents
1Introduction...............................................................1
2Minimal System........................................................1
2.1 Schematic........................................................2
2.2 Serial Interface.................................................2
2.3 Power supply...................................................2
2.4 Analog Digital Converter Supply Pins..............2
2.5 Analog Input Pins.............................................3
2.6 Reset Pin (RSTX) ............................................3
2.7 C Pin................................................................3
2.8 Clock Source ...................................................3
2.9 Mode Pins........................................................3
3Layout and Electromagnetic Compatibility................4
3.1 General............................................................4
3.2 Power Line Routing .........................................4
3.3 C Pin Decoupling.............................................5
3.4 Power Supply Decoupling................................6
3.5 Quartz Crystal Placement
and Signal Routing ..........................................8
3.6 Other documents.............................................8
3.7 MCU Pin Summary..........................................9
4Port Input / Unused Pins / Latch-up........................10
4.1 Port Input / Unused Pins................................10
4.2 Latch-up consideration (switch).....................11
5Minimum Flash Programming Connection .............14
5.1 Run mode and Programming Mode...............14
5.2 Programming Pins.........................................14
5.3 Asynchronous Programming .........................15
5.4 Synchronous Programming...........................15
5.5 External Watchdog during
Flash Programming .......................................16
6Background Debugging USART.............................18
6.1 Background Debugging Mode .......................18
7Document History...................................................19
1 Introduction
This application note describes how to set up a hardware environment for Cypress 16FX MCUs. As an example the
MB96F34x MCU is used.
2 Minimal System
This Chapter Gives an Example of a Minimum Hardware System

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www.cypress.com Document No. 002-04772 Rev. *B 2
2.1 Schematic
The following graphic shows a schematic of a minimum hardware system. Note that for other MCU families a different
pinning is needed.
*1 only needed for dual clock devices.
*2 please refer to chapter 3
*3 If PCB has good EMI routing, resistors can be 0Ω for mode pins
2.2 Serial Interface
The “PC connection” section is only needed, if no 5V external serial data lines for programming are existing. The
MAX232 is a standard level shifter, which converts the 5V levels of the MCU to 12V RS232V24 levels and vice
versa.
If you use a 3.3V system a MAX3232 is recommended.
Please consider, that the internal charge pumps of the level shifter can produce noise on the +5 Volts line, which can
influence the ADC, if AVcc and AVRH are directly (unfiltered) connected to it.
If the system is set to Background Debugging Mode (BDM), the used DBM-USART SIN pin shall be terminated to
VCC. Please see chapter 6 for details.
2.3 Power supply
The power supply should be from 3 Volts to 5.5 Volts for normal usage. If a different supply voltage is used please
refer to the MB96340 data sheet.
2.4 Analog Digital Converter Supply Pins
The analog converter supply pins (AVcc, AVss, AVRH, AVRL) should be connected even if the ADC of the MCU is
not used. Please refer to our application note mcu-an-300215-e-16fx_adc for using the ADC and pin connection.

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2.5 Analog Input Pins
Because the ADC works with an internal sample capacitor the input impedance and external capacity must be low.
Cypress recommends an input impedance of not more than 15k Ohm. Choose the external capacity as low as
possible (about 1 nF for EMI protection).
2.6 Reset Pin (RSTX)
To reset the MCU a switch connects this pin to Vss (Ground). Additionally a capacitor has to be connected between
Vss and the reset pin for debouncing the switch and for EMI protection. From experience Cypress recommend a
capacity of not more than 1 nF. This capacity covers the most common frequency protection in a wide range. Higher
capacities and high impedance may cause latch-up effects together with an RSTX-Switch and low EMI protection.
For further information please refer to the general application note mcu-an-300219-e-16fx_reset.
2.7 C Pin
A 1..10µF ceramic capacitor (dielectric X7R, e. g. 4,7µF) must be connected close to the C pin of the MCU.
Otherwise the MCU may not operate correct or will be damaged in worst case. Also see chapter 3.
2.8 Clock Source
A clock source must be provided to the MCU. Therefore crystals or external clock signals can be used. For external
source pin X0 (X0A) is used whereby pin X1 (X1A) is not connected.
The sub clock X0A pin has to be pulled down, if sub clock is not used.
Please also refer to the chapter Outline/Precautions for Device Handling in the corresponding hardware manual for
details.
2.9 Mode Pins
The mode pins signalize the MCU the current operation mode. For a minimal system only two modes are necessary:
Flash-Asynchronous-Serial-Programming-Mode and Run Mode. They should be pulled-up with 2k resistors. If the
PCB routing protects ESD and EMI influence, the mode pins can be connected directly to Vss and ground, but please
see chapter 4.
For these programming modes and methods please refer to the application notes mcu-an-300224-e-v10-
16fx_mcu_flash_prog_bi_rom.
The following settings are used for the both modes mentioned above:
2.9.1 Flash-(A)synchronous-Serial-Programming-Mode
MD0
MD1
MD2
0
1
0
2.9.2 Run Mode
MD0
MD1
MD2
1
1
0
2.9.3 NC Pins
Do not leave input pins open. Disable input pin functionality with PIERxy_IEz = 0; in this case.
Please read Chapter 4 for how to proceed with unused (not connected) pins.

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3 Layout and Electromagnetic Compatibility
This Chapter Gives Some Tips for Layout Design
3.1 General
To avoid ESD problems and noise emission of the system some rules for the layout design has to be observed.
The most critical point is the C pin because this is the connection to the internal 1.8 V supply for the MCU core. Thus
the two decoupling capacitors have to be placed very near to this pin.
Also the ground and Vcc routing has to be done carefully. Vcc lines should be routed in star shape. We recommend a
Vss ground plane on the mounting side just under the MCU. For both Vcc and Vss only one connection to the rest of
the circuit should be done, otherwise noise is carried-over from and to the MCU. Decoupling capacitors (DeCaps) has
to be placed as nearest as possible to the related pins. If they are placed too far away their function becomes
useless.
If crystals are used, they have to be placed as nearest as possible to the Xn(A) pins.
If possible all decoupling capacitors should be placed on the same mounting side as the MCU.
3.2 Power Line Routing
In general the Vcc and Vss lines should not be routed in “chains”, but in “star shape”. For Vss a ground plane is
recommended which covers the chip package, and is connected in one point to Vss of the whole circuit.
Below is a example of a bad and a good power line routing:

F²MC-16FX Family, Hardware Set Up
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3.3 C Pin Decoupling
The following routing and placement for single sided metal layer is recommended (Note, that in all following
illustrations the mounting metal layer is drawn in black and the back side metal layer in gray):
The following routing and placement for double sided metal layer is recommended. Note, that despite the capacitors
are placed on the opposite side as the MCU, this solution is the best.

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3.4 Power Supply Decoupling
DeCaps for power supply have to be placed within the “current flow”. Otherwise they are senseless, because then
their function become inoperable. The following graphic illustrates this:
For EMI reasons all decoupling capacitors should have the same capacitance, so that all have a common resonance
frequency. Cypress recommends 10nF (~100 MHz resonance) to 100nF (~10 MHz resonance) depending on
application. For further detailed information please refer to the application note 16bit-EMC-Guideline.
The following routing and placement for single sided metal layer is recommended:

F²MC-16FX Family, Hardware Set Up
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The following routing and placement for double sided metal layer is recommended. Note, that despite the capacitor is
placed on the opposite side as the MCU, this solution is the best like for the C pin.
If mounting on both sides is not possible the following placement and routing is recommended:

F²MC-16FX Family, Hardware Set Up
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3.5 Quartz Crystal Placement and Signal Routing
The crystal has to be placed as nearest as possible to the MCU. Therefore the oscillator capacitors have to be placed
“behind” the crystal.
For single metal layer circuit board the following placement and signal routing is recommended:
For double sided metal layer layout the following is recommended:
3.6 Other documents
For further detailed information please refer to the application note 16bit-EMC-Guideline.

F²MC-16FX Family, Hardware Set Up
www.cypress.com Document No. 002-04772 Rev. *B 9
3.7 MCU Pin Summary
The following table shows the EMC critical pins and gives short information about how to connect them.
Pin name
Function
VCC
Main supply for IO buffer MCU core, close to input the internal 3.3V regulator, close to crystal oscillator
VSS
Main supply for IO buffer and MCU core, close to the internal 3.3V regulator, close to crystal oscillator
C
External 1..10µF ceramic capacitor (dielectric X7R) as smooth capacitors for internal 1.8V regulator
output, it is used for supply of the MCU core. Note, that this pin leads the most of noise. Please refer to the
DS of used MCU series for selection of capacitance value.
AVCC*
Power supply for the A/D converter
AVSS*
Power supply for the A/D converter
AVRL*
Reference voltage input for the A/D converter
AVRH*
Reference voltage input for the A/D converter
DVCC*, HVCC*
Power supply for the PWM (high current) outputs, it is not connected to VCC, should be connected to
extra power supply
DVSS*, HVSS*
Power supply for the PWM (high current) outputs, it is not connected to VSS, should be connected to extra
power supply
X0, X0A*
Oscillator input, if not used so shall be connected with pull-up or pull-down resistor (see please DS)
X1, X1A*
Oscillator output, the crystal and bypass capacitor must be connected via shortest distance with X1 pin, if
not used so shall be open
*only if supported by device