Cypress FX2LP User manual

Application Note Please read the Important Notice and Warnings at the end of this document 001-65209 Rev.*I
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AN65209
Getting Started with FX2LP™
About this document
Scope and purpose
AN65209 introduces you to the EZ-USBFX2LPUSB 2.0 device controller. This application note helps you
build a project for FX2LP and explore its various development tools, and then guides you to the appropriate
documentation to accelerate in-depth learning about FX2LP.
Associated part family
CY7C68013A/14A/15A/16A/53
Associated project
Yes
Software version
None
More code examples? We heard you.
To access a variety of FX2LP code examples, please visit our USB High-Speed Code Examples webpage.
To access USB 3.0 product family, please visit our USB 3.0 Product Family webpage.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 3
1.1 Bulkloop_FX2LP Project..........................................................................................................................3
1.1.1 VS_Control Center..............................................................................................................................3
1.1.2 Bulkloop_VCS.....................................................................................................................................3
1.1.3 Windows Driver and Library...............................................................................................................3
2USB 2.0 ................................................................................................................................. 4
3FX2LP Introduction ................................................................................................................ 5
3.1 FX2LP Features........................................................................................................................................5
3.1.1 USB Interface......................................................................................................................................5
3.1.2 Parallel interfaces ..............................................................................................................................6
3.1.2.1 Slave FIFO......................................................................................................................................6
3.1.2.2 General Programmable Interface.................................................................................................7
3.2 Serial interfaces.......................................................................................................................................8
3.3 CPU and Memory.....................................................................................................................................8
3.3.1 8051 ....................................................................................................................................................8
3.3.2 Boot Options ......................................................................................................................................8
3.3.2.1 Package Choices ...........................................................................................................................8

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Table of contents
3.4 Example Applications of FX2LP.............................................................................................................10
3.4.1 Interfacing FPGA/ASIC using Slave FIFO..........................................................................................10
3.4.2 Further Reading................................................................................................................................10
3.4.3 Booting an FPGA from FX2LP...........................................................................................................11
3.4.4 Further Reading................................................................................................................................11
4Cypress Design Resources ......................................................................................................12
5FX2LP Development Tools......................................................................................................14
5.1 FX2LP Development Board ...................................................................................................................15
5.2 Running the Bulkloop Demo.................................................................................................................16
5.2.1 Using USB Control Center................................................................................................................16
5.2.2 Using BULKLOOP_VCS.....................................................................................................................19
5.3 FX2LP Firmware Development .............................................................................................................20
5.3.1 Keil uVision2.....................................................................................................................................20
5.3.2 Cypress USB Firmware Frameworks ...............................................................................................20
5.3.2.1 TD_Init.........................................................................................................................................22
5.3.2.2 TD_Poll ........................................................................................................................................22
5.3.2.3 Interrupt Service Routines..........................................................................................................23
5.3.2.4 Handling USB Dual Speeds.........................................................................................................23
5.3.3 Building the Bulkloop Project..........................................................................................................24
5.4 GPIF Designer ........................................................................................................................................25
6The Windows Side .................................................................................................................27
6.1 Cypress USB Driver................................................................................................................................27
6.1.1 Driver/Library Alternatives ..............................................................................................................27
6.2 Cypress Libraries ...................................................................................................................................28
7Summary .............................................................................................................................30
8Appendix A: FX2LP Development Kit (DVK)...............................................................................31
8.1 Firmware Example Projects ..................................................................................................................31
9Appendix B: Additional USB Hi-Speed Devices from Cypress.......................................................34
10 Appendix C: Third-Party Development Kits and SDKs ................................................................35
10.1 Third-party SDKs ...................................................................................................................................35
11 Appendix D: Application Notes and Reference Designs...............................................................36
11.1 Application Notes..................................................................................................................................36
12 Appendix E: Adding Custom VID and PID to the .inf File ..............................................................39
Revision history.............................................................................................................................41

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Getting Started with FX2LP™
Introduction
1Introduction
The Cypress EZ-USB FX2LP (hereafter abbreviated as FX2LP) is a flexible USB 2.0 PERIPHERAL controller
designed to handle maximum USB 2.0 bandwidth. To take full advantage of the USB 2.0 480 Mbps signaling
rate, FX2LP contains specialized hardware to buffer the USB data and connect seamlessly to a variety of high-
bandwidth external devices such as MCUs, ASICs, and FPGAs. After a brief introduction to USB 2.0, this
application note describes FX2LP features that contribute to its high throughput.
Any IC is only as good as the tools that support it, so the remaining sections of this application note introduce
the FX2LP Development Kit (DVK) and the FX2LP firmware and software development tools. A companion zip
file contains folders with code samples and an application is described in detail in this application note. Briefly,
they are as follows:
1.1 Bulkloop_FX2LP Project
The Bulkloop project attached to this application note shows how to structure the FX2LP firmware to create a
USB device. Much of the USB request handling is done by a Cypress-provided USB Firmware Framework, with
the user code required only for the specific application requirements. The bulkloop.c file contains a full USB
device template that can serve as the basis for a custom application.
Cypress tools include a free evaluation version of Keil uVision2 for the FX2LP CPU (8051). The Keil uVision2
Integrated Development Environment (IDE) compiles the user code and USB Firmware Framework to produce
the hex file. This hex file needs to be loaded by the provided USB Control Center application and exercised by
the provided Bulkloop_VCS application.
As part of the firmware tools discussion, the GPIF Designer program is introduced to show how custom
interfaces are created using graphical waveform entry (see GPIF Designer).
1.1.1 VS_Control Center
This is a Microsoft Visual Studio solution, written in Visual C#, that creates an application called USB Control
Center. This application is used to download the FX2LP code (a hex file) into the FX2LP Development Kit. The
executable is provided for instant use and the source code is provided for reference. It uses the Cypress .NET
library, demonstrating the use of many of its high-level functions.
1.1.2 Bulkloop_VCS
This is a simple Windows Visual Studio application written in Visual C#. It features continuous data looping and
byte counting that can be used to measure USB transfer bandwidths with various USB controller cards and
computers. As with the USB Control Center, both the source code and executable are provided.
1.1.3 Windows Driver and Library
Cypress provides a Windows driver to support FX2LP-based designs. It supports all USB transfer types, and is
available in binary form for use with customer products.
The USB Control Center and Bulkloop_VCS applications use CyUSB.dll,a managed Microsoft .NET class library
provided by Cypress. This makes it compatible with the Visual Basic.NET, Visual C#, Visual C++ (Win Forms), and
Visual J# languages. This library provides high-level calls that hide driver complexity and present a very simple
USB programming model.

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Getting Started with FX2LP™
USB 2.0
2USB 2.0
USB standardizes the connection of computer peripherals, such as keyboards, mice, printers, thumb drives,
hard disks, and portable media players. USB provides communication and power to peripheral devices. USB
has become the dominant connectivity solution for PCs and consumer devices. Its popularity is largely due to
its ease of use, achieved by its standardized and robust underlying structure.
The USB 1.0 specification, released in 1996, defined two transfer speeds to address common device types of the
time. Low-speed devices operate at 1.5 Mbps to support devices such as keyboards and joysticks. Full-speed
devices operate at 12 Mbps to support higher bandwidth devices, such as printers and disk drives. A minor
specification revision 1.1, released in 1998, mostly addressed hub issues and became the widely adopted first-
generation specification.
The USB 2.0 specification was released in 2000. It increased the signaling rate to 480 Mbps, naming it Hi-Speed.
The 2.0 specification is compatible with the previous transfer rates.
The USB 3.0 specification, released in 2008, further increased the signaling rate to 5 Gbps, calling it
SuperSpeed. The Cypress FX3 family supports this speed.
The subject of this application note is the Cypress FX2LP, which operates at Hi-Speed and Full-speed. Appendix
Blists other Hi-Speed devices available from Cypress. All USB controllers from Cypress are listed here. For
more details of USB 2.0, refer to USB 101: An Introduction to Universal Serial Bus 2.0.

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FX2LP Introduction
3FX2LP Introduction
FX2LP integrates a USB 2.0 transceiver, a smart serial interface engine (SIE), large data buffers, an enhanced
8051 microcontroller, and a programmable peripheral interface in a single chip. A simplified FX2LP block
diagram is shown in Figure 1.
Figure 1 FX2LP Block Diagram
The function of FX2LP is to transfer data between a USB host and a peripheral device. FX2LP provides this
connectivity using parallel and serial interfaces. In systems where the FX2LP CPU is not required to modify the
data before sending it to the USB host, the FX2LP firmware only needs to initialize its hardware transfer units,
allowing high-bandwidth USB transfers to proceed without CPU intervention.
FX2LP can be programmed to enumerate as any USB device type, conforming to a standard USB class, such as
HID or mass storage, or a custom device.
3.1 FX2LP Features
This section briefly describes the key features of FX2LP.
3.1.1 USB Interface
Hi-Speed USB transfers can be visualized as supporting two ends of a pipe. On one end, the pipe receives and
sends data at 480 Mbps over the USB interface, as shown in Figure 2. The other end of the pipe is described in
Parallel interfaces.

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FX2LP Introduction
Pipe
(FIFO)
SIE
PHY
VBUS
D+
D-
GND 480 Mbits/sec
Figure 2 USB Connection to a Data Pipe
To handle the USB host side, FX2LP includes:
•A physical bus interface (PHY) containing a USB 2.0 transceiver that supports Hi-Speed and Full Speed USB
transfers.
•A Smart serial interface engine (SIE). The SIE translates PHY signals into bytes. All Cypress USB SIEs add logic
to handle low-level USB details, such as error correction and Packet ID (PID) synchronization, relieving the
programmer of these tasks. This Smart SIE delivers bytes to an endpoint FIFO memory. The Smart SIE also
contains logic to enumerate FX2LP as a full-fledged USB device and also capable of loading code into its
internal RAM.
•Seven endpoints that support all four USB transfer types: CONTROL, BULK, INTERRUPT, and ISOCHRONOUS.
An endpoint is a transmitter or receiver of USB data.
•Large endpoint buffers (FIFOs) with multiple buffering. Double, triple, or quad buffering allows USB transfers
to be pipelined with a peripheral, increasing the throughput.
•Low-power operation (the “LP” in FX2LP). The USB VBUS wire supplies 5 V, which provides limited power to
peripheral devices. The low-power consumption of FX2LP enables you to create bus-powered applications.
For example, the FX2LP Development Kit is bus-powered, eliminating the need for an external power unit.
FX2LP can also be used in self-powered designs in which the peripheral device supplies its own power.
3.1.2 Parallel interfaces
The USB 2.0 specification and generous FX2LP buffering take care of transporting bytes in and out of endpoint
FIFOs at high speed over the USB interface, but that is only half of the job. The other end of the pipe must
transport the FIFO data on and off chip at speeds matching USB transfer rates. FX2LP contains two hardware
interfaces specifically designed for this purpose: Slave FIFO and general programmable interface (GPIF), as
shown in Figure 1.
Note: In addition to the high-speed transfer logic, the FX2LP 8051 has random access to the endpoint
FIFOs for applications that require interpreting or modifying the data that is moving between the
USB and peripheral interfaces.
3.1.2.1 Slave FIFO
FX2LP provides a Slave FIFO interface for use by external devices containing a FIFO controller, such as an MCU,
FPGA, or ASIC (see Figure 3).
Pipe
(FIFO)
Slave FIFO
Logic
Data
Clock
Flags
Control
FIFO Address
Figure 3 FX2LP Slave FIFO Interface

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FX2LP Introduction
The Slave FIFO interface:
•Provides a data bus that is 8 or 16 bits wide.
•Operates either asynchronously (no clock) or synchronously (with clock).
•Accepts an external clock or uses an internal FX2LP 30-/48-MHz clock (in synchronous mode), which it makes
available on the CLKOUT pin. There is no need of crystal for the external peripheral device if it can work
based on the clock provided on the CLKOUT pin.
•Has output flags indicating FIFO status, such as full and empty.
•Has control inputs OE#, RD#, and WR#.
•Has two address lines to select one of four FX2LP FIFOs.
•Automatically launches USB transfers when the FIFO fills or empties.
•Has a control signal (PKETND) that the interface device can use to launch a “short packet” (FIFO has data
but is not full). Short packets routinely occur as the final packet of a long USB transfer.
In systems where data processing is not required in FX2LP, the FX2LP Slave FIFO interface requires minimal
firmware just to select the Slave FIFO interface and to configure the flags to indicate the status of the FIFOs.
Waveforms and timing values for the Slave FIFO interface are given in the FX2LP datasheet.
3.1.2.2 General Programmable Interface
Not all external controllers are designed to connect to a FIFO. Therefore, FX2LP provides a high-speed interface,
GPIF (shown in Figure 4), which provides direct connection to common interfaces, such as disk drives, FPGAs,
and ASICs, without requiring additional glue logic. The GPIF’s core is a state machine—you must develop
waveforms using GPIF Designer to control the state machine. The GPIF is driven by one of the four Waveform
Descriptors, which are data structures containing all the waveform information. GPIF Designer relieves the
designer of understanding the descriptor formats. It uses the graphical waveform entry to create a C-language
source file, which can be included in an FX2LP project.
Pipe
(FIFO)
GPIF
Data
Clock
ADDR
Control
RDY
STATE
Waveform
Descriptors
Figure 4 FX2LP GPIF Interface
The GPIF (see the GPIF Designer section):
•Provides a data bus that is 8 or 16 bits wide.
•Operates synchronously (with clock).
•Accepts an external clock or uses an internal FX2LP 30-/48-MHz clock (in synchronous mode), which it makes
available on a device pin.
•Provides nine address outputs. Addresses can be initialized and incremented on a clock-by-clock basis.
•Provides six control (CTL) and ready (RDY) signals. Six control outputs are also programmable on a clock-by-
clock basis. As a simple example, RD# and WR# strobes can be created with programmable durations and
polarities using these control signals. Six ready inputs can be tested in a GPIF state machine to read status
and perform interface synchronization. Three state outputs (GSTATE [2:0]) indicate the GPIF state, useful for
debugging with a logic analyzer.

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FX2LP Introduction
3.2 Serial interfaces
•In addition to the USB and peripheral interfaces, FX2LP contains:
•An I2C master (only) which operates at 100 or 400 kHz.
•Two standard 8051 USARTs. These are standard UARTs with a synchronous option. The USART interface pins
are available on separate I/O pins, not multiplexed with GPIO pins.
•Up to 40 GPIOs. These pins are multi-purpose, serving as GPIO pins or pins that support the Slave FIFO or
GPIF interfaces. The Package Choices section illustrates these interface options.
3.3 CPU and Memory
3.3.1 8051
•FX2LP has an 8051 core with two USARTs, three counter/timers, and an enhanced interrupt system. The core
can use a 48 MHz, 24 MHz, or 12 MHz clock. The CPU is supported by 16KB of on-chip code/data RAM.
•The enhanced interrupt system uses an “Autovector” mechanism to automatically call one of the 27 USB
interrupt service routines (ISRs), depending on the USB activity that requires service. Automatically
incrementing pointer hardware (“Autopointers”) speed up block transfers.
3.3.2 Boot Options
•FX2LP uses RAM for program storage. FX2LP has the following boot options:
USB boot.
I2C boot.
Boot from external parallel memory.
•When connected to USB, its Smart SIE enumerates as a USB bootloader capable of loading program code
into its internal RAM. After the code is loaded, FX2LP electrically disconnects itself from USB and
immediately reconnects as the device defined by the downloaded code. This process is called
Re-Numeration™.
•The FX2LP program RAM also can be loaded at power-on from an external serial EEPROM. Boot options are
detailed in AN50963 - EZ-USB® FX1™/FX2LP™ Boot Options.
3.3.2.1 Package Choices
FX2LP is available in three packages, as Figure 5 shows:
•56-pin SSOP, QFN, and VFBGA.
•100-pin TQFP package.
•128-pin TQFP package.

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FX2LP Introduction
PC[7:0]/GPIFADR[7:0]
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
CTL[5:3]
RDY[5:2]
TxD1
RxD0
TxD0
RxD1
T1
INT4
INT5#
T2
WR# T0
RD#
EA
CS#
OE#
PSEN#
A[15:0]
D[7:0]
100
128
PD[7:0]
PB[7:0]
RDY0
RDY1
CTL0
CTL1
CTL2
XTALIN
XTALOUT
DPLUS
DMINUS
SCL
SDA
RESET#
WAKEUP#
XCLK
CLKOUT
INT0#/PA0
PA1/DA0
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
IORDY
DMARQ
IOW
IOR
DMACK
←INTRQ
→DA0
→DA1
→DA2
→CS0
→CS1
→DASP
→RESET
FIFO Data
GPIF
SLRD
SLWR
PRGFLAG
INFULL
OUTEMPTY
←INT0
←INT1
←SLOE
PA3
←FIFOADR0
←FIFOADR1
←PKTEND
PA7
FIFO Data
Slave FIFOSingle Chip
Figure 5 Three FX2LP Package Choices
The 56-pin package is the lowest-cost version of FX2LP. The signals on the left edge of the 56-pin block (in
Figure 5)are common to all package versions in the family. Three modes are available in all package versions:
single-chip, GPIF, and Slave FIFO. These modes define the signals shown on the right edge of the 56-pin block
(in Figure 5). The 8051 selects the interface mode using an internal register. Single-chip mode is the power-on
default configuration.
The 100-pin package adds functionality to the 56-pin package by adding 44 pins:
•Two additional 8-bit I/O ports, PORTC and PORTE.
•Seven additional GPIF controls (CTL) and ready (RDY) signals.
•Nine non-multiplexed control signals (two UARTs, three timer inputs, INT4, and INT5#).
•Eight additional control signals multiplexed on to PORTE.
•Nine GPIF address lines, multiplexed on to PORTC(8) and PORTE(1),
•RD# and WR# signals, which may be used as read and write strobes for PORTC.
The 128-pin package adds 8051 address and data buses and their control signals. These added pins allow
FX2LP to operate with an external 8051 memory. This package is used in the FX2LP Development Board.

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FX2LP Introduction
3.4 Example Applications of FX2LP
3.4.1 Interfacing FPGA/ASIC using Slave FIFO
In Figure 6, an FPGA or ASIC contains a FIFO controller that connects directly to the FX2LP Slave FIFO pins. The
FPGA/ASIC also connects to hardware that is specific to the application, such as a data logger or image sensor.
Although a synchronous FIFO is shown using the IFCLK signal, FX2LP also supports an asynchronous (no clock)
FIFO interface.
System
sensors,
data
channels
etc.
FPGA
ASIC FX2
LP
Sync Slave FIFO
PC
IFCLK
RD-WR-OE-CS
FLAGS
FIFOADR(2)
D(16/8)
PKTEND
USB 2.0
Figure 6 FPGA/ASIC Sees FX2LP as a FIFO
Further Reading
For more information about the FX2LP Slave FIFO interface, refer AN61345 - Designing with EZ-USB FX2LP™
Slave FIFO Interface using FPGA, which presents a detailed design example.
Refer to KBA222479 USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA for an example
project that implements a UVC framework to interface an image sensor with the Host PC/mobile phone using
the FX2LP device.
Some interface chips may provide the necessary FIFO interface signals without modification. For example, an
MPEG decoder can map its signals to the FX2LP FIFO as follows:
Table 1 MPEG Decoder Connections to FX2LP
MPEG Decoder Signals
FX2LP Signals
MPEG_CLK
IFCLK
MPEG_SYNC
PKTEND#
MPEG_VALID
SLWR#
D[7:0]
FD[7:0]
External Tuner Control
I2C bus
3.4.2 Further Reading
Cypress provides a reference design for a “TV Dongle”, documented at FX2LP DMB-T / H TV Dongle Reference
Design.
If an external chip does not exactly map to the FX2LP Slave FIFO signals, as in Table 1, the FX2LP GPIF can be
programmed to match the required signals without additional external logic.

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FX2LP Introduction
3.4.3 Booting an FPGA from FX2LP
FX2LP is all about efficient system integration. Figure 7 and Figure 8 illustrate another way FX2LP can save
external logic.
FPGA FX2LP PC
Bitstream
Boot
Memory
Figure 7 FPGA Boots from External Memory
At power-on, an FPGA boots its configuration bitstream using an external memory (Figure 7).
FPGA FX2LP PC
Bitstream
Figure 8 FPGA Boots through FX2LP
FX2LP can be configured to load the FPGA bitstream file from the PC as in Figure 8. This eliminates the need for
a boot memory and enables FPGA updates from the PC.
3.4.4 Further Reading
For an example implementation using a Xilinx Spartan-3E FPGA, refer AN63620 - Configuring a Xilinx Spartan-
3E FPGA Over USB Using EZ-USB FX2LP™.

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Cypress Design Resources
4Cypress Design Resources
Cypress FX2LP design resources include datasheets, application notes, evaluation kits, reference designs,
firmware examples, and software tools. The resources are summarized in Table 2.
Table 2 FX2LP Resource Summary
Design
Available Resources
Where To Find Resources
Hardware
Development Board –Schematic, Board
files and documentation
Development Kit (DVK) Schematic
Board files available with FX2LP DVK
installation
DVK User Guide
DVK Quick Start Guide
Hardware design guidelines including
recommendations for crystals, decoupling
capacitors for power supplies and PCB
layout
Application note –AN15456
IBIS model
http://www.cypress.com/?id=193&rtID=114
FX2LP
Firmware
Free version of Keil IDE (up to 4KB of code
size)
Available with FX2LPDVK installation
Firmware examples
Sync Slave FIFO firmware example in a
complete design with FPGA
Application note - AN61345
Firmware
Debug
Setting Up, Using, and Troubleshooting
the Keil Debugger Environment
Application note - AN42499
Serial (UART) Port Debugging of
FX1/FX2LP Firmware
Application note –AN58009
Host PC
Software
USB2.0 driver –cyusb.sys
Available with Suite USB installation. This
Suite USB installation file (.exe) is also
available with the FX2LP DVK installation.
Suite USB for Mac OS is also available. Use
FX3 SDK for Linux to get the host application
similar to Control Center for Linux platform.
Host application examples –Control
Center and Streamer applications
GPIF Interface
Design
GPIF Designer Tool that enables you to
design a GPIF waveform and generate
code to be integrated into firmware
Available with GPIF Designer installation. The
GPIF Designer installation file (.exe) is also
available with the FX2LP DVK installation.
Examples of popular GPIF
implementations
Application notes - AN57322 –Interfacing
SRAM with FX2LP over GPIF
AN66806 –EZ-USB® FX2LP™ GPIF Design
Guide
AN63787 –EZ-USB® FX2LP™ GPIF and Slave
FIFO Configuration Examples using 8-bit
Asynchronous Interface
Documentation on GPIF and instructions
for using the tool
GPIF Designer’s User Guide – available with
GPIF Designer Tool
Other Collateral
FX2LP Datasheet
http://www.cypress.com/?rID=38801

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Getting Started with FX2LP™
Cypress Design Resources
Design
Available Resources
Where To Find Resources
FX2LP Technical Reference Manual
http://www.cypress.com/?rID=38232
Application Notes
http://www.cypress.com/?id=193&rtID=76
Reference Designs
http://www.cypress.com/?id=193&rtID=201
Knowledge Base Articles
http://www.cypress.com/?id=193&rtID=118
Material on USB 2.0
http://www.beyondlogic.org/usbnutshell/usb1.shtml
AN57294 - USB 101: An Introduction to Universal Serial Bus 2.0
Third-party Development Kits
http://www.ztex.de/usb-fpga-1
http://www.opalkelly.com/products/xem6010/
Features of these development kits are given in Appendix C: Third-
Party Development Kits and SDKs.

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Getting Started with FX2LP™
FX2LP Development Tools
5FX2LP Development Tools
The steps involved in developing and testing the FX2LP firmware are shown in Figure 9.
Host PC
GPIF Designer FX2LP firmware project opened in
Keil uVision2 IDE USB Control Center
FX2LP DVK
Figure 9 Steps for Developing and Testing Firmware
1. Develop the interface waveforms using GPIF Designer to communicate with the peripheral device
connected to the GPIF of FX2LP. Export the .c file and integrate the .c file into the FX2LP firmware project.
This step is not required if you are not using the GPIF interface. More details on using the GPIF Designer are
described in the GPIF Designer section.
2. Develop the FX2LP firmware with the help of the firmware framework provided by Cypress. Integrate the .c
file that was exported from step 1. Build the firmware project using the Keil uVision2 IDE. This step
generates .hex and .iic file. The .hex file is for programming the RAM of FX2LP and the .iic file is for
programming the EEPROM that is connected to FX2LP. The FX2LP firmware framework and the steps to
build the FX2LP firmware are described in the FX2LP Firmware Development section.
3. Use the Control Center application to program the RAM of FX2LP or the EEPROM that is connected to FX2LP.
Usage of the Control Center application is shown in the Using USB Control Center section.
4. Verify the functionality of the firmware with the help of the FX2LP DVK. More details of the FX2LP DVK are
described in section 5.1 and Appendix A: FX2LP Development Kit (DVK).
The zip file accompanying this application note contains the following directory structure:
Figure 10 Application Note Folders
Note: The unzipped application note folder contains copies of various Cypress code samples and
development tools available for download. For convenience, they are collected in one folder. For
further development, check the Cypress web site for the most current file versions.
This section contains directions for creating and loading an FX2LP firmware example called bulkloop into an
FX2LP Development Kit. Along the way, it introduces various tools that ease design of any USB peripheral
device using FX2LP. If you do not have the FX2LP DVK, the instructions still provide an overview of the FX2LP

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FX2LP Development Tools
chip and tools available. This section shows how to create and run Windows applications to test the bulkloop
design.
5.1 FX2LP Development Board
Cypress Driver:
cyusb.sys, cyusbfx1_fx2lp.inf
PC
Figure 11 FX2LP Development Kit and Windows Driver
The FX2LP Development Kit is available at: http://www.cypress.com/?rID=14321.
Also included with this kit (and available for free download) is the development software package including a
free version of the Keil uVision2 IDE (limited in object size to 4 kilobytes) and C compiler. More details about the
DVK are in Appendix A.
To attach the board to a PC for the first time, follow these steps:
1. Prepare FX2LP board jumpers as shown in Table 3.
Table 3 EZ-USB FX2LP Board Jumper Settings
JP
State
Purpose
6,7
OUT
Memory is configured for development
2
IN
Power the board from USB connector
1,5,10
IN
Local 3.3V power source
3
IN
All 4 jumpers IN—activate 4 LEDs D2-D5
8
Either
Not used (for Remote Wakeup testing)
2. In the lower left corner of the board, move the EEPROM ENABLE slide switch to the “NO EEPROM” (down)
position. This enables the FX2LP chip to enumerate itself as a code loader. The other slide switch (EEPROM
SELECT) can be in either position.
3. Plug the FX2LP board into a PC USB port. If this is the first time, you should see a popup message to install a
USB driver. Navigate to the application note driver folder and select the sub-folder corresponding to your
Windows OS.
You can confirm a successful driver install by viewing the Windows Device Manager:

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Figure 12 FX2LP Board Driver (Bootloader) is Installed
After this driver is installed, any Windows apps that communicate with the FX2LP Development Board will
recognize it.
Before showing how to create the bulkloop.hex file, the next two sections illustrate how to use two Windows
apps to load and test the FX2LP firmware.
5.2 Running the Bulkloop Demo
5.2.1 Using USB Control Center
The Error! Reference source not found. folder contains a Microsoft Visual C# solution to create a Windows a
pplication called USB Control Center. This application is used to download the FX2LP firmware (a hex file) into
the FX2LP chip. After the firmware loads, the FX2LP board automatically detaches itself from USB and then re-
attaches as the device defined by the loaded hex file (ReNumerationTM). If the loaded hex file has custom
Vendor ID (VID) and Product ID (PID) then you need to add these values to the Cypress .inf file.
Cypress Driver: cyusb.sys
PC
bulkloop.hex
Figure 13 USB Control Center Loads Hex Files into the FX2LP Development Board.
Further Reading
For more information about adding custom VID and PID to the .inf file, refer to Appendix E: Adding Custom VID
and PID to the .inf File.
The USB Control Center also has a “Data Transfer” tab that allows you to initiate USB transfers into and out of
the FX2LP DVK to test the bulkloop application or any other firmware you write.
The attached zip file contains a Visual Studio solution (AN65209\USB Control Center) and its compiled binary.
To try it out, follow these steps:
1. Double click on the CyControl.exe file in either the Debug or Release folder (AN65209\USB Control
Center\bin\).

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You should see the FX2LP board along with other connected USB devices listed in the left panel. To simplify this
display to show only the FX2LP board, click the Device Class Selection tab in the right panel and uncheck
everything except the Devices served by the CyUSB.sys driver (or a derivative) item.
Then the left panel should look like Figure 14.
Figure 14 USB Control Center Finds the FX2LP Board.
2. Now you are ready to load the FX2LP firmware bulkloop.hex (AN65209\FX2LP Bulkloop Firmware) on to
the FX2LP DVK. Click on the Cypress device entry to highlight it, and then select Program FX2 > RAM. Open
the FX2LP Bulkloop Firmware folder and select the bulkloop.hex file. After the code loads, the FX2LP
Development Kit disconnects itself from USB and reconnects as the device created by the loaded firmware
bulkloop.hex (Figure 15). This is Cypress ReNumeration™ in action—FX2LP has enumerated twice, first as a
code loader and then as the loaded device.
The LED D5 should blink 8 times per second for a Hi-Speed USB attachment, and once per second for a Full
Speed attachment. You can observe this by looking at the toggling frequency of the LED D5 present on the
FX2LP DVK. For Hi-Speed USB attachment, you’ll see the LED blink slowly for a second or so, and then start
blinking quickly. This is because a USB device initially attaches at Full Speed, then negotiates the Hi-Speed
connection with the host. This is one of the many firmware details handled by the Cypress USB frameworks
described in the FX2LP Firmware Development section.
The 7-segment readout present on the FX2LP DVK should light up with the number zero, indicating the number
of packets ready to be transferred back to the host—none have been received and “looped back” yet.
Figure 15 The FX2LP Board Re-appears
Note: Before you load any hex file into the FX2LP DVK, you must first press the Reset button (Error! R
eference source not found., lower left corner) by keeping the “EEPROM ENABLE” switch in “NO
EEPROM” position to reset FX2LP and thereby enable the FX2LP boot loader.

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Figure 16 shows the interaction between USB Control Center and the FX2LP Development Board loaded with
the bulkloop.hex file. The bulkloop firmware enumerates as a Full Speed or Hi-Speed device depending on the
PC connection and copies (loops) BULK data it receives from OUT Endpoint 2 into an IN Endpoint 6 buffer for
transmission back to the PC. As the diagram indicates, the endpoints are double-buffered, a feature
demonstrated in this section.
Note: Because USB directions are host-centric, OUT means host to device, and IN means device to host.
The bulkloop firmware also contains the code for useful operations, such as controlling the LEDS and 7-
segment readout on the FX2LP Development Board, and using endpoint interrupts. This code is examined in
detail in the FX2LP Firmware Development section.
cyusb.sys
PC
FX2LP
EP2-OUT EP6-IN
Figure 16 USB Control Center Tests the Bulkloop Firmware
1. Expand the Bulkloop Example tree view in the Control Center to reveal the implemented BULK endpoints
(Figure 17).
Figure 17 Bulkloop Example Device Internals
2. Select the Data Transfer tab. Click on the Bulk out endpoint (0x02) entry in the left-hand panel, and notice
that the Transfer Data button is Transfer Data-OUT. Clicking this button leads to the following:
•512 bytes (with zero default values) transfer from the PC to the FX2LP DVK.
•LED D3 flickers to indicate the OUT transfer.
•The 7-segment readout increments to 1, indicating one packet has been received over EP2-OUT and loaded
into the EP6-IN endpoint FIFO, ready for transfer to the host.

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Figure 18 Successful BULK-OUT Transfer
1. Click the Transfer Data-OUT button again. The PC dispatches a second packet to FX2LP, and the 7-segment
readout increments to 2.
2. Highlight the Bulk in endpoint (0x86) entry. The Transfer button label now indicates -IN. Clicking this
button leads to the following:
•512 bytes transfer from FX2LP to the host, which it displays as hexadecimal values.
•LED D2 flickers to indicate the IN transfer.
•The 7-segment readout decrements to 1.
3. Click the Transfer Data-IN button again. The second queued packet transfers to the host, and the 7-
segment readout indicates 0 packets waiting. This sequence confirms the double-buffered operation of the
two endpoints.
4. Select the Bulk out endpoint again. Then, position the mouse cursor inside the Text to send box and type
1234. The hex values display in the Data to send box and the Bytes to Transfer box increments for every
digit typed. Click the Transfer Data-OUT button.
5. In the Text to send box, type abcdefg, then click the Transfer Data-OUT button.
6. Select the Bulk in endpoint, and leave the default Bytes to Transfer value of 512 bytes. Click the Transfer
Data-IN button twice to read the two packets of data that was transferred.
Figure 19 Two Packets OUT, Two Packets IN
As Figure 19 demonstrates, a feature of USB is that a USB peripheral always sends the smaller of bytes-
requested (512, in this example) and bytes-available (4 or 7).
5.2.2 Using BULKLOOP_VCS
A second Visual Studio project called Bulkloop_VCS performs streamlined transfers in and out of the FX2LP
Development Board. It continuously sends and receives BULK data while keeping a running total of bytes
transferred. Like the USB Control Center, it displays the device characteristics in the left panel for information.
Unlike the USB Control Center, it automatically sets up and conducts continuous transfers when the Start
button is pressed.

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Figure 20 Bulkloop_VCS Window
Before using this application, use the USB Control Center to load the bulkloop.hex file as described in the
previous section. Be sure to press the FX2LP Development Kit RESET button first to enable the FX2LP
bootloader by keeping the “EEPROM ENABLE” switch in “NO EEPROM” position.
5.3 FX2LP Firmware Development
This section explains the steps involved in generating the bulkloop.hex file.
5.3.1 Keil uVision2
The Cypress FX2LP DVK includes a free demonstration version of the Keil uVision2 tools for the 8051. This IDE is
fully featured, but limited in code size to 4096 bytes. Cypress demo projects, such as bulkloop.uv2, fit under
this limit so you can study and modify the code. Larger projects require purchasing the full uVision2 toolset
from Keil.
5.3.2 Cypress USB Firmware Frameworks
In conjunction with the Keil tools, Cypress provides a set of files called the USB Firmware Frameworks to handle
low-level USB details. This approach allows you to concentrate development time on your specific application
code.
When you open the bulkloop.uv2 project, you see the following project files:
Figure 21 bulkloop.uv2 Project Files
•fw.c is the Cypress USB Firmware Frameworks.
For more information on firmware frameworks, refer to Chapter 5 in FX2LP Development Kit User Guide.pdf.
•bulkloop.c is your application. Other Cypress examples may call this code module peripheral.c; it is a good
idea to rename it for your specific project name.