Cypress EZ-USB CX3 Product manual

EZ-USB® CX3 Technical Reference Manual
(Supplement to the EZ-USB FX3 Technical Reference Manual)
Doc. No. 001-91492 Rev. *B

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 2
Cypress EZ-USB CX3
1.1 Introduction
Cypress EZ-USB®CX3 is a USB 3.0 camera controller that enables developers to add USB 3.0 connectivity
to any image sensors conforming to the Mobile Industry Processor Interface (MIPI) Camera Serial Interface
Type 2 (CSI-2) standard. It serves as a MIPI CSI-2-to-USB Bridge.
EZ-USB CX3 is a variant of the EZ-USB FX3 device that features an integrated MIPI CSI-2 receiver mated to
the general programming interface II (GPIF II). CX3 provides the ability to add SuperSpeed USB connectivity
to image sensors supporting the MIPI CSI-2 interface.
CX3 conforms to the MIPI CSI-2 specification (version 1.01) and supports up to four data lanes with speed up
to 1 gigabits per second (Gbps) per lane for a total bandwidth of 2.4 Gbps.
CX3 is ideally suited forhigh-definition or high-speed image capturing applications and is capable of streaming
uncompressed video up to 1080p at 30 fps or 720p at 60 fps. CX3 supports a wide variety of image formats
including RAW8/10/12/14, YUV422, RGB888/666/565, and user-defined 8-bit.
Figure 1: EZ-USB® CX3 Device
Based on the proven EZ-USB FX3 platform, CX3 includes an ARM9™CPU and 512 KB SRAM that provide
200 MIPS of computational power. CX3 supports multiple peripheral interfaces such as I2C, SPI, and UART,
which can be programmed to support Autofocus, Pan, Tilt, and Zoom (PTZ), or other camera control functions.
CX3 uses the same application development tools as FX3. The FX3 Software Development Kit provides
support for CX3 along with application examples for accelerating time to market. CX3 complies with the USB
3.0 v1.0 specification and therefore is backward compatible with USB 2.0.
This technical reference manual (TRM) is a supplement to the EZ-USB FX3 TRM, and provides details about
the added CX3 MIPI CSI-2 receiver function block. Sections 1.5 through 1.9 of this TRM supplement describe
the MIPI CSI-2 receiver functional block, including the fixed-function GPIF II state machine. Section 1.10
provides the register details for the MIPI CSI-2 receiver interface. Detailed descriptions of the existing FX3

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 3
functional blocks, such as the CPU Subsystem, Memory, Global Controller, DMA, USB, and low-bandwidth
(serial and GPIO) peripherals are available in the EZ-USB FX3 TRM. Technical terms used in this TRM are
defined in the Glossary.
Figure 2 is the block diagram of FX3. Certain functional blocks are not included in CX3; these are shown in
red. The GPIF II, shown in blue, is included in CX3, but only with functionality specific to the camera interface.
Figure 2: FX3 Block Diagram
UART SPI I2S
I2C
GPIF II 32
EPs
HS/FS/LS
OTG Host
SS
Peripheral
HS/FS
Peripheral
Charger
Detection
(EZ-Dtect™)
USB Interface
ARM926EJ-S
JTAG
System
RAM
I2C_SDA
I2C_SCL
D+
D-
SSTX+
SSTX-
SSRX+
SSRX-
OTG_ID
FX3 BLOCK DIAGRAM
Memory
Controller
GPIOs
Not Available in CX3
Limited Functionality in CX3
Available in CX3
Figure 3 shows the CX3 block diagram, including the added MIPI CSI-2 functional block and the fixed-function
GPIF II interface available in CX3, highlighted in green.
Figure 3: CX3 Block Diagram
UART SPI I2S
I2C
Fixed
Function
GPIF II
32
EPs
SS
Peripheral
HS/FS
Peripheral
USB Interface
ARM926EJ-S
JTAG
System
RAM
D+
D-
SSTX+
SSTX-
SSRX+
SSRX-
CX3 BLOCK DIAGRAM
Memory
Controller
MIPI
CSI-2
Receiver
Block
I2C_SDA
I2C_SCL
MIPI
CSI2
Input
Image
Sensor
USB
Host
MCLK
XRESET
XSHUTDOWN
GPIOs
New Functionality in CX3

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 4
The differences between CX3 and FX3 devices are listed below.
Table 1: Differences Between FX3 and CX3 Devices
Feature
Supported in FX3
Supported in CX3
P-Port Support
Sync ADMux implemented with GPIF II
Yes
No
Async SRAM implemented with GPIF II
Yes
No
Async ADMux implemented with GPIF II
Yes
No
MMC Slave
Yes
No
GPIF II
Yes
Fixed-function GPIF II state
machine implemented to interface
with the CX3 MIPI CSI-2 receiver
block.
Low-Bandwidth Peripherals
I2S Master (Transmitter only)
Yes
Yes
SPI Master
Yes
Yes
UART
Yes
Yes
I2C Master Controller
Yes
Yes
U-Port Support
USB 3.0 Peripheral
Yes
Yes
USB 2.0 Peripheral
Yes
Yes
32 Physical endpoints
Yes
Yes
Charger Detection 1.1 Support (EZ-Dtect™)
Yes
No
Accessory Charger Adaptor (ACA) Support
Yes
No
Integrated Hi-Speed USB Switch
Yes
No
Carkit UART Pass-through mode
Yes
No
USB OTG (Hi-Speed, Full-Speed, Low-Speed host or
peripheral)
Yes
No
Clock input frequencies:
19.2 MHz,
26 MHz,
38.4 MHz,
52 MHz
19.2 MHz
Crystal input: 19.2 MHz
Yes
No
JTAG Support for debug only (Boundary Scan not
supported)
Yes
Yes
VBUS, VBAT signals
Separate VBUS, VBAT
signals for 5-V and
3.3-V operation
VBUS, VBAT combined to a
single signal VUSB. Supports 3.3-
V and 5-V operation.
GPIOs
42
12
Clock output for Image sensor
No
Yes
MIPI CSI-2 input
No
Yes

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 5
1.2 CX3 Features
CX3 supports the following features:
▪USB 3.0 and USB 2.0 peripheral controller compliant with the USB 3.0 specification 1.0
▪MIPI CSI-2 RX Interface
oMIPI CSI-2 conformant (Version 1.01 Revision 0.04 –April 2, 2009)
oSupports up to four data lanes; each lane supports up to 1 Gbps
oCamera Control Interface (over I2C) support for image sensor configuration
▪Supports the following video data formats:
oRAW 8/10/12/14
oYUV 422 (8/10bit)
oRGB 888 / 666 / 565
oUser-defined 8-bit
▪Twelve GPIOs for controlling camera-related functions (for example, lighting, sync in, sync out, etc.)
▪Support for I2C, SPI, I2S outputs, and UART interfaces, identical to FX3
▪JTAG interface for debugging

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 6
1.3 Block Diagram
Figure 4 is a detailed block diagram of a typical system using CX3 to transfer data from an image
sensor to a USB Host.
Figure 4: System Block Diagram
Image Sensor
Video
Data
Video
Control
USB Host
Host
Application
UVC/
Custom
Driver
USB
Host
Controller
GPIO
Fixed
Function
GPIF II
I2C
Master
UIB
CX3
DMA
Channel
USB
Bulk
IN EP
USB
EP0
Video
Data
Data
3
24
6
Firmware
5
Data
Lanes
Clock
Lane
Other I/O
Sensor-
Specific I/O
1
The main sub-blocks of the block diagram are numbered, and the tasks executed by each sub-block are
described below:
1. The MIPI CSI-2-based image sensor connects to CX3 and is configured using the Camera Control
Interface (I2C) bus.
2. The CX3 MIPI CSI-2 receiver block reads the data from the image sensor, de-serializes it, merges lanes,
de-packetizes it, and then sends it as a parallel input to the fixed function GPIF II block.
3. The GPIF II block and its fixed-function state machine make the image sensor data available to the USB
interface using a DMA channel.
4. The DMA channel moves the image data from the GPIF II block to the USB Interface Block (UIB).
5. The CX3 firmware initializes the CX3 hardware blocks, configures the image sensor and MIPI CSI-2
controller, controls the USB interface, and services all USB protocol requests. The CX3 firmware can be
customized to add class-specific headers to the video stream data before it is committed to the USB
interface.
6. A host application such as an image signal processor or a video stream player provides control requests
to configure the video stream and sensor, and processes and renders the video stream on the host PC.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 7
1.4 MIPI CSI-2 Block Configuration APIs
The MIPI CSI-2 Rx-block configuration APIs allow user applications to initialize, configure, and perform power
management for the camera interface. These APIs communicate with the camera over the I2C bus.
For modularity, the MIPI CSI-2 configuration APIs are compiled into a separate API library (cyu3mipicsi.a).
This library is linked with the application only if its functionality is required.
The main APIs provided in the API library are as follows:
Table 2: CX3-Specific APIs in the EZ-USB FX3 SDK
API Name
API Description
CyU3PMipicsiInit()
API to initialize the MIPI CSI-2 block.
CyU3PMipicsiDeInit()
API to de-initialize the MIPI CSI-2 block.
CyU3PMipicsiSetIntfParams()
API to configure the clocks and interface settings on the MIPI CSI-2
block.
CyU3PMipicsiQueryIntfParams()
API to query settings from the MIPI CSI-2 block.
CyU3PMipicsiSleep()
API to place the MIPI CSI-2 block in the low-power sleep mode.
CyU3PMipicsiWakeup()
API to wake the MIPI CSI-2 block from the low-power sleep mode to
active mode.
CyU3PCx3DeviceReset()
API to reset the MIPI CSI-2 block.
CyU3PCx3DeviceReset()
API to perform a warm or cold reset on the CX3 device.
CyU3PMipicsiSetSensorControl()
API to drive the MIPI CSI-2 XRESET and XSHUTDOWN signals to the
image sensor.
XRESET is a CX3 output signal that can be used to reset the image
sensor.
XSHUTDOWN is a CX3 output signal that can be used to control
image sensor power modes.
CyU3PMipicsiGpifLoad()
API to load the fixed-function GPIF II waveform and configure the
fixed-function GPIF II bus widths and DMA buffer size.
More information on the APIs is available in Section 1.11
Detailed API documentation is available in the MIPI CSI-2 and Fixed-Function GPIF Interface for CX3 section
of the EZ-USB FX3 SDK Firmware API Guide, available as part of the EZ USB FX3 SDK.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 8
1.5 MIPI CSI-2 Block
The CX3 device has an integrated MIPI CSI-2 block, which is hard-wired to the GPIF II interface on one side
and provides a MIPI CSI-2 interface on the other side to interface to an image sensor that supports MIPI CSI-
2. The block supports up to four MIPI CSI-2 data lanes, and is capable of speeds up to 1 Gbps per lane. The
MIPI CSI-2 receiver is connected to a fixed-function GPIF II controller via an 8-, 16-, or 24-bit data bus, which
can be clocked up to100 MHz. The maximum bandwidth thatcan be achieved is 2.4Gbps (i.e. 24 * 100 Mbps).
The MIPI CSI-2 block is configured over I2C and is available on the CX3 I2C bus at the 7-bit I2C slave address
7’b0000111.
Figure 5. CX3 MIPI CSI-2 Block
I2C
Fixed-Function
GPIF II
MIPI CSI-2
Block
8/16/24-Bit
Interface
I2C_SDA
I2C_SCL
1/2/3/4 Lane
MIPI CSI-2
Input
I2C Address
7’b0000111
XRESET
MCLK
XSHUTDOWN
REFCLK
MIPI CSI-2
Receiver
Parallel
Output

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 9
1.6 CX3 MIPI CSI-2 Stream Formats
The MIPI CSI-2 Rx block on CX3 natively supports the following stream formats and output modes:
Table 3: CX3 MIPI CSI-2 Stream Formats
Format and
Mode
CX3 Firmware Stream Format
Name
Format
Description,
Pixel Depth
CSI-2
Data
Typea
GPIF II
Bus Width
Output Stream
RAW8
CY_U3P_CSI_DF_RAW8
RAW format,
8 bits per pixel
0x2A
8-bit
RAW [7:0]
RAW10
CY_U3P_CSI_DF_RAW10
RAW format,
10 bits per
pixel
0x2B
16-bit
6’b0, RAW [9:0]
RAW12
CY_U3P_CSI_DF_RAW12
RAW format,
12 bits per
pixel
0x2C
16-bit
4’b0, RAW [11:0]
RAW14
CY_U3P_CSI_DF_RAW14
RAW format,
14 bits per
pixel
0x2D
16-bit
2'b0,RAW[13:0]
RGB888
CY_U3P_CSI_DF_RGB888
RGB 888
format,
24 bits per
pixel
0x24
24-bit
R[7:0], G[7:0],
B[7:0]
RGB666 Mode 0
CY_U3P_CSI_DF_RGB666_0
RGB 666
format,
24 bits per
pixel
0x23
24-bit
2’b0, R[5:0], 2’b0,
G[5:0], 2’b0,
B[5:0]
RGB666 Mode 1
CY_U3P_CSI_DF_RGB666_1
RGB 666
format,
24 bits per
pixel
0x23
24 bit
6’b0, R[5:0],
G[5:0], B[5:0]
RGB565 Mode 0
CY_U3P_CSI_DF_RGB565_0
RGB 565
format,
24 bits per
pixel
0x22
24-bit
2’b0, R[4:0],
3’b0, G[5:0],
2’b0, B[4:0], 1’b0
RGB565 Mode 1
CY_U3P_CSI_DF_RGB565_1
RGB 565
format,
24 bits per
pixel
0x22
24-bit
3’b0, R[4:0],
2’b0, G[5:0],
3’b0,B[4:0]
RGB565 Mode 2
CY_U3P_CSI_DF_RGB565_2
RGB 565
format,
16 bits per
pixel
0x22
16-bit
R[4:0], G[5:0],
B[4:0]
YUV422
8-bit Mode 0
CY_U3P_CSI_DF_YUV422_8_0
YUV422 format
16 bits per
pixel
0x1E
8-bit
P[7:0]
Data Order:
U1,Y1,V1,Y2,U3,
Y3,..
a
MIPI CSI-2 defined Data Type code. Please refer to the MIPI CSI-2 specification for details.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 10
Format and
Mode
CX3 Firmware Stream Format
Name
Format
Description,
Pixel Depth
CSI-2
Data
Typea
GPIF II
Bus Width
Output Stream
YUV422
8-bit Mode 1
CY_U3P_CSI_DF_YUV422_8_1
YUV422 format
16 bits per
pixel
0x1E
16-bit
P[15:0]
Data Order:
{U1,Y1},{V1,Y2},{
U3, Y3},{V3,Y4}...
YUV422
8-bit Mode 2
CY_U3P_CSI_DF_YUV422_8_2
YUV422 format
16 bits per
pixel
0x1E
16-bit
P[15:0]
Data Order:
{Y1,U1},{Y2,V1},{
Y3,
U3},{Y4,V3}....
YUV422
10-bit
CY_U3P_CSI_DF_YUV422_10
YUV422 format
20 bits per
pixel
0x1F
16-bit
6'b0,P[9:0]
Data Order:
U1,Y1,V1,Y2,U3,
Y3, V3,Y4.
a
MIPI CSI-2 defined Data Type code. Please refer to the MIPI CSI-2 specification for details.
If the GPIF II bus width selected is larger than the width of the output stream, for example if a 24-bit GPIF II
bus width is used for the CY_U3P_CSI_DF_YUV422_8_1 type, the upper bits on the GPIF II are padded with
0s.
For stream formats not listed in Table 3, such as MJPEG or custom format streams, 8 bit wide streams can
be transported on the RAW8 stream format, and 24 bit wide streams can be transported by treating the stream
as an RGB888 format stream. GPIF bus widths and buffers should be set up appropriately to match the stream
output. Section 1.11.12 has more details on setting up the GPIF bus-width and DMA buffers.
Packing more than one pixel per PCLK is possible. For example, selecting the “MIPI CSI input -Data format"
configured as "RAW8" and the “MIPI interface configuration –data format” as a 24bit format (RGB888) will
output three pixel data per PCLK. Similarly, two 10 bit or 12bit pixels can be packed and output per PCLK
using the 24 bit output format.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 11
1.7 MIPI CSI-2 Block Clocks
Figure 6 shows the CX3 clocks on the MIPI CSI-2 block. The interface takes a reference clock as its input and
generates the required clocking using a PLL followed by multiple clock dividers. In the CX3 application
firmware, clock configuration parameters are a part of the CyU3PMipicsiCfg_t structure, which is passed to
the CyU3PMipicsiSetIntfParams() API to configure the CSI-2 block. Details of the structure and configuration
API can be found in the EZ-USB FX3 SDK Firmware API Guide.
Figure 6. CX3 MIPI CSI-2 Block Clocks
CSI RX LP óHS CLK Divider
Parallel Output Clock (PCLK)
Divider (2/4/8)
MCLKCTL Divider
(MCLK_LOW + MCLK_HIGH)
MCLK
Divider
(2/4/8)
PLL PLL_CLK
CSI RX LP óHS CLK
PCLK
MCLK
REFCLK
A brief description of each of the clocks is provided in the following sections.
1.7.1 Reference Clock (REFCLK)
This is the reference clock input provided to the MIPI CSI-2 block. This input clock should be between 6 and
40 MHz.
1.7.2 PLL Clock (PLL_CLK)
The PLL_CLK is the primary clock of the MIPI CSI-2 block. The value for PLL clock should be between
62.5 MHz and 1 GHz. All other internal and output clocks are derived from this clock.
The PLL clock frequency is generated from the input reference clock using the following equation:
PLL_CLK = REFCLK * [(PLL_FBD + 1) / (PLL_PRD + 1) ] / (2^ PLL_FRS)
Where
PLL_FBD is the feedback divider whose range is between 0 and 0x1FF.
PLL_PRD is the input divider whose range is between 0 and 0x0F.
PLL_FRS is the frequency range selection parameter that takes the following values:
‘0’ if the PLL clock is between 500 MHz and 1 GHz.
‘1’ if the PLL clock is between 250 MHz and 500 MHz.
‘2’ if the PLL clock is between 125 MHz and 250 MHz.
‘3’ if the PLL clock is between 62.5 MHz and 125 MHz.
Sample computations for the PLL clock frequency are provided for a REFCLK value of 19.2 MHz in the
following table:

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 12
Table 4: PLL Clock Frequency Calculation example
REFCLK in MHz
PLL_PRD
PLL_FBD
PLL_FRS
PLL_CLK in MHz
19.2
1
69
0
672
19.2
1
69
2
168
19.2
3
201
1
484.8
19.2
2
97
3
78.4
19.2
2
125
1
403.2
1.7.3 CSI RX LP  HS Clock
This clock is used for detecting the CSI Link Low Power (LP)  High Speed (HS) transition. It is generated
by dividing the PLL_CLK by a value of 2, 4, or 8. Details regarding the CSI Link LP  HS transitions can
be found in the MIPI CSI-2 specification documentation available from the MIPI alliance
(http://www.mipi.org/specifications/camera-interface).
The maximum value for this clock is 125 MHz.
This clock frequency is calculated automatically by the “MIPI Receiver configuration tool”.
1.7.4 Output Parallel Clock (PCLK)
This clock is the PCLK output, which drives the fixed-function GPIF II interface on CX3. It is generated by
dividing the PLL_CLK by a value of 2, 4, or 8.
The maximum value for this clock is 100 MHz.
This clock frequency is calculated automatically by the “MIPI Receiver configuration tool”.
1.7.5 Image Sensor Reference Clock (MCLK)
The MCLK is an optional clock output that can be used as the input reference clock for the image sensor. It is
sourced from the PLL_CLK by first dividing down using the mClkRefDiv (2/4/8) and then dividing further using
the MCLKCTL divider. The MCLKCTL divider specifies the HIGH time and LOW time counted by the divided
down PLL_CLK.
The upper eight bits define the HIGH time count (1-255) and the lower eight bits define the LOW time count
(1-255).
MCLK is computed using the following equation:
MCLK = ( PLL_CLK/mClkRefDiv ) / [ ( HighByte (mClkCtl) + 1 ) + ( LowByte (mClkCtl) + 1 ) ]
For example:
If the PLL_CLK is 672 MHz, to generate MCLK of 24 MHz, set mClkRefDiv to 4 and mClkCtl to 0x0203.
Thus:
MCLK = ( 672 / 4 ) / ( (2 + 1) + ( 3 + 1 ) )
= 168 / 7 = 24 MHz
MCLK is the only output when both HighByte ( MClkCtl ) and LowByte ( MclkCtl ) are non-zero.
This clock frequency is calculated automatically by the “MIPI Receiver configuration tool”.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 13
1.8 CX3 MIPI CSI-2 Block Power Modes
The MIPI CSI-2 block on CX3 supports the following power modes:
▪Active: In this mode, the MIPI CSI-2 receiver block will be active and transfer data from the image
sensor to the GPIF II interface.
▪Low-Power Sleep: In this mode, all data transfer clocks on the MIPI CSI-2 block are stopped and there
will be no data transfer. All register settings are retained in this state.
▪Soft Reset: This state puts the MIPI CSI-2 block into reset mode where all clocks on the interface are
stopped. The MIPI CSI-2 block configuration register states are retained across a soft reset.
▪Hard Reset: In this state the MIPI CSI-2 controller and all clocks are stopped. The MIPI CSI-2 block
configuration registers are reset to their default states by a hard reset. Hard reset is automatically
executed during MIPI CSI-2 receiver initialization.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 14
1.9 Fixed-Function GPIF II Interface on CX3
The fixed-function GPIF II state machine of CX3 is shown in Figure 7. This state machine makes the parallel
data provided by the MIPI CSI-2 receiver available for transfer over two sockets, which can be connected to
a manual, Many-to-One DMA channel.
The functionality of this state machine is similar to the GPIF II state machine described in Application Note
AN75779 - How to Implement an Image Sensor Interface with EZ-USB® FX3™ in a USB Video Class (UVC)
Framework.
Figure 7. CX3 GPIFII State Machine
Start Wait for
Frame Done
Wait for
Frame valid,
Load DATA
Transfer
thread 0 data
DATA++
ADDR=0
Transfer
thread 1 data,
ADDR++
DATA=0
Wait for LV
with thread 0
active
Wait for LV
with thread 1
active
Wait for LV
with thread 0
full
Wait for LV
with thread 1
full
Frame end
full buffer in
thread 0
Intr CPU
Frame end
full buffer in
thread 1
Intr CPU
Frame end
partial buffer
in thread 0
Intr CPU
Frame end
partial buffer
in thread 1
Intr CPU
!FV
FV & LV
LV & DATA Limit
LV & ADDR Limit
!LV & !DATA Limit !LV& !ADDR Limit
LV LV
LVLV
!LV & DATA Limit !LV &ADDR Limit
!FV !FV !FV !FV
State 0 State 1 State 2
State 3 State 4State 5 State 6
State 7 State 8
State 9 State 12State 11 State 10
Start
Wait for
Frame Done
Wait for
Frame valid,
Load DATA
State 13
State 14
State 15
FV & LV
Frame end
Wait for
Firmware
Trigger
Frame end
Wait for
Firmware
Trigger
FW_TRIG FW_TRIG
FW_TRIG
!FW_TRIG & DATA on thread 1
FW_TRIG
!FW_TRIG & DATA on thread 0
!FV
The FX3 SDK (Software Development Kit) provides the CyU3PMipicsiGpifLoad() API to loadthis fixed-function
state machine into the CX3 GPIF II block. This API allows selection of the bus width (8, 16, or 24 bits) to match
the output from the parallel interface on the MIPI CSI-2 block, and also allows setting of the DMA buffer size
to be used for the GPIF II interface. The buffer size calculation is explained in CyU3PMipicsiGpifLoad() API
documentation in section 1.11.12

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 15
1.10 MIPI CSI-2 Block Registers
The MIPI CSI-2 block exposes a set of registers used to configure the block over I2C. The block is available
at the 7-bit I2C slave address 7'b0000111 (Read address 0x0F; Write address 0x0E). The block supports 100
kHz and 400 kHz I2C operation.
Note: No other I2C device with the same address as the MIPI CSI-2 block should be connected to the I2C bus
of the CX3 device.
The registers are 16-bit aligned, and data transfers are performed Most Significant Bit (MSB) first.
Figure 8 and Figure 9 show typical I2C Read and Write transfers to the MIPI CSI-2 block.
Figure 8. Write Transfer Sequence
SSLAVE ADDRESS
7 bit (0000_111)0 A REG_ADDR_VAL [15:8] AREG_ADDR_VAL [7:0] A DATA[15:8] A DATA[7:0] A P
Figure 9. Read Transfer Sequence
Table 5 provides a list of the configuration registers included in the CX3 MIPI CSI-2 block.
Table 5: MIPI CSI-2 Block Configuration Registers
Register
Address
Register Name
Description
0x0002
CX3_SYSTEM_CTRL
System Control Register
0x0004
CX3_CONFIG_CTRL
Configuration Control Register
0x0006
CX3_FIFO_CTRL
FIFO Control register
0x0008
CX3_DATA_FMT
Data Format Control Register
0x000C
CX3_MCLK_CTRL
MCLK Control Register
0x0010
CX3_CSI_ SENSOR_SIG_EN
Register to Enable MIPI CSI-2 signals (XRESET and
XSHUTDOWN)
0X0014
CX3_CSI_SENSOR_SIG_VAL
Register to Control MIPI CSI-2 signals (XRESET and
XSHUTDOWN)
0x0016
CX3_PLL_CTRL0
PLL Clock Control Register 0
0x0018
CX3_PLL_CTRL1
PLL Clock Control Register 1
0x0020
CX3_CLK_CTRL
Clock Control Register
0x0022
CX3_BYTE_COUNT
Byte Count Register
0x0060
CX3_PHY_TIME_DELAY
Register to set MIPI THS-Settle timer settings.
The following sections provide detailed descriptions of each of the CX3 MIPI CSI-2 configuration registers.
Note: RESERVED Register Bits should not be changed. When writing to a register with RESERVED bits, you
should ensure that the values are not changed during a Write (preferably by doing a Read before the Write
and maintaining the values for the RESERVED bits during the Write).
SSLAVE ADDRESS
7 bit (0000_111)1 A DATA[15:8] A DATA[7:0] A PS SLAVE ADDRESS 7 bit (0000_111)0 A REG_ADDR_VAL [15:8] AREG_ADDR_VAL [7:0] A

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 16
1.10.1 CX3_SYSTEM_CTRL (Register Address: 0x0002)
This register controls the Sleep and Software Reset functionality for the MIPI CSI-2 block.
This register is used by the CyU3PMipicsiSleep(), CyU3PMipicsiWakeup(),and CyU3PMipicsiReset() APIs.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
BIT
7
6
5
4
3
2
1
0
NAME
RESERVED
SLEEP
RESET
Register Field
Bit
Description
RESERVED
[15:2]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
SLEEP
[1]
Sleep Control:
Places the MIPI CSI-2 block into low-power sleep mode.
0: Normal Operation
1: Sleep Mode
RESET
[0]
Software Reset:
Forces software reset of the MIPI CSI-2 block. Does not clear the
configuration registers.
0: Normal Operation
1: Reset Operation

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 17
1.10.2 CX3_CONFIG_CTRL (Register Address: 0x0004)
This register controls number of data lanes and the output data mode for the MIPI CSI-2 block.
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
DATA MODE
BIT
7
6
5
4
3
2
1
0
NAME
RESERVED
OUTEN
RESERVED
DATA LANES
Register Field
Bit
Description
RESERVED
[15:10]
RESERVED. Firmware must preserve their settings by reading them, changing
non-reserved bits, and re-writing them.
DATA MODE
[9:8]
Data Mode Selection:
Sets the data mode for the data format selected using the DATA FORMAT bits
of the CX3_DATA_FMT register. The combination of DATA MODE and the
DATA FORMAT is used to select the output stream as defined in Table 3. The
DATA FORMAT setting determines the output data format, while the DATA
MODE setting determines the data packing and byte ordering for the
DATA TYPE as defined in Table 3.
2’b00: Mode 0
2’b01: Mode 1
2’b10: Mode 2
2’b11: Reserved
RESERVED
[7]
RESERVED. Firmware must preserve their settings by reading them, changing
non-reserved bits, and re-writing them.
OUTEN
[6]
Enable Parallel Output:
Enables parallel output from MIPI CSI-2 receiver block to fixed-function GPIF II.
0: Disable Parallel Output.
1: Enable Parallel Output
RESERVED
[5:2]
RESERVED. Firmware must preserve their settings by reading them, changing
non-reserved bits, and re-writing them.
DATA LANES
[1:0]
MIPI CSI-2 Data Lane Selection:
Selects the number of data lanes to be used.
2’b00: 1 Data Lane
2’b01: 2 Data Lanes
2’b10: 3 Data Lanes
2’b11: 4 Data Lanes

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 18
1.10.3 CX3_FIFO_CTRL (Register Address: 0x0006)
This register determines the FIFO trigger level for the initiation of parallel data output from the parallel output
buffer of the MIPI CSI-2 block. The MIPI CSI-2 block waits for the parallel output buffer to reach the level
specified by this register before transferring data to GPIF II interface.
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
FIFO LEVEL[8]
BIT
7
6
5
4
3
2
1
0
NAME
FIFO LEVEL [7:0]
Register Field
Bit
Description
RESERVED
[15:9]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
FIFO LEVEL
[8:0]
FIFO Level:
Determines the FIFO Write trigger level. The MIPI CSI-2 block starts parallel
output to the GPIF II only when the output buffer reaches this level.
Range: 0x000-0x1FF

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 19
1.10.4 CX3_DATA_FMT (Register Address: 0x0008)
This register controls the output data format for the MIPI CSI-2 block.
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
BIT
7
6
5
4
3
2
1
0
NAME
DATA FORMAT
RESERVED
DATA FMT ENABLE
Register Field
Bit
Description
RESERVED
[15:8]
RESERVED. Firmware must preserve their settings by reading them, changing
non-reserved bits, and re-writing them.
DATA FORMAT
[7:4]
Data Format Selection:
Selects the output data format.
4’b0000: RAW8
4’b0001: RAW10
4’b0010: RAW12
4’b0011: RGB888
4’b0100: RGB666
4’b0101: RGB565
4’b0110: YUV422-8-bit
4’b0111: RESERVED
4’b1000: RAW14
4’b1001: YUV422-10-bit
4’b1010-1111: RESERVED
This field, along with the DATA MODE field from the CX3_CONFIG_CTRL
register, is used to select the output stream format defined in Table 3.
For stream formats not listed in Table 3, such as MJPEG or custom format
streams, 8 bit wide streams can be transported on the RAW8 stream format,
and 24 bit wide streams can be transported by treating the stream as an
RGB888 format stream.
RESERVED
[3:1]
RESERVED. Firmware must preserve their settings by reading them, changing
non-reserved bits, and re-writing them.
DATA FMT ENABLE
[0]
Data Format Enable:
0: Not supported.
1: Normal operation.

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 20
1.10.5 CX3_MCLK_CTRL (Register Address: 0x000C)
This register configures the MCLK divider and controls the Image Sensor Reference Clock (MCLK) output
from the MIPI CSI-2 block. Detailed information on calculating the MCLK value is provided in Section 1.7.5 .
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
MCLK HIGH
BIT
7
6
5
4
3
2
1
0
NAME
MCLK LOW
Register field
Bit
Description
MCLK HIGH
[15:8]
MCLK HIGH Time Count:
HIGH time count for the MCLK divider. See Section 1.7.5 for details on this
field.
MCLK is enabled only if MCLK HIGH and MCLK LOW are non-zero.
MCLK LOW
[7:0]
MCLK LOW Time Count:
LOW Time count for MCLK divider. See Section 1.7.5 for details on this
field.
MCLK Divider = (MCLK HIGH +1) + (MCLK LOW+1)