Denon Avr-5805-upgrade User manual

SERVICE MANUAL

TOKYO, JAPAN

Denon Brand Company, D&M Holdings Inc.

Some illustrations using in this service manual are

slightly different from the actual set.

●

Please use this service manual with referring to the

operating instructions without fail.

●

For purposes of improvement, specifications and

design are subject to change without notice.

●

本文中に使用しているイラストは、説明の都合上現物

と多少異なる場合があります。

●

修理の際は、必ず取扱説明書を参照の上、作業を行っ

てください。

サービスをおこなう前に、このサービスマニュアルを

必ずお読みください。本機は、火災、感電、けがなど

に対する安全性を確保するために、さまざまな配慮を

おこなっており、また法的には「電気用品安全法」に

もとづき、所定の許可を得て製造されております。

従ってサービスをおこなう際は、これらの安全性が維

持されるよう、このサービスマニュアルに記載されて

いる注意事項を必ずお守りください。

●

本機の仕様は性能改良のため、予告なく変更すること

があります。

●

補修用性能部品の保有期間は、製造打切後8年です。

注意

For U.S.A. & Canada,

Europe, Taiwan R.O.C.,

China, & Japan model

X0278 V.01 DE/CDM 0604

AV SURROUND RECEIVER

MODEL AVR-5805-

UPGRADE

AV SURROUND AMPLIFIER

UPGRADE KIT SPK-553 (For U.S.A. & Canada model)

UPGRADE KIT SPK-556 (For Japan model)

UPGRADE KIT SPK-555 (For Europe, China & Taiwan R.O.C. model)

MODEL AVC-A1XV-

UPGRADE

This service manual is composed of only pages whose

contents are different from those for the model AVR-5805,

AVC-A1XV.

For servicing, refer to the previously issued service manual

of

AVR-5805, AVC-A1XV

at the same time.

本書の内容は、既発行のサービスマニュアルAVR‑5805、

AVC‑A1XVとの相違部分のみ記載しています。

サービスの際はサービスマニュアル

AVR‑5805,

AVC‑A1XV

と本書をご用意願います。

Ver. 1

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AVR-5805/AVC-A1XV-UPGRADE

Page 4

WIRE ARRANGEMENT

Wire arrangement viewed from the top

ワイヤー整形図

上面からみたワイヤー整形

Front Panel side

Back Panel side

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3

AVR-5805/AVC-A1XV-UPGRADE

Dock Control

Connector

XM Supply

The other

unit

XM RADIO

IC251

(PLD)

EPM570T144C5N

SIGNAL DET.

INPUT

SELECTOR

SYNC. DET.

OSD

SIGNAL DET.

OSD BLOCK

INPUT

SELECTOR

CVBS OUT

S(Y/C) OUT

COMPONENT OUT

D CONTROL OUT

(

JAPAN ONLY

)

S MONI.DET.

CVBS IN

S(Y/C) IN

COMPONENT IN

D CONTROL IN

(JAPAN ONLY)

ANALOG VIDEO

VIDEO BLOCK DIAGRAM

6dB

0dB

INPUT:2Vpp

INPUT

SELECTOR

75

LOAD

75

LOAD

75

LOAD

75

LOAD

75

LOAD

75

LOAD

-6dB

70℃

75℃

DC

GENERATOR

fc:0.016Hz

fc:0.16Hz

fc:0.15Hz

fc:0.16Hz

fc:0.016Hz

1U-3755-1

DIGITAL VIDEO UNIT

HDMI

0dB

IC353

TRANSMITTER

SiI9030

SD

ITU-R. BT656 10bit

PS/HD

YCBCR4:2:2 20bit

/

RGB 24bit

SIGNAL DET.

INPUT

SELECTOR

SYNC. DET.

OSD

SIGNAL DET.

OSD BLOCK

INPUT

SELECTOR

CVBS OUT

S(Y/C) OUT

COMPONENT OUT

S MONI.DET.

ZONE 2

-6dB

A

TT

-6dB

A

TT

6dB

0dB

INPUT:1Vpp

INPUT:2Vpp

INPUT

SELECTOR

70℃

75℃

0dB

FILTER

6dB

-12dB

0dB

FILTER

6dB

-6dB

0dB

FILTER

6dB

GAIN ADJ.:11.3dB typ.

PAL

1H DELAY

TA8772AN

0dB

VIDEO CONVERT BLOCK

-6dB

CROMA

DECODER

TA1270BF

GAIN ADJ.:11.3dB typ.

Y/C

SEPARATOR

TC90A69F

Y/C MIXER

NJM2274R

INPUT:1Vpp

-6dB

A

TT

-6dB

A

TT

12dB

INPUT:0.5Vpp

75℃

65℃

85℃

65℃

INPUT

SELECTOR

6dB

INPUT

SELECTOR

CVBS OUT

S(Y/C) OUT

RECOUT

INHIBIT

RECOUT

INHIBIT

0dB

ZONE 3

fc:0.16Hz

fc:0.15Hz

fc:0.16Hz

fc:0.72Hz

㪽㪺㪑㪇㪅㪎㪉㪟㫑

fc:1.59Hz

fc:0.16Hz

ZONE 1

DVI-D

IC303

TRANSMITTER

SiI9030

SD

ITU-R. BT656 10bit

PS/HD

YCBCR4:2:2 20bit

/RGB 24bit

PS/HD

YCBCR4:2:2 20bit

/RGB 24bit

YCBCR4:2:2 20bit

/RGB 24bit

ZONE2/ZONE3 is equal with AVR5805

HDMI

DVI

HDMI

IC203

RECEIVER

SiI9033

DAC D

DAC E

DAC F

DAC E

DAC F

IC605

FORMAT

DETECTOR

TE8201PF

VIDEO CONVERT BLOCK

IC755

VIDEO

DRIVER

WITH FILTER

BH7868F

INPUT:1Vpp

6dB

INPUT:1Vpp

70℃

fc:0.16Hz

fc:159Hz

fc:0.16Hz

fc:79.6Hz

INPUT:1Vpp

64M SDRAM

IC703

VIDEO

ENCODER

ADV7320

70℃

IC501

VIDEO

PROCESSOR

FLI2310

70℃

IC753

VIDEO

ENCODER

ADV7320

IC606

VIDEO

DECODER

ADV7403

70℃

IC705

VIDEO

DRIVER WITH

FILTER

FMS6403

70℃

INPUT:1Vpp

6dB

SD

ITU-R. BT656 10bit

PS/HD

YCBCR4:2:2 20bit

/RGB 24bit

OPTION

CONNECTOR

PS/HD

YCBCR

4:2:2 20bit

PS/HD

YCBCR4:2:2 20bit

/RGB 24bit

PORT2:

SD

ITU-R. BT656 10bit

PORT1:

PS/HD

YCBCR4:2:2 20bit

SD

ONLY

ITU-R.

BT656

10bit

-6dB

A

TT

-6dB

A

TT

-6dB

A

TT

-6dB

A

TT

-6dB

A

TT

-6dB

A

TT

0dB

BIAS

CLAMP

0dB

FONT ROM

New

OSD

INPUT:2Vpp, OUTPUT:2Vpp

IC802

VIDEO CPU

M30835FJGP

OPTION

IC401

FPGA

EP1C4F400C8N

LVDS

To

Digital

Audio

Block

IC451

Audio signal

selector

EPM570T144C5N

IC153

RECEIVER

SiI9033

IC103

RECEIVER

SiI9033

IC457

DSD-PCM

CONVERTER

SM5819A

70℃

S(Y/C) RECOUT

CVBS RECOUT

TheoutputMUTEofthe

CONPONENT uses the

function of the CPAMP

TheoutputMUTEofthe

CONPONENT uses the

function of the CPAMP

Page 27, 28

BLOCK DIAGRAMS

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4

AVR-5805/AVC-A1XV-UPGRADE

Page 32~34

ADJUSTMENT

VIDEO Section

I. MAIN ZONE

1. SETTING

(1) Connect the oscilloscope to the Y-signal and C-signal of

S MONITOR OUT terminal and each terminate at 75

Ohms.

(2) Connect the oscilloscope to the Y-signal, PB-signal and

CB-signal, PR-signal and CR-signal of COMPONENT

MONITOR OUT2 terminal and each terminate at 75

Ohms.

※Use the 75 Ohms resistance must be 1%

(3) DVD test disc : DVDT-S01

(4) COMPONENT VIDEO OUT of DVD player is connected

to COMPONENT IN-5.

2. BEFORE ADJUSTMENT

2.1. Setting the Oscilloscope as below.

(1) PB/CB, PR/CR, C

(a) TIME/DIV : 10μs

(b) VOLT/DIV : 100mV

(Use the probe : x10 )

(2) Y

(a) TIME/DIV : 10μs

(b) VOLT/DIV : 200mV

(Use the probe : x10 )

Power on. Power Supply

U.S.A. & Canada : 120V

Taiwan R.O.C. : 120V

Europe : 230V

Japan : 100V

China & Korea : 220V

2.2. Setup the DVD player and confirmation of the

stators

(1) Set to "INTERLACED" mode at the COMPONENT OUT.

(2) Confirm the DVD player’s out put level is equal as the

item 2.4. in following.

2.3. Preparation

(1) Push [POWER] button with pressing [GAME] and [SUR-

ROUND BACK] buttons.

(2) Confirm "0.0dB" appearing on the FL display.

(3) Turn the FUNCTION knob to select "VCR-1" input.

(4) Push [VIDEO ON/OFF] button twice to select "VIDEO

OFF". (It becomes Adjustment mode.)

(5) Push [OPEN/CLOSE] button of DVD player, then open

the Disc Tray.

Set DVD test disc (DVDT-S01) on the Disc Tray, and

then push [CLOSE] button.

(6) DVD player FL display appear "STOP", push [PLAY] but-

ton to playback DVD.

(7) Push the [DISPLAY] button of remote control of DVD

player unit and then appear the ON-Screen Display (GUI)

on the monitor TV.

(8) Push the [+10] and [2] button, select Title 12 of DVD.

(9) Push the [ENTER] button, playback Title 12.

(color bar 75%)

調整

ビデオセクション

I.MAINZONE

1. セッティング手順

(1) セットの SMONITOROUT 端子から Y 信号と C 信号を

それぞれオシロスコープ（終端抵抗：75Ω）に接続し

ます。

(2) セットの COMPONENTMONITOROUT2 の端子（Y,

PB/CB,PR/CR）をそれぞれオシロスコープ（終端抵抗：

75Ω）に接続します。

※ 75Ω 抵抗は 1％品を使用する事。

(3) DVD テストディスク：DVDT-S01 を用意します。

(4) DVD プレーヤーの COMPONENTVIDEOOUT を

COMPONENTIN-5 に接続します。

2. 調整のまえに

2.1. オシロスコープを下記に設定

(1) PB/CB,PR/CR,C

(a) TIME/DIV : 10μs

(b) VOLT/DIV : 100mV

（プローブ x10 使用）

(2) Y

(a) TIME/DIV : 10μs

(b) VOLT/DIV : 200mV

（プローブ x10 使用）

電源電圧： 100V

2.2. DVD プレーヤの設定と確認

(1) COMPONENTOUT の設定を " インターレース " にしま

す。

(2) DVD プレーヤーの出力が以下 2.4. に合っていることを

確認します。

2.3. 準備手順

(1) セットの AC コードをコンセントへ挿入し、「GAME」

と「SURROUNDBACK」ボタンを押しながらセットの電

源を "ON" にします。

(2) FL 表示右上の VOL 表示が "0.0dB" になっていることを

確認します。

(3) FUNCTION ノブを回し、入力を "VCR-1" に切り替えます。

(4) 「VIDEOON/OFF」ボタンを 2 回押し、"VIDEOOFF" に

します。（調整モードになります）

(5) DVD プレーヤーの「OPEN/CLOSE」ボタンを押しトレ

イを開き、トレイ上に DVD テストディスク（DVDT-

S01）をセット後、「CLOSE」ボタンを押します。

(6) DVD プレーヤーの表示管上に "STOP" が表示されてか

ら、「PLAY」ボタンを押し、ディスクを再生します。

(7) DVD プレーヤーのリモコンの「DISPLAY」ボタンを押

しグラフィカル・ユーザー・インターフェイス (GUI) 画

面を出します。

(8) 番号ボタンの｢ +10 ｣ , ｢ 2 ｣ボタンを押し、Title12 を選択

します。

(9) 「ENTER」ボタンを押し、Title12 を再生します。

（75％カラーバー信号）

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AVR-5805/AVC-A1XV-UPGRADE

2.4. Procedure

(1) Adjust the signal of S MONITOR OUT by the wave of os-

cilloscope.

(a) Target, Y-signal

Point : 1U-3755-1 VR751

Adjustment Value : 714 ±14mV

Waveform

(b) Target, C-signal

Point : 1U-3755-1 VR752

Adjustment Value : 286 ±5mV

Waveform

(2) Adjust the signal of COMPONENT OUT by the wave of

oscilloscope.

(a) Target, Y-signal

Point : 1U-3755-1 VR701

Adjustment Value : 714 ±14mV

Waveform

(b) Target, PB/CB-signal

Point : 1U-3755-1 VR702

Adjustment Value : *525 ±10mV

Waveform

Y-signal of S MONITOR OUT

Y

C

C-signal of S-MONITOR

Y

Y-signal COMPONENT OUT

PB/CB-signal COMPONENT OUT

PB/CB

2.4. 手順

(1) セットの SMONITOROUT の信号レベルをオシロスコー

プ上の波高値で調整します。

(a) Y 信号レベル

調整個所： 1U-3755-1VR751

調整値： 714 ± 14mV

波形

(b) C 信号レベル

調整個所： 1U-3755-1VR752

調整値： 286 ± 5ｍV

波形

(2) COMPONENTOUTの信号レベルをオシロスコープ上の

波高値で調整します。

(a) Y 信号レベル

調整個所： 1U-3755-1VR701

調整値： 714 ± 14ｍV

波形

(b) PB/CB信号レベル

調整個所： 1U-3755-1VR702

調整値： 525 ± 10ｍV

波形

SMONITOROUT の Y 信号レベル

Y

C

SMONITOR の C 信号レベル

Y

COMPONENTOUT の Y 信号レベル

PB/CB

COMPONENTOUT の PB/CB信号レベル

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AVR-5805/AVC-A1XV-UPGRADE

(c) Target, PR/CR-signal

Point : 1U-3755-1 VR703

Adjustment Value : *525 ±10mV

Waveform

* : 486 ±10mV for U.S.A. & Canada model

PR/CR-signal COMPONENT OUT

PR/CR

(c) PR/CR信号レベル

調整個所： 1U-3755-1VR703

調整値： 525 ± 10ｍV

波形

PR/CR

COMPONENTOUT の PR/CR信号レベル

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AVR-5805/AVC-A1XV-UPGRADE

Page 37~74

SEMICONDUCTORS (for 00D1U-3755A D.VIDEO P.W.B.)

Only major semiconductors are shown, general semiconductors etc. are omitted to list.

主な半導体を記載しています。汎用の半導体は記載を省略しています。

IC’s

FLI2310-LF-CF (IC501)

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AVR-5805/AVC-A1XV-UPGRADE

Terminal Function

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AVR-5805/AVC-A1XV-UPGRADE

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AVR-5805/AVC-A1XV-UPGRADE

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AVR-5805/AVC-A1XV-UPGRADE

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AVR-5805/AVC-A1XV-UPGRADE

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AVR-5805/AVC-A1XV-UPGRADE

M30835FJGP (IC802)

M30835FJGP Terminal Function

Pin Pin name Symbol I/O Type Det Op(Int.) Op(Ext.) Res stop Function

1 P96/TXD4 (GIVO) O C - - (-) Z O/L NC(VIDEO-GUI Communication Control terminal)

2 P95/CLK4 (CLK GIVO) O C - - (-) Z O/L NC(VIDEO-GUI Communication Control terminal)

3 P94/CTS4 (REQ GOVI) O C - - (-) Z O/L NC(VIDEO-GUI Communication Control terminal)

4 P93/CTS3 Z1VCONV.B O C - - Ed Z O/L MAIN CVBS Routing control(convert/through)(TC4052)

5 P92/TXD3/SDA3 HDMI SDA I/O C - - - Z O/L HDMI T/R/EDIT(E2PROM)Control terminal

6 P91/RXD3/SCL3 HDMI SCL I/O C - - - Z O/L HDMI T/R/EDIT(E2PROM)Control terminal

7 P90/CLK3 Z1VCONV.A O C - - Ed Z O/L MAIN CVBS Routing control(convert/through)(TC4052)

8 P146 Z1SCONV.B O C - - Ed Z O/L MAIN S Routing control(convert/through)(TC4052)

9 P145 Z1SCONV.A O C - - Ed Z O/L MAIN S Routing control(convert/through)(TC4052)

10 P144 CV/MIX O C - - - Z O/L Y/C MIX selection control(convert/analog MIX )(BH7868)

11 P143 (XM RST) O C - - (-) Z O/L (XM RADIO terminal for control)

12 P142 (XM COMMAND) O C - - (-) Z O/L (XM RADIO terminal for control)

13 P141 (XM POWER) O C - - (-) Z O/L (XM RADIO power on/off switching(ONÅFH))

14 P140 (XMDACMDI) O C - - (-) Z O/L (DAC control terminal for XM(AK4385ET))

15 BYTE BYTE - - - - - - - GND(Ext. data bus bit width switching, 16bit="L")

16 CNVss CNVSS I - - - Ed - - "Single-chip/Micro-processor mode switching (Normal single-chip:L, Rewrite boot

program start:H input set)"

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14

AVR-5805/AVC-A1XV-UPGRADE

17 P87/XCIN (XMDACRST) O C - - (-) Z O/L (DAC control terminal for XM(AK4385ET))

18 P86/XCOUT (XMDACMUTE) O C - - (-) Z O/L (DAC output MUTE control terminal for XM )

19 RESET RESET I - Lv - Eu L I Reset input(Reset:"L")

20 XOUT X2 O - - - - - - Clock output

21 VSS VSS - - - - - - - GND

22 XIN X1 I - - - - - I Clock input

23VCC VCC ---- ---+3.3V

24 P85/NMI _NMI I - - - - - - Not used(Fixed:"H")

25 P84/INT2 (REMOTE) I - E↑&L - Ed Z I Remote control signal input(TEST:usually unused thing)

26 P83/INT1 V.B.DOWN I - E↓&L - Eu Z I Power down detect (Power down: L)

27 P82/INT0 (REQ XM) O C - - (-) Z O/L (XM RADIO terminal for control)

28 P81/ (XMDACCS) O C - - (-) Z O/L (DAC control terminal for XM(AK4385ET))

29 P80/ISRXD0 (RXD MIXMO) O C - - (-) Z O/L (XM RADIO terminal for control)

30 P77/ISCLK0 (XMDACMC) O C - - (-) Z O/L (DAC control terminal for XM(AK4385ET))

31 P76/ISTXD0 (TXD MOXMI) O C - - (-) Z O/L (XM RADIO terminal for control)

32 P75/ISRXD1 (RXD iPod) O C - - (-) Z O/L (IPOD communication control terminal)

33 P74/ISCLK1 (iPOD CON DET) O C - - (-) Z O/L (IPOD detect terminal("L": DETECT)

34 P73/CTS2/ISTXD1 (TXD_iPod) O C - - (-) Z O/L (IPOD communication control terminal)

35 P72/CLK2 CLK VIMO I - Lv - - Z O/L MAIN-VIDEO communication control terminal

36 P71/RXD2/ VIMO I - Lv - Eu Z O/L MAIN-VIDEO communication control terminal

37 P70/TXD2/ VOMI O N - - Eu Z O/L MAIN-VIDEO communication control terminal

38 P67/TXD1 FRONT TxD O C - - - Z O/L Data transfer terminal to outside(MAKER BOOT)

39VCC VCC ---- ---+3.3V

40 P66/RXD1 FRONT RxD I - Lv - - Z O/L Data reception terminal from Ext.(MAKER BOOT)

41 VSS VSS - - - - - - - GND

42 P65/CLK1 REQ VOMI O C - - - Z O/L MAIN-VIDEO communication control terminal

43 P64/CTS1 VSEL0 O C - - - Z O/L BUS SW(FPGA)switching control terminal

44 P63/TXD0 ZONE1 SDA I/O C - - - Z O/L VIDEO I2C control terminal

45 P62/RXD0 ZONE1 SCL I/O C - - - Z O/L VIDEO I2C control terminal

46 P61/CLK0 Z2 VSIG DET I - Lv - Eu Z O/L ZONE2 VIDEO IN signal detect input(signal input:"H")

47 P60/CTS0 Z1 VSIG DET I - Lv - Eu Z O/L MAIN ZONE VIDEO IN signal detect input(signal input:"H")

48 P137 Z1 OSD RST O C - - - Z O/L MAIN OSD control terminal(M35015)

49 P136/ISCLK2 Z1 OSD CLK O C - - - Z O/L MAIN OSD control terminal(M35015)

50 P135/ISRXD2 Z1 OSD STB O C - - - Z O/L MAIN OSD control terminal(M35015)

51 P134/ISTXD2 Z1 OSD DATA O C - - - Z O/L MAIN OSD control terminal(M35015)

52 P57 ZONE2 SDA I/O C - - - Z O/L ZONE2 VIDEO I2C control terminal(TA1270/TC90A69F)

53 P56 ZONE2 SCL I/O C - - - Z O/L ZONE2 VIDEO I2C control terminal(TA1270/TC90A69F)

54 P55/EPM FRASH EPM I - - - Ed Z I Rewrite boot program start: "L" Input setting

55 P54 Z1 SMONIDET I - Lv - Eu Z O/L S MONITER connection detect input for MNAIN ZONE (Connected:"L")

56 P133 Z2 S SIG DET I - Lv - Eu Z O/L MAIN ZONE S signal detect input(Connecte:"H")

57 VSS VSS - - - - - - - GND

58 P132 Z1 S SIG DET I - Lv - Eu Z O/L MAIN ZONE S signal detect input(Connecte:"H")

59VCC VCC ---- ---+3.3V

60 P131 Z2 SMONIDET I - Lv - Eu Z O/L S MONITER connection detect input for ZONE2(Connected:"L")

61 P130 SV EXP OE O C - - Ed Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

62 P53 SV EXP STB O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control

63 P52 SV EXP DATA O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

64 P51 SV EXP CLK O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control

65 P50/CE FRASH CE I - - - Ed Z I Rewrite boot program start:H input set

66 P127 C EXP OE O C - - Ed Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

67 P126 C EXP STB O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

68 P125 C EXP DATA O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

69 P47/CS0/A23 C EXP CLK O C - - - Z O/L Control terminal switching for COMPONENT section, Expander control(BU4094B)

70 P46/CS1/A22 COMP SDET1 I - Lv - Eu Z O/L COMPONENT IN signal detect input for MAIN ZONE

71 P45/CS2/A21 COMP SDET2 I - Lv - Eu Z O/L COMPONENT IN signal detect input for ZONE2

72 P44/CS3/A20 Z2 OSD RST O C - - - Z O/L ZONE2 OSD control terminal(M35015)

73 P43/A19 Z2 OSD STB O C - - - Z O/L ZONE2 OSD control terminal(M35015)

74VCC VCC ---- ---+3.3V

75 P42/A18 Z2 OSD CLK O C - - - Z O/L ZONE2 OSD control terminal(M35015)

76 VSS VSS - - - - - - - GND

77 P41/A17 Z2 OSD DATA O C - - - Z O/L ZONE2 OSD control terminal(M35015)

78 P40/A16 Z2 SYNC DET I - Lv - Eu Z O/L Synchronous detect input for ZONE2(Ext.Synchronous:H)

79 P37/D15 Z1 SYNC DET I - Lv - Eu Z O/L Synchronous detect input for MAIN(Ext.Synchronous:H)

80 P36/D14 OSDOUTSEL O C - - Ed Z O/L MAIN OSD Routing control

81 P35/D13 OSDRST O C - - - Z O/L NEW OSD control terminal(LC74731W)

82 P34/D12 OSDCLK O C - - - Z O/L NEW OSD control terminal(LC74731W)

83 P33/A11 OSDSIN O C - - - Z O/L NEW OSD control terminal(LC74731W)

84 P32/D10 OSDCS O C - - - Z O/L NEW OSD control terminal(LC74731W)

85 P31/D9 OSDMUTE O C - - - Z O/L NEW OSD control terminal(LC74731W)

86 P124 V/Y SEL O C - - Ed Z O/L MAIN NEW OSD control of input signal selection(S/CVBS)(TC4053)

87 P123 Y/C SEL O C - - Ed Z O/L Croma Decoder SELECT for ZONE2

88 P122/ISRXD3 VÇéCONFIG O C - - - Z O/L FPGA rewrite control terminal

89 P121/ISCLK3 V DATAOUT O C - - - Z O/L FPGA rewrite control terminal

90 P120/ISTXD3 V ASDI O C - - - Z O/L FPGA rewrite control terminal

91VCC VCC ---- ---+3.3V

92 P30/D8 VnCS O C - - - Z O/L FPGA rewrite control terminal

93 VSS VSS - - - - - - - GND

Pin Pin name Symbol I/O Type Det Op(Int.) Op(Ext.) Res stop Function

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AVR-5805/AVC-A1XV-UPGRADE

94 P27/AN27/D7 VDCLK O C - - - Z O/L FPGA rewrite control terminal

95 P26/AN26/D6 VCONF_DONE I - Lv - - Z O/L FPGA rewrite control terminal

96 P25/AN25/D5 VCPUASON O C - - - Z O/L Rewrite for FPGAROM ON=L ※Initial setting, V.POWER OFF=H

97 P24/AN24/D4 VnCE O C - - - Z O/L FPGA rewrite control terminal

98 P23/AN23/D3 VSEL5 O C - - - Z O/L BUS SW(FPGA) switching control terminal

99 P22/AN22/D2 VSEL4 O C - - - Z O/L BUS SW(FPGA) switching control terminal

100 P21/AN21/D1 VSEL3 O C - - - Z O/L BUS SW(FPGA) switching control terminal

101 P20/AN20/D0 VSEL2 O C - - - Z O/L BUS SW(FPGA) switching control terminal

102 P17/INT5/D15 VSEL1 O C - - - Z O/L BUS SW(FPGA) switching control terminal

103 P16/INT4/D14 ACK VIMO I - E↑&L - - Z O/L MAIN-VIDEO communication Control terminal

104 P15/INT3/D13 HDMIVS. I - E↓&L - - Z O/L HDMI V SYNC input terminal for count

105 P14/D12 TDO O C - - - Z O/L JTAG terminal for rewriting

106 P13/D11 FPGATDI I - Lv - - Z O/L JTAG terminal for rewriting

107 P12/D10 TMS O C - - - Z O/L JTAG terminal for rewriting

108 P11/D9 TCK O C - - - Z O/L JTAG terminal for rewriting

109 P10/D8 HDMI IN1 O C - - Ed Z O/L HDMI input selection control terminal

110 P07/AN07/D7 HDMI IN2 O C - - Ed Z O/L HDMI input selection control terminal

111 P06/AN06/D6 HDMI IN3 O C - - Ed Z O/L HDMI input selection control terminal

112 P05/AN05/D5 HDMI R RST1 O C - - Ed Z O/L Reset for HDMI RECEIVER(Si I9031)(DVI/HDMI1)

113 P04/AN04/D4 HDMI R RST2 O C - - Ed Z O/L Reset for HDMI RECEIVER(Si I9031)(HDMI2/3)

114 P114 HDMI R RST3 O C - - Ed Z O/L Reset for HDMI RECEIVER(Si I9031)(HDMI4/5)

115 P113 SCDT I - Lv - - Z O/L HDMI RECEIVER(Si I9031) SCDT output detection

116 P112/ INT I - Lv - - Z O/L HDMI RECEIVER(Si I9031) INT output detection

117 P111/ WPCPU1 O C - - - Z O/L WRITE PROTECT terminalfor HDMI IN EDIT(24LC02)

118 P110/ WPCPU2 O C - - - Z O/L WRITE PROTECT terminalfor HDMI IN EDIT(24LC02)

119 P03/AN03/D3 PRMVCPU1 O C - - - Z O/L HDMI IN Terminal, HP DET control terminal

120 P02/AN02/D2 PRMVCPU2 O C - - - Z O/L HDMI IN Terminal, HP DET control terminal

121 P01/AN01/D1 AUDIO1 O C - - - Z O/L HDMI AUDIO selection

122 P00/AN00/D0 AUDIO2 O C - - - Z O/L HDMI AUDIO selection

123 P157/AN157 AUDIO3 O C - - - Z O/L HDMI AUDIO selection

124 P156/AN156 HDMI T RST1 O C - - Ed Z O/L Reset for HDMI TRANSMITTER (Si I9030)

125 P155/AN155 HDMI SENS1 I - E↓&L - - Z O/L HDMI IN signal detect input

126 P154/AN154 HDMI T RST2 O C - - Ed Z O/L Reset for HDMI TRANSMITTER (Si I9030)

127 P153/AN153 HDMI SENS2 I - E↓&L - - Z O/L HDMI IN signal detect input

128 P152/AN152/ CFSEL0 O C - - - Z O/L Image resolution selection control terminal

129 P151/AN151/ CFSEL1 O C - - - Z O/L Image resolution selection control terminal

130 VSS VSS - - - - - - - GND

131 P150/AN150/ VIDEO POWER O C - - Ed Z O/L VIDEO POWER control terminal(ON:"H")

132 VCC VCC - - - - - - - +3.3V

133 P107/AN7 IP RST O C - - Ed Z O/L Reset for IP CONVERTER(FLI2310)

134 P106/AN6 TE RST O C - - Ed Z O/L Reset for COMPONENT FORMAT DETECTOR (TE8200PF)

135 P105/AN5 VD RSTZ1 O C - - Ed Z O/L Reset for VIDEO DECODER(ADV7403)

136 P104/AN4 Z1CERST O C - - Ed Z O/L Reset for COMPONENT ENCODER(ADV7320)

137 P103/AN3 Z1SVERST O C - - Ed Z O/L Reset for S/CVBS ENCODER(ADV7320)

138 P102/AN2 (G BDOWN) O C - - (-) Z O/L NC(VIDEO-GUI communication control terminal)

139 P101/AN1 (RST G) O C - - (-) Z O/L NC(VIDEO-GUI communication control terminal)

140 AVSS AVSS - - - - - - - Analog GND

141 P100/AN0 (ACK GIVO) O C - - (-) Z O/L NC(VIDEO-GUI communication control terminal)

142 VREF VREF - - - - - - - Standard power input +3.3V

143 AVCC AVCC - - - - - - - Analog power +3.3V

144 P97/ADTRG/RXD4 (GOVI) O C - - (-) Z O/L NC(VIDEO-GUI communication control terminal)

Pin Pin name Symbol I/O Type Det Op(Int.) Op(Ext.) Res stop Function

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TEL 13942296513 QQ 376315150 892498299

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16

AVR-5805/AVC-A1XV-UPGRADE

SiI9033CTU (IC103, 153, 203)

Block Diagram

DSDA0 RESET#

INT

CSDA

CSCL

MCLKOUT

XTALIN

XTALOUT

SCK

WS

SD[3:0]

DL[3:0]

DR[3:0]

EVNODO

DE

HSYNC

VSYNC

ODCK

Q[23:0]

CLK48B

MUTEOUT

SCDT

SPDIF

DCLK

DSCL0

DSDA1

DSCL1

R1XC±

R1X0±

R1X1±

R1X2±

R0XC±

R0X0±

R0X1±

R0X2±

R0PWR5V

R1PWR5V

Port

MUX

PanelLink

TMDSTM

Digital

Core

PanelLink

TMDSTM

Digital

Core

I2C

Slave I2C

Slave

MCLK

Aux

Data

Audio

HDMI

Mode

Control

Video Color

Port

Detect

Spade

Converter

Up/Down

Sampling

Auto A/V

24-Bit

24-Bit Encrypted

Pixel Data

Control Signais

Decrypted

Pixel Data

Exception

Handling

Data

Men

Decode

Registers

HDCP

HDCP &

Port

MUX

XOR

Mask

Decryption

Engine

Repeater

Embedded Keys

Logic Block

Configuration

----------------

24-Bit

Date

24-Bit

Date

HS,VS,

DE

HS,VS,

DE

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17

AVR-5805/AVC-A1XV-UPGRADE

ADV7403BSTZ-110 (IC606)

Block Diagram

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TEL 13942296513 QQ 376315150 892498299

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18

AVR-5805/AVC-A1XV-UPGRADE

Pin description

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2

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9

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2

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2

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TEL 13942296513 QQ 376315150 892498299

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19

AVR-5805/AVC-A1XV-UPGRADE

K4S643232H-UC60 (IC505)

Block Diagram

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

N.C

V

DD

DQM0

WE

CAS

RAS

CS

N.C

BA0

BA1

A10/AP

A0

A1

A2

DQM2

V

DD

N.C

DQ16

V

SSQ

DQ17

DQ18

V

DDQ

DQ19

DQ20

V

SSQ

DQ21

DQ22

V

DDQ

DQ23

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

N.C

V

SS

DQM1

N.C

CLK

CKE

A9

A8

A7

A6

A5

A4

A3

DQM3

V

SS

N.C

DQ31

V

DDQ

DQ30

DQ29

V

SSQ

DQ28

DQ27

V

DDQ

DQ26

DQ25

V

SSQ

DQ24

V

SS

Bank Select

Data Input Register

512K x 32

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row Decoder Col. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE

CLK CKE CS RAS CAS WE DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

512K x 32

Timing Register

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TEL 13942296513 QQ 376315150 892498299

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AVR-5805/AVC-A1XV-UPGRADE

Pin description

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS Chip select Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM.

CKE Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disables input buffers for power down mode.

A

0

~ A

10

Address Row/column addresses are multiplexed on the same pins.

Row address : RA

0

~ RA

10

, Column address : CA

0

~ CA

7

BA0,1 Bank select address Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE Write enable Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

DQ

0

~

31

Data input/output Data inputs/outputs are multiplexed on the same pins.

V

DD

/V

SS

Power supply/ground Power and ground for the input buffers and the core logic.

V

DDQ

/V

SSQ

Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise

immunity.

NC No Connection This pin is recommended to be left No connection on the device.

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i

a

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y

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1

6

3

.

c

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m

Q

3

7

6

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1

5

1

5

0

9

2

8

9

4

2

9

8

T

E

L

1

3

9

4

2

9

6

5

1

3

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2

8

9

4

2

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1

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Denon AVR-5805-UPGRADE User manual

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