Digi NS7520 User manual

NS7520 Jumpers and Components
90000354_C

Part number/version: 90000354_C
Release date: January 2006
www.digi.com
NS7520 Jumpers and
Components Guide

Digi International
11001 Bren Road East
Minnetonka, MN 55343 U.S.A.
United States: [phone]
Other locations: [phone]
www.digi.com/support/
www.digi.com
©2001-2006 Digi International Inc.
Printed in the United States of America. All rights reserved.
Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi
International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi
International, Inc. in the United States and other countries worldwide. All other trademarks are the
property of their respective owners.
Information in this document is subject to change without notice and does not represent a committment
on the part of Digi International.
Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including,
but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi may
make improvements and/or changes in this manual or in the product(s) and/or the program(s) described
in this manual at any time.
This product could include technical inaccuracies or typographical errors. Changes are made periodically
to the information herein; these changes may be incorporated in new editions of the publication.

Contents
      iii
Chapter 1: Hardware Description ......................................... 1
Overview .................................................................................. 2
Features of the development board .................................................. 2
Chip select configuration............................................................... 3
Jumpers ................................................................................... 3
Connectors................................................................................ 6
Ethernet interface....................................................................... 6
Chapter 2: Schematics ........................................................... 7
Schematics................................................................................ 8
Chapter 3: Bill of Materials ................................................. 21
BOM — NS7520 development board .................................................. 22

       v
Using This Guide
Review this section for basic information about this guide, as well as for general
support contact information.
About this guide
This guide provides information about the jumpers and components of the NS7520
development boards. The NS7520, part of the NET+ARM line of SoC (System-on-Chip)
products, supports any type of high bandwidth application in Intelligent Networked
Devices.
The NET+ARM is part of the NET+Works integrated product family, which includes the
NET+OS network software suite.

Using This Guide
vi        NS7520 Jumpers and Components, Rev. C 01/2006
Who should read this guide
This guide is for hardware developers, system software developers, and application
programmers who want to use the NS7520 for development.
To complete the tasks described in this guide, you must:
Understand the basics of hardware and software design, operating systems,
and microprocessor design.
Understand the NS7520 architecture.
What’s in this guide
This table shows where you can find information in this guide:
To read about See
A description of the NET+Works development
board hardware
Chapter 1, “Hardware Description”
The NS7520 board schematics Chapter 2, “Schematics”
The bill of materials (BOM) for the NS7520
development board
Chapter 3, “Bill of Materials”

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Using This Guide
Conventions used in this guide
This table describes the typographic conventions used in this guide:
Related documentation
For information on the chip you are using, see the NS7520 Hardware
Reference.
For information on third-party products and other components, review the
documentation CD-ROM that came with your development kit.
See the NET+OS software documentation for information appropriate to the
chip you are using.
Documentation updates
Digi occasionally provides documentation updates on the Web site (www.digi.com/
support).
Be aware that if you see differences between the documentation you received in your
package and the documentation on the Web site, the Web site content is the latest
version.
This convention Is used for
italic type Emphasis, new terms, variables, and document titles.
bold, sans serif type Menu commands, dialog box components, and other items
that appear on-screen.
Select Menu →option Menu commands. The first word is the menu name; the
words that follow are menu selections.
monospaced type Filenames, pathnames, and code examples.

Using This Guide
viii        NS7520 Jumpers and Components, Rev. C 01/2006
Customer support
To get help with a question or technical problem with this product, or to make
comments and recommendations about our products or documentation, use the
contact information listed in this table:
For Contact information
Technical support United States: [phone]
Other locations: [phone]
www.digi.com/support
www.digi.com

       1
Hardware Description
CHAPTER 1
This chapter provides a hardware description of the NS7520 development board. In
addition, this chapter describes how to configure the base address for each chip
select.

Overview
2        NS7520 Jumpers and Components, Rev. C 01/2006
Overview
The board is identifiable by this information:
Market name. NET+Works Development Board
Part number. 6152000
NS7520. Consists of a 177-pin BGA package. The NS7520 is a high-
performance, cost-effective, highly-integrated 32-bit chip, designed for use
in intelligent network devices and Internet appliances.
Features of the development board
The NET+Works development board provides these basic features:
55 MHz NS7520.
18.432 MHz crystal or an external oscillator. NS7520 development boards
may be populated with an external 18.432 MHz crystal or 55 MHz oscillator
for system clock generation.
ARM JTAG ICE port
20 LED indicators: eight each on PORT A and PORT C, two on the Ethernet
connector, one power indicator, and one CPU LED
2 ASYNC 1 Mbps serial ports, one with RS485 option, user selectable
10/100BaseT Ethernet port
128 Mb SDRAM (16 MB)
2 MB flash, expandable to 16 MB
Bootstrap configuration headers
Breakout headers for logic analyzer connections
GPIO PORTA and PORTC breakout headers

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Hardware Description
Chip select configuration
The peripheral devices can be tied to different chip selects on the NS7520. The chip
select must be configured using NS7520 development board jumpers (as shown in this
table). CSSEL0 is set to 0 by installing the jumper at JP14 and set to 1 by removing
the jumper at JP14. CSSEL1 is set to 0 by installing the jumper at J20 and set to 1 by
removing the jumper at JP20.
The board is built and shipped with CS0 set to flash; CS1 set to SDRAM, and CS4 set to
PIC(u9).
Jumpers
This table defines the jumpers. The entry default = DISABLED means that the jumper
is removed from the board.
CSSEL1 CSSEL0 Chip selects
0 0 CS0= flash; CS1= SDRAM; CS4= PIC(u9)
0 1 CS2= flash; CS1= SDRAM; CS0= PIC(u9)
1 0 CS3= flash; CS1= SDRAM; CS2= PIC(u9)
1 1 CS4= flash; CS1= SDRAM; CS3= PIC(u9)
Signal name Purpose
JP1 Port C RS485; 1-2 = ENABLE; default = DISABLED
JP2 Reserved
JP3 Port C RS485; 1-2 = ENABLE; default = DISABLED
JP4 Reserved
JP5 Port A Force 232 OFF; 1-2 = DISABLED; default = ENABLED
JP6 Port C Force 232 OFF; 1-2 = DISABLED; default = ENABLED
JP7 Port C RS485; 1-2 = ENABLE; default = DISABLED
JP8 Reserved

Jumpers
4        NS7520 Jumpers and Components, Rev. C 01/2006
JP9 Port C RS485; 1-2 = ENABLE; default = DISABLED
JP10 Port C RS232/485; 1-2 = ENABLE RS232; 2-3 = ENABLE RS485
JP11 8 pin Header Port C GPIO [0:7]
JP12 6 pin JTAG header for U9 CPLD (ISP)
JP13 BWSEL0; 1-2 = 0; default = 1; Bus Width Select
JP14 CSSEL0; 1-2 = 0; default = 1; Chip Select Config
JP15 8 pin Header Port A GPIO [0:7]
JP16 TDO_PIC; 1-2 = TDO signal from JP12 Header to U9
JP17 TDI_PIC; 1-2 = TDI signal to U9
JP18 FLASH_EN; 1-2 = ENABLED; default = DISABLED
JP19 BWSEL1; 1-2 = 0; default = 1; Bus Width Select
JP20 CSSEL1; 1-2 = 0; default = 1; Chip Select Config
JP21 JTAG TDO ENABLE; 1-2 = ICE (default); 2-3 = Boundary SCAN
JP22 Reserved
JP23 Reserved
JP24 Reserved
JP25 A27 Endian configuration; 1-2 = little; default = big
JP26 A26 CPU Bootstrap; 1-2 = ARM CPU disabled; default = ARM CPU
Enabled
JP27 A25 GEN_IARB; 1-2 = External Bus Arbiter; default = Internal Bus
Arbiter
JP28 A24 CSO/MMCR[19]; 1-2 = 0; default = 1; CSO Bootstrap Setting
JP29 A23 CSO/MMCR[18]; 1-2 = 0; default = 1; CSO Bootstrap Setting
JP30 A22 Reserved
JP31 A21 Reserved
JP32 A20 Reserved
JP33 A19 GEN_ID[10]; 1-2 = 0; default = 1; user defined
JP34 A18 GEN_ID[9]; 1-2 = 0; default = 1; user defined
JP35 A17 GEN_ID[8]; 1-2 = 0; default = 1; user defined
Signal name Purpose

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Hardware Description
JP36 A16 GEN_ID[7]; 1-2 = 0; default = 1; user defined
JP37 A15 GEN_ID[6]; 1-2 = 0; default = 1; user defined
JP38 A14 GEN_ID[5]; 1-2 = 0; default = 1; user defined
JP39 A13 GEN_ID[4]; 1-2 = 0; default = 1; user defined
JP40 A12 GEN_ID[3; 1-2 = 0; default = 1; user defined
JP41 14 pin JTAG header for NS7520
JP42 A11 GEN_ID[2]; 1-2 = 0; default = 1; user defined
JP43 A10 GEN_ID[1]; 1-2 = 0; default = 1; user defined
JP44 A9 GEN_ID[0]; 1-2 = 0; default = 1; user defined
JP45 A8 PLL_IS[1]; 1-2 = 0; default = 1
JP46 A7 PLL_IS[0]; 1-2 = 0; default = 1
JP47 A6 PLL_FS[1]; 1-2 = 0; default = 1
JP48 A5 PLL_FS[0]; 1-2 = 0; default = 1
JP49 A4 PLL_ND[4]; 1-2 = 0; default = 1
JP50 A3 PLL_ND[3]; 1-2 = 0; default = 1
JP51 A2 PLL_ND[2]; 1-2 = 0; default = 1
JP52 A1 PLL_ND[1]; 1-2 = 0; default = 1
JP53 A0 PLL_ND[0]; 1-2 = 0; default = 1
JP54 SCANEN; 1-2 = 0; default = 1; active low signal
JP55 PLLTST; 1-2 = 0; default = 1; active low signal
JP56 BISTEN; 1-2 = 0; default = 1; active low signal
Signal name Purpose

Connectors
6        NS7520 Jumpers and Components, Rev. C 01/2006
Connectors
This table defines the connectors and their designations:
Ethernet interface
The development board provides a full-duplex 10/100 Mbps Ethernet interface using
the Intel 3V PHY in a BGA package, which uses the standard MII interface.
The RJ45 connector is integrated with the isolation transformer, EMI filter
components, link, and receive LEDs.
You also can use the MII interface to determine the current Ethernet link status.
Change of link status can cause an interrupt on IRQ0*.
Reference
number Type Purpose
J1/J3 Mini/din jack Power connector - 5 pin din populated
J5 RJ45 MAG-jack 10/100 BT Ethernet with magnetics and LEDs
J6-12 Mictor 38 pin Breakout emulator headers
P1 DB9 male Serial port A RS232, 1 Mbps, full modem
support
P2 DB9 male Serial Port C RS232, 1 Mbps or RS485
JP41 Header 2x7 ARM ICE port
P3 Header 1x6 Manufacturing test plug

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Schematics
CHAPTER 2
This chapter provides the schematics for the development board. The schematics
in this chapter are at a small scale. For larger (and most up-to-date) diagrams, see
the file NS7520_schematics.pdf on the NS7520 hardware documentation CD.

Schematics
8        NS7520 Jumpers and Components, Rev. C 01/2006
Schematics
Cover sheet
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SHEET DESCRIPTI ON
4. C CPU-B, & CPU-C
2. D Block Diagr am
DESCRIPTION SH. #
5. B 32/16 Bit SDRAM, B us Transceivers
NOTES:
07/15/02 1952000 REV A
8. B FPGA-A, Ext. Board Mictor Conns
CONFIDENTIAL MATERIAL TO NetSilicon - A Digi Internati onal Company
NS7520
3. C CPU-A & BCL K Buffer
GLOBAL FUDUCIA LS
9. B FPGA-B, -C, ISP PROM
4. ALL CAPACITORS ARE RATED AT 50 VDC OR HIGHER UNLESS OTHERWISE NOTED
BOARD REV NOTES
12. B Mictor Co nnectors
DESIGNER: Jan Szymbo rski
SHEET REV NOTES
7. B FL ASH, SRAM, DRAM
REV.
DEVELOPMENT BOARD
11. B Ethernet In terface
1. ALL RESISTOR VALUES ARE IN OHMS AND IN THE 0603 SIZE UNLESS OTHERWISE NOTED
13. B Power Supply & LEDs
6. B PIC CPLD
10. B Serial RS232/485 Ports A & B
2. ALL RESISTOR VALUES ARE 5% UNLESS OTHERWISE NOTED
BOARD REVISIONS
REF S CH1952000
1. D Co ver Sheet
5. LAST USED:
TOOLING HOL ES
March 8, 200 3: Added Cover sheet and Block Diagram as page 1 & 2. Bumped up
rest of sheets by two page numbers and updated al l title blocks to NS7520. No
schematic change s were made to Pages 3-13.
Aug. 28, 20 03: Block Diagram Updated (page 1 & 2)
3. ALL CAPACITORS ARE RATED IN uFARADS AND IN THE 0603 SIZE UNLESS OTHERWISE NOTED
Sep. 23, 2004: Bl ock Diagram, CPUIA & CPUB updated: (pages 1-4)
Aug. 25, 2005: 1. C orrected population option for oscillator vs
crystal. (pages 2 & 3); 2. Updated s heet page references
(pages 3-13); 3. Added corrections to page 2 for Vantives
1678 1-16782.
PAGE01.S CH
D
NS7520 Cove r Sheet
NetSilicon - A Digi International Company
B
1
13 Thursday, August 25, 2005
Titl e
Size Document Number Rev
Date: Sheet of
NC
SP5
FID
NC
SP6
FID
NC
SP4
FID
NC
Z1
MT _125
NC
Z2
MT _125
NC
Z3
MT _125
NC
Z4
MT_125
NC
SP1
FID
NC
SP3
FID
NC
SP2
FID

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Schematics
Block diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.5 V LDO
RESET*
232 or 485 jumpe rs
P2 DB9-M
8
PW R
10/ 100
MAC
GPIOA
JP12
PO RT C
P1 DB9-M
18 .432MHz
(C0)
PORT C
MICTOR 46 PIN J 10
Buffer
CONT'L LINES
J5 RJ 45
(C5)
(A0)
18
32 address/cntrl
SPI_ RXD
3.3 V
5V
SD_C K
(A5)
NS7520
28
(A4)
JP41
PIC_C K
SPI
MAG-
JACK
14 pin
MII
SDRAM memory , x32(16MB,1 28Mb)
(C2)
(A7)
JP11
(C7)
XTAL1
PORT A
DEBUG
RS23 2
3.3 V
MICTOR 46 PIN JP6
3.3 V
-SRST
19 control lines
(C2)
CPLD
JTAG
JP25 - JP40, JP42 - JP53
BCLK
RESET P.B.
CORE, PL L
RS485
Add ress
19 control lines
16 GPIO(port
A, C)
25M Hz
BGA
PORT A
JP15
LDO
Link
LED
Cont rol
(A3)
-TRST
Data
J2 DIN
Crystal
Optional
MICTOR 46 PIN JP9
D31:0
POWER IN - 5V@1 .5A
3
Buffer
3.3 V
SPI_ RXD
MICTOR 46 PIN J 12
(A6)
SD_C K
BC K4
-TRST1
Addr ess
(C6) (C3)
LXT9 71 PHY
10/10 0 BTX
BGA
PORT C
RS23 2
CUST. LEDS
I/ O
32 address/cntrl
CPLD
YEL
-TRST
5V
32 data lines
(A2)
3.3 V
Bu ffer
3
MICTOR 46 PIN JP7
-SRST
(C1)
-TRST1
Re ceive
LED
FLASH m emory, x32(2MB)
Ethernet
Interface
-RST
(C4)
3.3 V
3.3 V
A27:0
Headers for Address
Boots trap Config
NS752 0
JTAG
BCK4
PORT A
GPIO C
1.5 V
Clo ck
Bu ffer
OSCILLATOR
55 .000MHz
P4
-RST
MAX811 R
MICTOR 46 PIN J 11
MICTOR 46 PIN JP8
3.3 V
4 pin
JP1,3,6,7,9,10
(A1)
XTAL2
28
32 data lines
PORT A
6 pin
PAGE02.S CH
D
NS7520 Dev. Brd. Block D iagram
NetSilicon - A Digi International Company
B
2
13 Tuesday, August 23, 2005
Titl e
Size Document Number Rev
Date: Sheet of

Schematics
10        NS7520 Jumpers and Components, Rev. C 01/2006
CPU-A & B CLK Buffer
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ERRATA FIX:
Inverter require
d
in place of JP54 .
NOT ADDED ON DE V
PCB
R129
SHOULD BE 2.4K
DNP
RESET_L rise time = 1 8ns Max.;
0.8V to 2.0V
C
NS75 20 CPU-A & Clock Buffer
NetSilicon - A Digi International Comp any, Waltham, MA
3 13 Thursday, August 25, 2005
PAG E03.SCH
Title
Siz e Document Number Rev
Date: Sheet of
BISTEN_L
SCANEN_L
CS_L1
D16
D10
CASA_L3
CASA_L0
RESET_L
D18
D9
D4
D22
D19
CS_L4
D14
D13
D0
D29
D26
CASA_L3
CASA_L1
D31
D3
CS_L1
D15
D8
CS_L0
CASA_L0
D30
D21
D12
D11
CS_L3
D20
D2
CS_L2
D25
D23
D1
PL LTST_L
D28
D24
CASA_L1
D27
D17
D7
CASA_L2
D6
D5
CASA_L2
TDO
BCLK
TDI
CAS_L3
CAS_L1
CAS_L2
CAS_L0
BE_L3
BE_L0
BE_L2
BE_L1
CASA_L[3..0]
BEA_L[3..0]
BEA_L1
BEA_L0
BEA_L1
BEA_L2
BEA_L2
BEA_L3
BEA_L0
BEA_L3
BCLKA
A6
A22
A24
A11
A6
A1
A3
A9
A10
A17
A16
A23
A14
A20
A15
A26
A10
A11
A8
A12
A21
A13
A27
A8
A21 A22
A18
A0
A20
A25
A3
A4
A25
A5
A17
A2
A8
A9
A11
A16
A15
A7
A7
A19
A4
A14
A9
A22
A26
A1
A5
A0
A18
A27
A4
A2
A7
A23 A24
A13
A5
A6
A2
A3
A10
A23
A13
A12
A19
XTA LA1
SD32_A11
SD32_A3
SD32_A12
SD32_A8
SD32_A4
SD32_A0
SD32_A13
SD32_A7
SD32_A2
SD32_A5
SD32_A9
SD32_A1
SD32_A6
XTA LA2
CLKA2
CLKB3
CLKB4
CLKB2
CLKA1
CLKA3
CLKA4
CKDRV_VDD
OSC
VDD_55M
RESET_L
D[31..0]Sh-5,12
BR_L Sh-8
A[27..0] Sh-5,12
BE_L[3..0] Sh-5,12
CS_L[4..0] Sh-6,8
RW_L Sh-6,8
WE_L Sh-6,8,12
SD32_CS_L Sh-5
BG_L Sh-8
BCLK_XBD Sh-8
RESET_L Sh-6..8,13
BUSY_L Sh-6,8
TEA _L Sh-8
TA _L Sh-8
TS _L Sh-8
TMS Sh-6,9
TRST_ L Sh-6
TCK Sh-6,9
TDO_FPGA Sh-6,9
ICETRST_L Sh-6
ICESRST_L Sh-6
TDO_20UM Sh-6
CAS_L[3..0] Sh-5,6,12
SD32_A[13..0] Sh-5
OE_L Sh-6,8,12
BCLK_FPGA Sh-9
BCLK_PIC Sh-6
BCLK_SD16 Sh-5
BCLK4 Sh-12
BCLK_SD32 Sh-5
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V
3.3V
3.3V
JP52
JP47
RA23
RA_38V 2.7K
1
2
3
4 5
6
7
8
C133
10pF
RA15
RA_38V 33
1
2
3
4 5
6
7
8
R93
33
R6
33
JP29
JP40
RA16
RA_38V 2.7K
1
2
3
4 5
6
7
8
JP38
SYSTEM BU S
U19A
NS7520
NS7520-BGA177
D7
C7 B7
B9
C9
A9
D9
D6
A8
C8
D8
C6
B6
D5
B5
C5
A4
C2
D3
D4
B1
C1
D1
E3
E2
E1
F3
F2
F4
G2
G3
G1
G4
H2
H1
H4
H3
J1
J3
J2
K1
K2
K3
L1
L4
L2
L3
M1
N1
B4
N10
P10
M10
R10
N9
R9
M9
N8
P8
M7
R7
N7
R6
M6
P6
N6
M5
P5
N5
R4
R3
R2
M4
N4
R1
M3
N2
P1
A10
K14
K12
A6
N15
M15
L13
A2
B3
C4
A1
N14
M12
P15
M13
M14
M11
P11
N11
R12
R14
P13
BR_
BG_ BUSY_
BE0_
BE1_
BE2_
BE3_
RW_
TS_
TEA_
TA_
WE_
OE_
CS0_
CS1_
CS2_
CS3_
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CS4_
A27/CS0OE_
A26/CS0WE_
A25/BLAST_
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RESET_
XTALA1
XTALA2
BCLK
PLLTST_
BISTEN_
SCANEN_
CAS0_
CAS1_
CAS2_
CAS3_
TDI
TMS
TCK
TDO
TRST_
NC1
NC2
NC3
NC4
NC5
NC6
R125
2.4K
JP55
JP33
R129
53.6K
R107
100
JP50
RA28
RA_38V 10K
1
2
3
4 5
6
7
8
R9
33
TP8
TS TP
1
JP43
R102
0
JP51
RA18
RA_38V 33
1
2
3
4 5
6
7
8
C122
10pF
JP45
JP56
R95
0
RA21
RA_38V 2.7K
1
2
3
4 5
6
7
8
R94
33
R120
2.4K
JP34
RA22
RA_38V 2.7K
1
2
3
4 5
6
7
8
R103 1ME G
JP26
JP48
C145
.1
RA17
RA_38V 2.7K
1
2
3
4 5
6
7
8
L18
BEAD_0805_201
R7
2.4K
XU 2
SG-BGA-6002
177-BGA SCKT
JP53
NC
U31
INV_SOT23
1
23
4
5
R3
33
JP31
JP46
JP41
HEADER 7X2
12 34 56 78 9
10 11
13
12
14
12 34 56 78 9
10 11
13
12
14
C15
.1
JP39
U20
EC2600_T TS_55M
3
4
1
2
OUT
VCC
E/D
GND
JP27
Y2
18.432MHZ_FPX_SM
1 4
32
U18
CY2309_TSSOP16
4
12
13
3
5
15
1
9
10
6
11
14
2
7
16
8
VDD
GND
VDD
CLKA2
GND
CLKA4
REF
S1
CLKB3
CLKB1
CLKB4
CLKA3
CLKA1
CLKB2
CLKOUT
S2
JP54
JP44
R4
33
RA26
RA_38V 33
1
2
3
4 5
6
7
8
R124
2.4K
R8
33
JP49
RA19
RA_38V 2.7K
1
2
3
4 5
6
7
8
L9
BEAD_0805_201
JP30
RA14
RA_38V 33
1
2
3
4 5
6
7
8
JP35
R5
33
JP37
JP32
JP42
RA20
RA_38V 33
1
2
3
4 5
6
7
8
JP28
R2
33
JP21
JPR3
JP25
R101
33
JP36
C19
.1
RA25
RA_38V 2.7K
1
2
3
4 5
6
7
8