Digital Equipment PDP-11 Series User manual

PDP-11/40,-11/35
(21 inch chassis)
system manual

PDP-11/40,-11/35
(21 inch chassis)
system manual
DEC-ll-H40SA-B-D
digital equipment corporation •maynard.massachusetts

First Edition, June 1973
2nd Printing (Rev), February 1974
3rd Printing, July 1974
4th Printing, January 1975
Copyright© 1973, 1974, 1975 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respo11-
sibility for any errors which may appear in this
manual.
Printed in U.S.A.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
.FLIP CHIP
DIGITAL
UNIBUS
PDP
FOCAL
COMPUTER LAB

CHAPTER 1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.5.1
1.3.5.2
1.3.5.3
1.3.6
1.3.7
1.3.8
1.4
1.5
CHAPTER2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.4
2.3
2.3.l
2.3.2
2.3.3
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.6
2.3.7
2.3.8
2.4
2.5
CONTENTS
INTRODUCTION
SCOPE ............. .
SYSTEM COMPONENTS
FUNCTIONAL DESCRIPTION
Unibus .......... .
KD11-A Processor . . . . .
KY11-D Programmer's Console
MFl 1-L Core Memory ..
Optional Memory Systems
PDP-11 /40 Memories
PDP-11 /20 Memories
MFl 1-U/UP Core Memory
LA30 DECwriter . . . . . . . .
DLI 1 Asynchronous Line Interface
Power System . . . . . . . . . . . .
APPLICABLE DOCUMENTATION
ENGINEERING DRAWINGS ...... .
INSTALLATION
SCOPE ......... .
SITE PREPARATION ..
Physical Dimensions
Fire and Safety Precautions
Environmental Requirements
Humidity and Temperature
Air Conditioning . . .
Acoustical Damping
Lighting ........ .
Special Mounting Conditions
Static Electricity . . .
Electrical Requirements
INSTALLATION PROCEDURES
Unpacking ....
Inspection . . . . . . . . . . ,
Cabinet Installation
A,C Power Connections . . .
Intercabinet Connections
Unibus Connections
Remote Power Connections
Ground Strapping . . . . .
Remote Peripheral Interconnection
Installation Verification ..... .
Initial Power Turn-on . . . . . . .
INITIAL OPERATION AND PROGRAMMING
CUSTOMER ACCEPTANCE ..... , ..... .
Page
1-1
1-1
1-1
1-4
1-5
1-6
1-6
1-7
1-7
1-8
1-9
1-9
1-10
1-10
1-11
1-13
2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-3
2-3
2-3
2~3
2-3
2-4
2-4
2-5
2-5
2-6
2-6
2-6
2-6
2-6
2-7
2-7
2-12
2-13
2-13

CHAPTER3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.3
3.5.4
3.5.4.1
3.5.4.2
3.5.5
3.6
CHAPTER4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
CHAPTERS
5.1
5.2
CHAPTER6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2
CONTENTS (Cont)
Page
SYSTEM OPERATION
SCOPE .............•...
KYl 1-D PROGRAMMER'S CONSOLE
. . . . . . . . . . . . . . . . . . . . . . . . 3-1
......... •· . . . . • . . . . . . . . . 3-1
DECwriter ........ .
.. ' ..................... 3-15
TELETYPE ..... .
BASIC OPERATION ... .
Power On
Basic Console Control
ENABLE/HALT Switch
Loading Data Manually
Manual Program Loading (Bootstrap Loader)
Automatic Program Loading . . . .
Loading Absolute Loader
Loading Maintenance Loader
Running Programs
BASIC PROGRAMMING . . . . . . .
PROCESSOR INSTRUCTIONS AND OPTIONS
SCOPE ....... .
INSTRUCTION SET . . . .
Address Modes . . . .
Basic Instruction Set .
Extended Instruction Set
PROCESSOR OPTIONS . . .
KEl 1-E Extended Instruction Set (EIS) Option .
KEl 1-F Floating Instruction Set (FIS) Option
KJl 1-A Stack Limit Register Option ...... .
KTl 1-D Memory Management Option .
KWl 1-L Line Time Clock Option
KMll-AMaintenance Console Option
Small Peripheral Controller
SYSTEM PERIPHERALS AND OPTIONS
SCOPE ............ .
PERJPHERALS AND OPTIONS . . . . .
EQUIPMENT MOUNTING AND POWER
SCOPE ................. .
SYSTEM MOUNTING BOX . . . . . . .
Processor Module Allocations
Memory Module Allocations . . .
Programmer's Console Mounting .
CABINET AND SYSTEM MOUNTING
System Cabinet
System Configuration
iv
• .....
.. . ~
. . . . . . ... 3-15
................ 3-19
............... 3-20
. . . . . . . . . . 3-20
.............. 3-20
.... 3-20
............. 3-21
..... 3-25
............. 3-26
.............. 3-28
. . . . . . . . . . 3-29
.............. 3-29
. -· ......
. . . . . 4-1
4-1
4-3
4-5
. 4-17
. 4-22
. 4-23
. 4-24
.. 4-25
...... 4-26
....... 4-27
. .... 4-29
....... 4-29
. . . . . . . 5-1
5-1
6-1
6-1
6-3
6-3
6-3
. . . . . . . . . 6-3
6-5
6-5

6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.2.3
6.4.3
6.4.3.1
6.4.3.2
6.4.3.3
6.4.4
6.4.4.1
6.4.4.2
6.4.4.3
6.4.4a
6.4.5
6.4.6
6.4.7
6.4.7.1
6.4.7.2
CHAPTER 7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.3
7.4.3.1
7.4.3.2
7.4.4
7.4.5
7.4.5.1
7.4.5.2
CONTENTS (Cont)
POWER SYSTEM
861 Power Controller
H742 Power Supply
H742 +15V Output
H742 Clock Output
AC LO and DC LO Circuits
H744 +5V Regulator . . . . . .
H744 Regulator Circuit
H744 Overcurrent Sensing Circuit
H744 Overvoltage Crowbar Circuit
H745 - l 5V Regulator . . . . . . . . .
H745 Regulator Circuit . . . . .
H745 Overcurrent Sensing Circuit
H745 Overvoltage Crowbar Circuit
H754 +20, -5V Regulator ...
861 Power Controller Interconnection
Power System Cable Harnesses . . . .
DC Power Distribution . . . . . . . .
Early Power Distribution Systems
Newer Power Distribution Systems
GENERAL MAINTENANCE
SCOPE ..................... .
OVERALL MAINTENANCE TECHNIQUES
Knowledge of Proper Hardware Operation .
Detection and Isolation of Error Conditions
Means of Repairing Error Conditions
Digital Field Service . . . . . . . . .
MAINTENANCE EQUIPMENT REQUIRED
PREVENTIVE MAINTENANCE
Physical Checks . . . . . . . . . . .
Electrical Checks and Adjustments . .
Processor Clock Adjustment Check
Voltage Regulator Checks
861 Power Controller ..... .
AC Power Connector Receptacles
ASR 33 Teletype . . . . . . . . . .
Preventive Maintenance Checks
Lubrication . . . . . . . . .
LA30 DECwriter Preventive Maintenance
PC05 High-Speed Paper-Tape Read/Punch Option
Mechanical Checks
Electrical Checks ............. .
v
Page
6-7
6-9
6-9
6-10
6-10
6-10
6-10
6-11
6-12
6-12
6-12
6-12
6-12
6-13
6-13
6-13
6-15
6-15
6-16
6-18
7-1
7-1
7-1
7-2
7-2
7-2
7-3
7-3
7-3
7-3
7-5
7-5
7-5
7-5
7-5
7-5
7-6
7-6
7-6
7-6
7-7

7.5
7.5.1
7.5.2
7.6
7.7
7.7.1
7.7.2
CONTENTS (Cont)
DIAGNOSTIC PROGRAMS . . . . .
General Description . . . . . .
Diagnostic Program Utilization .
USE OF MODULE EXTENDERS . .
PDP-11/40 POWER SYSTEM MAINTENANCE .
Visual Inspection . . .
Power System Checks . . . . . . . . . . .
APPENDIX A SUMMARY OF EQUIPMENT SPECIFICATIONS
Figure No.
1-1
3-la
3-lb
3-2
3-3
3-4
3-5
4-1
4-2
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
Table No.
1-1
1-2
1-3
ILLUSTRATIONS
Title
PDP-11/40 Basic System Block Diagram ................ .
PDP-11 /40Programmer's Console . . . . .
PDP-11/35 Programmer's Console .......... .
LA30-S Keyboard . . . . . . . . .
LA30 Power Controls . . . . . . . . . . . . . . . . .
Teletype Controls . . . . . . . . . . . . . . . . . .
Flowchart of Procedure for Loading and Running Programs .
Double and Single Operand Addressing . . . . . .
Instruction Formats . . . . . . . . .
PDP-11/40 System Cabinet . . . . . . .... .
PDP-11/40 Mounting Box (BAll-FC) ..... .
Module Allocation -KDl 1-A Processor, Basic and Options ..
Module Allocation - MF 11-L Memory, Basic and Optional MM 11-Ls .
Typical Multiple Cabinet System Configuration . . . . . . . . .
PDP-11/40 Power, System Block Diagram .............. .
Precision Voltage Regulator El, Simplified Diagram ......... .
Power Control Interconnection . . . . . . . . . . . . . . . . . . . .
Regulated DC Power Distribution . . . . . . . . . . . . . . . . . . .
Power Distribution -Early Units with System Serial No. 5999 and Lower
Power Distribution Schematic -Early Systems
(System Serial No. 5999 and lower) ................... .
MFll-U/UP Installation -Early Systems ................ .
Power Distribution - Newer Unit with System Serial No. 6000 and Higher
Power Distribution Schematic - Newer Systems
(System Serial No. 6000 and Higher) .................. .
Possible PDP-11/40 Variations .
Applicable Documents . . . . .
Drawing Set/Sheet Code Prefixes
TABLES
Title
vi
Page
7-7
7-7
7-9
.. 7-12
..... 7-12
. .... 7-12
. .... 7-12
Page
1-4
3-2
3-2
.. 3-16
.. 3-16
.. 3-17
.. 3-23
4-4
4-4
6-2
6-3
6-4
6-4
6-6
6-8
.. 6-11
.. 6-14
. . 6-16
.. 6-17
. . 6-19
. 6-20
.. 6-21
.. 6-22
Page
1-2
l-11
1-14
c

Table No.
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
5-1
6-1
6-2
7-1
7-2
7-3
74
7-5
TABLES (Cont)
Option Installation Verification
Memory Verification or Installation
PDP-11 /40 Console Indicators
PDP-11 /40 Console Controls .
LA30 Controls and Indicators
Teletype Controls . . . . . .
Program Identification Codes
Title
Bootstrap Loader (DEC-11-LIPA-LA)
Binary Tape Load Selection (using Absolute Loader)
Relocation of Memory Contents .
PDP-11 Programming Comparison
ISP Symbology . . . . . . .
Address Modes . . . . . . .
Double Operand Instructions
Single Operand Instructions
Register Source or Destination Instruction
Branch Instruction . . . .
Miscellaneous Instructions . .
Condition Code Operators . .
Extended Instruction Set (EIS)
Floating Instruction Set (FIS)
Memory Management Instruction Set
Location of Processor Options
KEl 1-E (EIS) Specifications
KEl 1-F (FIS) Specifications
KJl 1-A Specifications
KTl 1-D Specifications .. .
KWl 1-L Specifications .. .
PDP-11 /40 Peripherals and Options
Timing Characteristics of PDP-11 NPR Devices
Priority of Devices Affected by BR Latency
Maintenance Equipment Required
DC Output Voltages . . . . . . . . . . . .
PDP-11/40 Diagnostic Programs ..... .
PDP-11/40 Processor Preliminary Diagnostic Program Error Analysis
Power System Troubleshooting Guide . . . . . . . . . . . . . . . .
vii
Page
2-8
2-10
3-3
3-7
3-15
3-17
3-22
3-24
3-27
3-28
3-30
4-2
4-3
4-6
4-8
4-12
4-13
4-15
4-16
. 4-18
4-20
4-22
4-23
4-24
4-26
4-27
4-28
4-28
5-1
6-5
6-7
7-4
7-5
7-8
7-10
7-13

FOREWORD
This Manual describes all PDP-11 /40s and those PDP-11 /35s that are
mounted in a 21-inch, (as opposed to a 10-1/2 inch) box.
Text references that specify "PDP-11 /40" also apply to the PDP-11 /35.
ix

1.1 SCOPE
CHAPTER 1
INTRODUCTION
This manual provides a general introduction to the PDP·l 1/40 System and includes sections on installation,
operation, the instruction set, options, peripherals, equipment mounting, power, and maintenance. This overview is
supplemented with references to other manuals in the PDP-11 /40 series for detailed explanations.
The PDP-11/40 series manuals provide the user with the theory of operation necessary to understand, operate, and
maintain the PDP-11 /40 System. These manuals and the associated engineering drawings are discussed in Paragraph
1.4. Please note that the associated drawings are separate volumes documented by their Drawing Directory number.
The manuals and drawings combine to form a complete documentation package.
The level of discussion in each manual assumes that the reader is familiar with basic digital computer theory. The
maintenance philosophy presents information about normal system operation and enables the user to recognize
trouble symptoms and take necessary corrective action. Each individual manual contains theory of operation,
diagrams, and maintenance techniques. Logic drawings for the specific components covered are contained in separate
volumes.
This chapter describes the basic system components (Paragraph 1.2) and provides a functional description of the
overall PDP-11/40 System and each of its major components (Paragraph 1.3). The remainder of the chapter covers
applicable documents and engineering drawings (Paragraphs 1.4 and 1.5).
1.2 SYSTEM COMPONENTS
The PDP-ll/40 System consists of six basic components: processor, programmer's console, core memory,
DECwriter with associated control, power system, and mounting box. Possible variations to this basic system are
listed in Table 1-1.
Options and peripherals added to the basic PDP-11/40 System are covered in separate manuals delivered with the
system. Manuals are included only for those options specifically ordered with an individual system.
1.3 FUNCTIONAL DESCRIPTION
The PDP-11/40 is a 16-bit, general purpose, parallel logic, microprogrammed computer using single and double
operand instructions and 2's complement arithmetic. The system contains a multiple word instruction processor,
which directly addresses up to 28K words of core memory. All communication among system components
(including processor, core memory, and peripherals) is performed on a single high-speed bus, the Unibus. Because of
the bus concept, all peripherals are compatible, and device-to-device transfers can be accomplished at the rate of 2.5
million words per second. All system components and peripherals are linked by the Unibus and power connectors,
and all peripherals are in the basic system address space. Therefore, all instructions applied to data in memory can
also be applied to data in peripheral device registers, enabling peripheral device registers to be manipulated by the
processor as flexibly as memory.
Subsequent paragraphs present a brieffunctional description of basic PDP-11 /40 System components (Figure 1-1 ). A
functional description of all processor options is presented in Chapter 4.
1-1
Revision 1
January 1974

Major Component
*KDl 1-A Processor
*KYl 1-D Programmer's Console
Core Memory
DECwriter
DECwriter
Revision 1
January 1974
Table 1-1
Po~ible PDP-11/ 40 Variations
Possible Variations
No variations in basic processor. However, any of the following internal
proce~r options can be included:
KEl 1-E Extended Instruction Set (EIS)
KEl 1-F Floating Instruction Set (FIS)
KJl 1-A Stack Limit Register
KMl1-A Maintenance Console
KTI 1-D Memory Management
KWI 1-L Line Time Clock
None
MMll-L - SK word core memory, 900 ns cycle time, 350 ns internal
access time
*MFl1-L -MMl 1-L memory plus double system unit backplane,
(space exists for two additional MMl 1-Ls)
MFl 1-LP - Same as MFl 1-L with the addition of two parity bits
making it an 18-bit word memory
MEll-L - MMll-L memory plus backplane, mounting box, and power
supply (complete memory system)
MM 11-S - MMl 1-L memory, plus backplane· (may be used for
e:i_cpansion of memory above 24K)
NOTE
Memory systems compatible with the PDP-11/20 may also
be used in the PDP-11/40. However, these memories must
be housed in their own mounting boxes and powered by
their own power supplies. The memories are:
MMll-E
MMll-F
MMll-FP
MMll-H
MMll-J
4K by 16 bit
4K by 16 bit
4K by 18 bit, with parity
lK by 16 bit
2K by 16 bit
MMll-U -16K word core memory
MFl 1-U - MMI 1-U plus double backplane (can accept one additional
MMII-U)
MMll-UP, MFll-UP -Same as MMll-U and MFll-U but with
addition of parity.
**LA30 -Standard 97-character keyboard. Optional 128-character
keyboard available. (LA30-S is a serial DECwriter and is controlled by a
DLl 1 control; LA30-P is a parallel DECwriter and is controlled by an
LCI I control.) '
1-2

Major Component
Teletype Unit
Input Terminal Control
Power System
Mounting Box
Table 1-1 (Cont)
Possible PDP-11/40 Variations
**33 ASR
33KSR
35 ASR
35KSR
Possible Variations
Each unit is available in 120V or 240V models.
DLI1-A -Teletype, display, or LA30-S control.
DLI1-8 -EIA terminal control.
DLI 1-C -Teletype, display or LA30-S control. The DLI 1-C is simply a
more flexible version of the DLI 1-A. The DLI 1-C features a variable
character code plus crystal and switch selectable baud rates.
DLI 1-D -EIA terminal control. The DLI1-D is simply a more flexible
version of the DLl 1-B. The DLI 1-D features a variable character code
plus crystal and switch selectable baud rates.
DLll-E -Dataset control.
KLli-A
KLll-8
KLII-C
KLll-E
KLII-F
ASR or KSR Teletype controi. Units differ primarily
in baud rates as described in KLl 1 manual.
LClI - LA30-P DECwriter control.
*H742 Power Supply (may be jumpered for either l20V or 230V,
50/60 Hz).
*H744 +SV regulator, 25A (three supplied with basic system)
*H745 - JSV regulator, JOA (one or two)
H754 +20, -5V regulator, used with MFI 1-U/UP
*~61 Power Controller -mounted in bottom rear of cabinet. Two
versions available:
86IB -requires 240 Vac input
86IC -requires 120 Vac input
*BAI 1-FC Mounting Box
*An asterisk indicates that this is the normal configuration shipped with the basic machine, unless otherwise specified by the
customer.
**Either the LA30 DECwriter or the Teletype unit may be used as the basic. PDP-11/40 System input/output device.
1-3
Revision 1
January 1974

1.3.1 Unibus
Olll
ASYNCHRONOUS
LINE INTERFACE
DECWriter
OR
TELETYPE
UNIBUS
KOll-A
CENTRAL
PROCESSOR
KOll-0
PROGRAMMER'S
CONSOLE
POWER SYSTEM
861 POWER CONTROLLER
MF11-L
CORE
MEMORY
(SK)
r-------------------------
PRJ~~~~ )-4- I- - __ - ____ ~7~2_P~W-=~ ~U~~ ________ _t-
H744 REGULATOR (2)
1- - -- - - -- -H"745-R"'EG'UU\T"o"R i2i-- - - - ---
11-1719
Figure 1-1 PDP-11/40 Basic System Block Diagram
The Unibus provides high;speed communication between system components. With bidirectional data, address, and
control lines, the Unibus allows data transfers to occur between all units on the bus, with control of the bus an
important factor in these transfers. The fixed repertoire of bus operations is flexible enough for speed and design
economy, yet provides a fixed specification for interfaces. The asynchronous nature of these operations also eases
design and operation. The repertoire of bus operations is:
DATI, OATIP, DATO, DATOB -data operations
INTR, BR, NPR -control operations
Full 16-bit words or 8-bit bytes of information can be transferred on the bus between the master and slave. The
DATI, DATIP operations transfer data into the master; DATO, DATOB operations transfer data out of the master.
When a device is capable of becoming bus master and requests use of the bus, it is for one of two purposes: to make
a Direct Memory Access (DMA) transfer of data directly to or from another device or memory without processor
intervention, or to INTeRrupt (INTR) program execution and force the processor to branch to a specific address
where an interrupt service routine is located.
Bus control is obtained under a Non-Processor Request (NPR) for the DMA or under a Bus Request (BR) for an
INTR. A device can perform a DMA after acquiring bus control via a BR.
Requests for the bus can be made at any time on the BR and NPR lines. Transfer of bus control from one device to
another is made by the processor priority arbitration logic which grants control of the bus to the device having the
highest priority. NPRs are accorded higher priority than BRs. The NPRs are serviced before and immediately after
Unibus data cycles, in addition to specific times during WAIT or TRAP sequences. The BRs are serviced upon
completion of the current instruction if the requesting priority exceeds that of the processor.
Revision 1
January 1974
14

The PDP-11 /40 processor has a special role in bus control operations as it performs the priority arbitration to select
the next bus master. The processor assumes bus control when no other device has control.
The Unibus originates in the processor with the Internal Unibus and Terminator module (M981), which carries the
Unibus from the processor to the next system unit. All 56 Unibus signals and 17 grounds are carried in this one
module. In addition, a 120-conductor Mylar cable may be used to connect system units in different mounting boxes
or to connect a peripheral device removed from the mounting box.
A complete description of the Unibus, including specifications, is presented in the PDP-11 Peripherals and
Interfacing Handbook.
1.3.2 KDl 1-A Processor
The KDll-A Processor decodes instructions; accepts, modifies, and outputs data; performs arithmetic operations;
and controls allocation of the Unibus among external devices. The processor contains sixteen hardware registers,
eight of which are programmable. Two of the eight programmable registers are specifically used for processor
operation: a program counter (PC) and a stack pointer (SP); the remaining six serve as arithmetic accumulators,
index register, and autoincrement and autodecrement registers.
The eight non-programmable registers are used for storage of a variety of functions including: intermediate address,
source and destination data, a copy of the instruction register, the last interrupt vector address, console operation
data and stack pointer for the KTl 1-D Memory Management Option.
Because of the flexibility of hardware registers, address modes, instruction set, and DMA, PDP-11 /40 programs are
written in directly relocatable codes. The processor also includes a full complement of instructions that manipulate
byte operands and provisions for byte swapping. Either words or bytes may be displayed on the programmer's
console.
Any of the eight programmable internal registers can be used to build last-in, first-out stacks. One register serves as a
processor (or system) stack pointer for automatic stacking. This stack-handling capability permits save and restore of
the program counter and status word in conjunction with subroutine calls and interrupts. This feature allows true
reentrant codes and automatic nesting of subroutines.
The Unibus serves the processor and all peripheral devices; therefore, there must be a priority structure to determine
which device becomes bus master. Generally, a device requests use of the bus for one of two reasons: to make a
non-processor transfer of data directly to or from memory, or to interrupt program execution and force the
processor to branch to an interrupt service routine. An NPR is granted by the processor at the end of bus cycles and
allows device-to-device data transfers without processor intervention. A BR is granted by the processor at the end of
an instruction and allows the device to interrupt the currentprocessor task.
The processor recognizes four levels of hardware BRs, with each major level containing sublevels. Many devices can
be attached on each major level, with the device that is electrically closest to the processor given priority over other
devices on the same priority level. The priority level of the processor itself is programmable within the hardware
levels; therefore, a running program can select the priority level of permissible interrupts.
Additional speed and power are added to the interrupt structure through the use of the PDP-11/40 fully vectored
interrupt scheme. With vectored interrupts;-the device identifies itself, and a unique interrupt service routine is
automatically selected by the processor. This eliminates d(:lvice polling and permits nesting of device service routines.
The device interrupt priority and service routine priority are independent to allow dynamic adjustment of system
behavior in response to real-time conditions.
The Unibus addresses generated by the KDl 1-A Processor are 18-bit direct byte addresses, even though the
PDP-11/40 word length and operational logic is all 16-bit word length. Thus, while the PDP-11/40 word can only
contain address references up to 32K words (64K bytes), the KD11-A Processor can reference addresses up to 128K
words (256K bytes).
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In addition to the word length constraint on basic addressing space, the uppennost 4K words of address space are
reserved for peripheral control, status, and data registers. In the basic PDP-11/40 configuration (without memory
management), all address references to the uppermost 4K words of 16-bit address space (160000-177777) are
converted to full 18-bit references with bits 16 and 17 always set to 1. Thus. a 16-bit reference to address 1732248
is automatically converted to a full 18-bit I/O device register address of 7732248• Consequently, the basic
PDP-11/40 configuration can address up to 28K words of core memory and 4K words of I/O device registers. If core
memory is increased beyond 28K words, the KTI 1-D Memory Management Option must be installed. A brief
description of the KTI l·D Memory Management Option is provided in Chapter 4.
A detailed description of the KDl 1-A Processor is contained in the KDll·A Processor Manual,
DEC-11-HKDAA·A-D.
1.3.3 KYl 1-D Programmer's Console
The KYl l·D Programmer's Console provides the programmer with a direct system interface. The console allows the
user to start, stop, load, modify, examine, step, or continue a program. Console displays indicate processor operation
and the contents of the address and data registers. The console is mounted as the front panel of the BAI 1-FC
Mounting Box and is connected to the processor by two cables.
The programmer's console interacts with the processor through a microprogram control located in the processor.
The console contains only indicators (light emitting diodes), switches, and the contact bounce filtering circuits for
the control switches. Console operation does require certain Unibus operations through the processor: DATO for
DEP and DATI for EXAM. For single-step operation, the processor responds to a Console Bus Request (CBR) whose
priority supersedes all other BR priorities. Note that use of the KMl 1 Maintenance Console option provides a
further display of machine states, and allows single microword stepping.
Console operation, including descriptions of all controls and indicators, is presented in Chapter 3. Detailed
descriptions of console logic circuits are contained in the KD 11 ·A Processor Manual, DEC-11-HKDAA-A-D.
1.3.4 MFll-L Core Memory
The PDP-11/40 contains an MFI 1-L Core Memory. The MFJ 1-L consists of a three-module, SK, 16-bit word,
MMl 1-L memory mounted on a double system unit backplane. The backplane has nine slots of mounting space,
hence two additional MMl 1-L memories may be mounted on the backplar~ as options. With two additional MMl 1-L
memories installed, the memory size is increased to a total of 24K. A detailed description of the memory is
contained in the MFJ 1-L, MFJ 1-LP, MMJ 1-S Core Memory Manual, DEC-11-HMFLA-A-D.
NOTE
PDP-11/40 memory is powered for non-interleaved and
non-overlapped situations. Successive and continuous
operations to alternate 8K memory segments is considered a
prohibited overlapped situation. Interleaving is not allowed
within the MFll-L or MMll-S powered by the basic box.
The core memory uses the Unibus for data transfers to and from the processor and other devices. The core memory,
however, is never bus master; therefore, DATO or DATOB indicates informatio_n transferred out of the master into
the memory. Because of the Unibus structure, the memory can be directly addressed by the processor or any other
master device. Because of double operand instructions, every location iri core can function as a true arithmetic
accumulator.
The memory does not enter the priority structure because it is always a slave device. The master device, however,
can request use of the Unibus and thus the memory through either a BR or a NPR. Because the memory is
completely independent of the processor, any master device can perform direct data transfers with memory without
processor intervention.
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NOTE
The instruction timing specified for the PDP-11/40 applies
only for the memories mounted within the computer
mounting box. These memories employ a special MSYN A
signal between the processor and the memory.
1.3.S Optional Memory Systems
Memories with different ranges of speeds and various physical and electrical characteristics can be freely mixed and
interchanged in a single PDP-11 /40 System. The basic system mounting box can house up to SOK of memory in
addition to the processor and processor options. Additional memory units may be added by using separate mounting
boxes and power supplies up to a total of 124K. Note that the KTI 1-D Memory Management Option is required if
core memory is increased beyond 28K.
Generally, memory systems compatible with the PDP-11/40 fall into two categories: memories designed for use
with the PDP-11/40 and memories designed for use with the PDP-11/20. The PDP-11/40 memories are: MMll-L,
MFll-L, MFl 1-LP, MEl 1-L, and MMl 1-S. The PDP-11/20 memories are: MMl 1-E, MMl 1-F, MMl 1-FP, MMl 1-H,
andMMll-J.
1.3.S.l PDP-11/40 Memories -The following paragraphs provide brief descriptions of the MMll-L, MFll-LP,
MEl1-L, and MMl 1-S memories {the MFl 1-L memory was described in Paragraph 1.3.4). For detailed descriptions
of the MMll-L, MFl 1-LP, and MMll-S memories, refer to the MFJJ-L, MFJJ-LP, MMJJ-S Core Memory Manual,
DEC-11-HMFLA-A-D. For a detailed description of the MEll-Lmemory, refer to theMEJJ-L Core Memory System
Manual, DEC-11-HMELA-B-D.
1.3.5.1.1 MMJJ-L Core Memory -The MMl 1-L Core Memory is a read/write, random access, coincident current,
magnetic core type memory with a cycle time of 900 ns and Unibus access time of 400 ns. The memory is organized
in a 3D, 3-wire planar configuration. It provides 8192 (8K) 16-bit words that are both word and byte addressable.
The memory is organized into 16-bit words, each word containing two 8-bit bytes. The bytes are identified as the
low-order byte {bits. 07-00) and the high-order byte {bits 15-08). Each byte is addressable and has its own address
location. Low bytes are always even numbered and high bytes are odd numbered. Full words are addressed at
even-numbered locations only. When a full word is addressed, the high byte is automatically included. For example,
the 8K memory has 8,192 words or 16,384 bytes; therefore, 16,384 locations are assigned. Address 000000 is the
first low byte, address 000001 is the first high byte, 000002 is the second low byte, 000003 is the second high byte,
etc.
The MMll-L consists of three modules: a GUO Hex module containing the memory control logic and data
channels; a G231 Hex module containing the memory driver logic; and an H214 Quad module containing the
memory core stack.
The memory control logic acknowledges the request of the master device, determines which of the four basic
operations (DATI, DATIP, DATO, or DATOB) is to be performed, and sets up appropriate timing and control
circuits to perform the desired read or write operation. It also contains the inhibit drivers and sense amplifiers as well
as device selector logic to determine if the memory bank has been addressed from the Unibus. The control logic
includes a 16-bit flip-flop storage register. During DATI operations, this register stores the contents of the memory
location being read (destructive read) so that the data can be written back into memory (restored). The register is
also used during DATO and DATOB cycles to store incoming data from the Unibus lines so that it can be written
into core memory.
The memory driver logic includes: address selection logic that decodes the incoming address to determine the core
specifically addressed; the switches and drivers that direct current flow through the magnetic cores to ensure the
proper polarity for the desired function; and the X and Y current generators that provide the necessary current to
change the state of the magnetic cores.
1-7

The ferrite core memory stack consists of 16 memory mats arranged in a planar configuration. Each m .. t contains
8192 ferrite cores arranged in a 128 X 64 matrix. Each mat represents a single bit position of a word. Each ferrite
core can assume a stable magnetic state correspondin~ to either a binary 1 or binary 0. Even if power is removed
from the core, the core retains its state until changed by appropriate control signals.
1.3 5.1.2 MFll·LP Core Memory -The MFll-LP is an 8K, 18-bit word memory consisting of four modules
mounted on a double system unit backplane. Three modules perform identical functions as those in the MMll-L
memory while the fourth module contains parity control circuitry. The two additional bits (bits 16 and 17) provide
parity bits for the low and high bytes of the data word respectively. The MFll-LP may be expanded to 24K
capacity by installing two additional 8K segments (three modules each) on the double system unit backplane.
Note that while the 8K MFll-LP memory contains four modules, the 24K unit only requires 9 module slots (one
double system unit). This is possible because only one parity controller module is needed for 24K. The parity
controller module is a dual-height module and is installed in the two normally vacant slot/sections next to the
memory stack module.
1.3.5.1.3 MEll·L Core Memory -The MEll-L is a eomplete memory system consisting of an MMll-L Core
Memory and associated backplane housed in its own mounting box which contains an integral power supply. This
power supply and mounting box can accommodate up to three MMl 1-L Core Memories. In effect, the MEl 1-L can
be expanded up to 24K in 8K increments. These memories should not be interleaved due to power supply
limitations.
The system mounting box is 5-1/4 in. high, 19 in. wide, and 20 in. deep and is designed for mounting in a standard
19-in. cabinet. Rack-mountable slides are included but the box can be used as a stand-alone unit, if desired. In
addition to holding the core memory, backplane, and power supply, the box contains all cables necessary for
providing power and for interfacing the units of the MEl1-L. It also provides for connection to the Unibus. The rear
of the box contains cable clamps, a line cord for input power, a cooling fan for the memory modules and power
supply, and a power control circuit breaker.
The memory system power supply converts single-phase 115 or 230 Vac line voltage to the two regulated de voltages
required by the memory system: +5V for the logic and-15V for the core memory. Both outputs are overvoltage
and overcurrent protected. The power supply also provides line power to the mounting box cooling fan and the BUS
AC LO and BUS DC LO signals which are sent to the Unibus in the event of a power failure.
The power supply consists of a power control, a power chassis assembly, and a de regulator along with associated ac
and de cables. The power control contains a thermal circuit breaker w)iich protects against input and overload and is
reset by depressing a button on the rear of the mounting box. A thermostat in the regulator opens one side of the
primary circuit and deenergizes the power supply if the temperature rises above 100° C. It is automatically reset
when the temperature reaches 63° C.
1.3.5.1.4 MMll·S Core Memory -The MMll-S Core Memory is an MMll-L memory on a single system unit
backplane. The prime physical difference between the MMl 1-S and the MFl 1-L is that the MMl 1-S is an 8K single
system unit while the MFll-L is a 24K capacity double system unit. The MMll-S should not be interleaved in the
PDP-11/40.
1.3.5.2 PDP-11/20 Memories -Brief descriptions of the PDP-11 /20 memories are provided below. These memories
may be used with the PDP-11 /40 System provided they are powered by H720 Power Supplies and are mounted in a
BAll-ES Mounting Box. The MMl 1-E and MMll-F memories are expandable to 28K with interleaving of 4K
segments permitted.
MMll-E -4K by 16 bit, 1.2 µs access time
MMll-F - 4K by.16 bit, 950 ns access time
MMll-FP -an MMll-F with parity option included
MMll-H - lK by 16 bit, 950 ns access time
MMll-J -2K by 16 bit, 950 ns access time
1-8

1.3.S.3 MFl1-U/UP Core Memory -The MFl 1-U/UP Memory is a read/write, random access coincident current,
magnetic core type with a maximum cycle time of 980 ns and a maximum access time of 425 ns. It is organized in a
3D, 3-wire planar configuration. Word length is 16 bits and the memory consists of 16,384 (16K) words.
The MFl 1-U provides 16,384 (16K) 16-bit words; the MFl I-UP provides the same number of words but includes
parity.
The memory can be interleaved in 32K increments for faster operation. Interleaving causes consecutive bus addresses
to be located within alternate J6K memory blocks. ,
The chart below shows the various option descriptions associated with the I6K memory.
MFI 1-U
MMl 1-U Module Set
MFll-UP
MM 11-UP Module Set
M8293 161( Unibus Timing Module
G114 Sense Inhibit Module
G235 X-Y Driver
H217D Stack Module (16 bits)
7009295 Backplane Assembly
Includes all modules listed in MFll-U but does not include backplane
assembly
M8293 16K Unibus Timing Module
G114 Sense Inhibit Module
G235 X-Y Driver Module
H217C Stack Module (I 8 bits including parity)
7009295 Backplane Assembly
M7259 Parity Control Module
Includes all modules listed in MFl 1-UP except M7259 ·Parity Control
Mod.ule and does not include backplane assembly
Ifa user has a 16K memory system and wishes to add another 16K, he merely specifies the appropriate module set
since the existing backplane assembly can hold 32K of memory.
The MFI 1-U/UP Core Me~~ry is explained in detail in the MFJJ-U/UP Core Memory System Maintenance Manual,
DEC-11-HMFMA-A-D.
1.3.6 LA30 DECwriter
The LA30 DECwriter is a dot matrix impact printer and keyboard for use as a hard copy 1/0terminal. It is capable
of printing a set of 64 ASCII characters at speeds up to 30 characters per second on a sprocket-fed 9- 7 /8 in.
continuous form. Data entry is from a keyboard capable of generating either 97 or 128 characters.
The LA30 is available in two versions: parallel (LA30-P) and serial (LA30-S). The serial version is normally used
with the PDP-11/40 Systemin that it is interfaced to the Unibus via the DLl 1 Asynchronous Line Interface. The
DLl1 is basic to the PDP-11/40 System.
The LA30 DECwriter is covered in Chapter 3 and a detailed description is contained in the LA30 DECwriter
Maintenance Manual, DEC-OO-LA30-DC.
1-9
Revision 1
January 1974