Digital Equipment Alpha 21164PC Quick user guide

Digital Equipment Corporation
Maynard, Massachusetts
http://www.digital.com/semiconductor
Digital Semiconductor
Alpha 21164PC Microprocessor
Hardware Reference Manual
Order Number: EC–R2W0A–TE
Revision/Update Information: This is a preliminary document.
Preliminary

September 1997
While DIGITAL believes the information included in this publication is correct as of the date of publication, it is
subject to change without notice.
Digital Equipment Corporation makes no representations that the use of its products in the manner described in this
publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication
imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.
©Digital Equipment Corporation 1997. All rights reserved.
Printed in U.S.A.
DIGITAL, Digital Semiconductor, OpenVMS, VAX, the AlphaGeneration design mark, and the DIGITAL logo are
trademarks of Digital Equipment Corporation.
Digital Semiconductor is a Digital Equipment Corporation business.
29 September 1997 – Subject to Change
GRAFOIL is a registered trademark of Union Carbide Corporation.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Windows NT is a trademark of Microsoft Corporation.
All other trademarks and registered trademarks are the property of their respective owners.

29 September 1997 – Subject to Change iii
Contents
Preface
1 Introduction
1.1 The Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.3 Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 21164PC Microprocessor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2 Internal Architecture
2.1 21164PC Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 Instruction Fetch/Decode Unit and Branch Unit. . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.1.1 Instruction Decode and Issue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.1.2 Instruction Prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.1.3 Branch Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.1.4 Instruction Translation Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.1.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.1.2 Integer Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.1.3 Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.1.4 Memory Address Translation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.1.4.1 Data Translation Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.1.4.2 Load Instruction and the Miss Address File . . . . . . . . . . . . . . . . . . . . . . 2-11
2.1.4.3 Dcache Control and Store Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.1.4.4 Write Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.1.5 Cache Control and Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.1.6 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.1.6.1 Data Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.1.6.2 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.1.6.3 External Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.1.7 Serial Read-Only Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

iv 29 September 1997 – Subject to Change
2.2 Pipeline Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.1 Pipeline Stages and Instruction Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.2.2 Aborts and Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.2.3 Nonissue Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3 Scheduling and Issuing Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.1 Instruction Class Definition and Instruction Slotting. . . . . . . . . . . . . . . . . . . . 2-19
2.3.2 Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.3 Instruction Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.3.1 Producer–Producer Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.4 Issue Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.4 Replay Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.5 Miss Address File and Load-Merging Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.5.1 Merging Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.5.1.1 Cacheable Space Load-Merge Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.5.1.2 Noncacheable Space Load-Merge Rules. . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.5.2 Read Requests to the CBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.5.3 MAF Entries and MAF Full Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.5.4 Fill Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.6 MTU Store Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.7 Write Buffer and the WMB Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.7.1 The Write Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.7.2 The Write Memory Barrier (WMB) Instruction . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.7.3 Entry-Pointer Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.7.4 Write Buffer Entry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.7.5 Ordering of Noncacheable Space Write Instructions. . . . . . . . . . . . . . . . . . . 2-36
2.8 Performance Measurement Support–Performance Counters . . . . . . . . . . . . . . . 2-36
2.8.1 CBU Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.9 Floating-Point Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.10 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
3 Hardware Interface
3.1 21164PC Microprocessor Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 21164PC Signal Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
4 Clocks, Cache, and External Interface
4.1 Introduction to the External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1.1 Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.2 Bcache Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.2.1 Bcache Interface Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.2.2 Pipelined Bcache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.2.3 Write Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

29 September 1997 – Subject to Change v
4.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.1 CPU Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.2.2 System Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.3 Delayed System Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.3 Physical Address Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.1 Physical Address Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.2 Data Wrapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.3.3 Noncached Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.3.4 Noncached Write Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4 Bcache Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4.1 Bcache Victim Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.5 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.5.1 Flush Cache Coherency Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.6 21164PC-to-Bcache Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.6.1 Synchronous Burst-Mode Cache Support. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.6.2 Bcache Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.6.3 Bcache Private Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.6.4 Bcache st_clk Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.6.5 Bcache Private Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.6.5.1 Bcache Private Write-Probe Operation . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.6.5.2 Bcache Private Data-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.6.5.3 Interleaving Write-Probes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4.6.6 Selecting Bcache Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
4.7 21164PC-Initiated System Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
4.7.1 READ MISS Clean - No Victim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.7.2 FILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.7.3 READ MISS with Victim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
4.7.4 WRITE BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.8 System-Initiated Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4.8.1 Sending Commands to the 21164PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4.8.2 Write Invalidate Protocol Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
4.8.2.1 21164PC Responses to Flush-Based Protocol Commands. . . . . . . . . . 4-41
4.8.2.2 FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
4.8.2.3 INVALIDATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.8.2.4 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.9 Data Bus and Command/Address Bus Contention. . . . . . . . . . . . . . . . . . . . . . . . 4-45
4.9.1 Command/Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
4.9.2 Read/Write Spacing—Data Bus Contention . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
4.9.3 Using idle_bc_h and fill_h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
4.9.4 Using data_bus_req_h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
4.9.5 Tristate Overlap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.9.5.1 Private READ or WRITE to FILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.9.5.2 System READ to FILL (System WRITE) Spacing. . . . . . . . . . . . . . . . . . 4-49
4.9.5.3 FILL to Private READ or WRITE Operation . . . . . . . . . . . . . . . . . . . . . . 4-50
4.10 21164PC Interface Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
4.10.1 Fill Operations After Other Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
4.10.2 Command Acknowledge for WRITE BLOCK Commands . . . . . . . . . . . . . . . 4-51

vi 29 September 1997 – Subject to Change
4.11 21164PC/System Race Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
4.11.1 Rules for 21164PC and System Use of External Interface . . . . . . . . . . . . . . 4-51
4.11.2 READ MISS with Victim Aborted by FILL Example. . . . . . . . . . . . . . . . . . . . 4-53
4.11.3 idle_bc_h and cack_h Race Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
4.11.4 READ MISS with idle_bc_h Asserted Example. . . . . . . . . . . . . . . . . . . . . . . 4-55
4.11.5 READ MISS with Victim Aborted by System Command Example. . . . . . . . . 4-56
4.11.6 Bcache Hit Under READ MISS Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4.12 Data Integrity and Bcache Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4.12.1 Data Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4.12.2 Bcache Tag Data Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
4.12.3 Fill Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
4.13 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
4.13.1 Interrupt Signals During Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
4.13.2 Interrupt Signals During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
4.13.3 Interrupt Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
5 Internal Processor Registers
5.1 Instruction Fetch/Decode Unit and Branch Unit (IDU) IPRs . . . . . . . . . . . . . . . . . 5-5
5.1.1 Istream Translation Buffer Tag (ITB_TAG) Register (101) . . . . . . . . . . . . . . 5-5
5.1.2 Instruction Translation Buffer Page Table Entry (ITB_PTE) Register (102) . 5-5
5.1.3 Instruction Translation Buffer Address Space Number (ITB_ASN)
Register (103) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.4 Instruction Translation Buffer Page Table Entry Temporary
(ITB_PTE_TEMP) Register (104) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.5 Instruction Translation Buffer Invalidate All Process (ITB_IAP)
Register (106) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.6 Instruction Translation Buffer Invalidate All (ITB_IA) Register (105) . . . . . . . 5-8
5.1.7 Instruction Translation Buffer IS (ITB_IS) Register (107) . . . . . . . . . . . . . . . 5-8
5.1.8 Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (112) . . 5-9
5.1.9 Virtual Page Table Base (IVPTBR) Register (113) . . . . . . . . . . . . . . . . . . . . 5-10
5.1.10 Icache Parity Error Status (ICPERR_STAT) Register (11A) . . . . . . . . . . . . . 5-11
5.1.11 Icache Flush Control (IC_FLUSH_CTL) Register (119). . . . . . . . . . . . . . . . . 5-11
5.1.12 Exception Address (EXC_ADDR) Register (10B) . . . . . . . . . . . . . . . . . . . . . 5-12
5.1.13 Exception Summary (EXC_SUM) Register (10C) . . . . . . . . . . . . . . . . . . . . . 5-12
5.1.14 Exception Mask (EXC_MASK) Register (10D) . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.1.15 PAL Base Address (PAL_BASE) Register (10E). . . . . . . . . . . . . . . . . . . . . . 5-15
5.1.16 IDU Current Mode (ICM) Register (10F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.1.17 IDU Control and Status (ICSR) Register (118) . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.1.18 Interrupt Priority Level (IPLR) Register (110). . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.1.19 Interrupt ID (INTID) Register (111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.1.20 Asynchronous System Trap Request (ASTRR) Register (109). . . . . . . . . . . 5-20
5.1.21 Asynchronous System Trap Enable (ASTER) Register (10A). . . . . . . . . . . . 5-20
5.1.22 Software Interrupt Request (SIRR) Register (108) . . . . . . . . . . . . . . . . . . . . 5-21
5.1.23 Hardware Interrupt Clear (HWINT_CLR) Register (115). . . . . . . . . . . . . . . . 5-22

29 September 1997 – Subject to Change vii
5.1.24 Interrupt Summary (ISR) Register (100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.1.25 Serial Line Transmit (SL_XMIT) Register (116). . . . . . . . . . . . . . . . . . . . . . . 5-25
5.1.26 Serial Line Receive (SL_RCV) Register (117). . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.1.27 Performance Counter (PMCTR) Register (11C) . . . . . . . . . . . . . . . . . . . . . . 5-27
5.2 Memory Address Translation Unit (MTU) IPRs. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.1 Dstream Translation Buffer Address Space Number (DTB_ASN)
Register (200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.2 Dstream Translation Buffer Current Mode (DTB_CM) Register (201). . . . . . 5-31
5.2.3 Dstream Translation Buffer Tag (DTB_TAG) Register (202). . . . . . . . . . . . . 5-32
5.2.4 Dstream Translation Buffer Page Table Entry (DTB_PTE) Register (203) . . 5-32
5.2.5 Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP)
Register (204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5.2.6 Dstream Memory Management Fault Status (MM_STAT) Register (205). . . 5-35
5.2.7 Faulting Virtual Address (VA) Register (206). . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5.2.8 Formatted Virtual Address (VA_FORM) Register (207). . . . . . . . . . . . . . . . . 5-37
5.2.9 MTU Virtual Page Table Base (MVPTBR) Register (208). . . . . . . . . . . . . . . 5-38
5.2.10 Dcache Parity Error Status (DC_PERR_STAT) Register (212). . . . . . . . . . . 5-39
5.2.11 Dstream Translation Buffer Invalidate All Process (DTB_IAP)
Register (209) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5.2.12 Dstream Translation Buffer Invalidate All (DTB_IA) Register (20A) . . . . . . . 5-40
5.2.13 Dstream Translation Buffer Invalidate Single (DTB_IS) Register (20B) . . . . 5-41
5.2.14 MTU Control (MCSR) Register (20F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
5.2.15 Dcache Mode (DC_MODE) Register (216) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.2.16 Miss Address File Mode (MAF_MODE) Register (217). . . . . . . . . . . . . . . . . 5-46
5.2.17 Dcache Flush (DC_FLUSH) Register (210). . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.2.18 Alternate Mode (ALT_MODE) Register (20C) . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.2.19 Cycle Counter (CC) Register (20D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
5.2.20 Cycle Counter Control (CC_CTL) Register (20E) . . . . . . . . . . . . . . . . . . . . . 5-51
5.2.21 Dcache Test Tag Control (DC_TEST_CTL) Register (213). . . . . . . . . . . . . . 5-52
5.2.22 Dcache Test Tag (DC_TEST_TAG) Register (214). . . . . . . . . . . . . . . . . . . . 5-54
5.2.23 Dcache Test Tag Temporary (DC_TEST_TAG_TEMP) Register (215) . . . . 5-56
5.3 External Interface Control (CBU) IPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58
5.3.1 CBU Configuration (CBOX_CONFIG) Register (FF FFF0 0008). . . . . . . . . . 5-59
5.3.2 CBU Address (CBOX_ADDR) Register (FF FFF0 0088). . . . . . . . . . . . . . . . 5-62
5.3.3 CBU Status (CBOX_STATUS) Register (FF FFF0 0108) . . . . . . . . . . . . . . . 5-63
5.3.4 CBU Configuration #2 (CBOX_CONFIG2) Register (FF FFF0 0188) . . . . . . 5-65
5.4 PALcode Storage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
5.5 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
5.5.1 CBU IPR PALcode Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
5.5.2 PALcode Restrictions—Instruction Definitions. . . . . . . . . . . . . . . . . . . . . . . . 5-69
6 Privileged Architecture Library Code
6.1 PALcode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 PALmode Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

viii 29 September 1997 – Subject to Change
6.3 Invoking PALcode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.4 PALcode Entry Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4.1 CALL_PAL Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4.2 PALcode Trap Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.5 Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.6 21164PC Implementation of the Architecturally Reserved Opcodes . . . . . . . . . . 6-7
6.6.1 HW_LD Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.6.2 HW_ST Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.6.3 HW_REI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.4 HW_MFPR and HW_MTPR Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
7 Initialization and Configuration
7.1 Input Signals sys_reset_l and dc_ok_h and Booting . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Pin State with dc_ok_h Not Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2 sysclk Ratio and Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.3 Built-In Self-Test (BiSt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4 Serial Read-Only Memory Interface Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4.1 Serial Instruction Cache Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.5 Serial Terminal Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.6 Cache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.6.1 Icache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.6.2 Flushing Dirty Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.7 External Interface Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.8 Internal Processor Register Reset State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.9 Timeout Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.10 IEEE 1149.1 Test Port Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
8 Error Detection and Error Handling
8.1 Error Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Icache Data or Tag Parity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 Dcache Data Parity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3 Dcache Tag Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.4 Istream Data Parity Errors (Bcache or Memory) . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.5 Dstream Data Parity Errors (Bcache or Memory) . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.6 Bcache Tag Parity Errors—Istream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.7 Bcache Tag Parity Errors—Dstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.8 System Read Operations of the Bcache . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.9 Fill Timeout (FILL_ERROR_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.10 System Machine Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.11 IDU Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2 MCHK Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.3 MCK_INTERRUPT Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

29 September 1997 – Subject to Change ix
9 Electrical Data
9.1 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.1 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 Input Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.3 Output Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.1 Input Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.2 Clock Termination and Impedance Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.3 AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4.1 Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4.2 Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.2.1 Backup Cache Loop Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.2.2 sys_clk-Based Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.3 Timing—Additional Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.4.4 Timing of Test Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.4.4.1 Icache BiSt Operation Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.4.4.2 Automatic SROM Load Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9.4.5 Clock Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.4.5.1 Normal (1× Clock) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.4.5.2 Clock Test Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.4.6 IEEE 1149.1 (JTAG) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.5 Power Supply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.5.1 Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.5.1.1 Vdd Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.5.1.2 Vddi Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.5.2 Power Supply Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
10 Thermal Management
10.1 Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Heat-Sink Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Thermal Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
11 Mechanical Packaging Information
11.1 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Signal Descriptions and Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.1 Signal Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

x 29 September 1997 – Subject to Change
12 Testability and Diagnostics
12.1 Test Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.1 IEEE 1149.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.2 Test Status Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.3 Boundary-Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
A Alpha Instruction Set
A.1 Alpha Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1.1 Opcodes Reserved for DIGITAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A.1.2 Opcodes Reserved for PALcode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A.2 IEEE Floating-Point Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A.3 VAX Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.4 Opcode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.5 Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
A.6 21164PC Microprocessor IEEE Floating-Point Conformance. . . . . . . . . . . . . . . . A-15
B 21164PC Microprocessor Specifications
C Serial Icache Load Predecode Values
D Errata Sheet
E Support, Products, and Documentation
Glossary
Index

29 September 1997 – Subject to Change xi
Figures
2–1 21164PC Microprocessor Block/Pipe Flow Diagram . . . . . . . . . . . . . . . . . . . . . . 2-2
2–2 Instruction Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2–3 Floating-Point Control Register (FPCR) Format. . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2–4 Typical Uniprocessor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
3–1 21164PC Microprocessor Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4–1 21164PC System/Bcache Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4–2 Merits of a Multiprobes In Flight – Pipelined Cache . . . . . . . . . . . . . . . . . . . . . . . 4-5
4–3 Tag/Data Store Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4–4 Clock Signals and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4–5 21164PC Uniprocessor Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4–6 Flush-Based Protocol 21164PC States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4–7 Flush-Based Protocol System/Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4–8 SSRAM/Bcache Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4–9 Bcache Private Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4–10 Bcache Private Write Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4–11 Bcache Private Data – Write Hit Clean. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
4–12 Bcache Private Data – Write Hit Dirty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4–13 Bcache Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4–14 READ MISS Clean – Bcache Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4–15 READ MISS with Victim Timing Diagram, Pipelined Mode. . . . . . . . . . . . . . . . . . 4-35
4–16 READ MISS with Victim Timing Diagram, Flow-Through Mode . . . . . . . . . . . . . . 4-36
4–17 WRITE BLOCK Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4–18 Algorithm for System Sending Commands to the 21164PC. . . . . . . . . . . . . . . . . 4-39
4–19 FLUSH Timing Diagram (Bcache Hit) Flow-Through SSRAM . . . . . . . . . . . . . . . 4-42
4–20 INVALIDATE Timing Diagram – Bcache Hit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4–21 READ Timing Diagram (Bcache Hit) Flow-Through SSRAM . . . . . . . . . . . . . . . . 4-44
4–22 Driving the Command/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
4–23 Using data_bus_req_h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4–24 System READ to FILL Spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
4–25 FILL to Private READ or WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
4–26 READ MISS with Victim Aborted by FILL Example. . . . . . . . . . . . . . . . . . . . . . . . 4-53
4–27 idle_bc_h and cack_h Race Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
4–28 READ MISS with idle_bc_h Asserted Example . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
4–29 READ MISS with Victim Abort Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
4–30 Bcache Hit Under READ MISS Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4–31 21164PC Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
5–1 Istream Translation Buffer Tag (ITB_TAG) Register. . . . . . . . . . . . . . . . . . . . . . . 5-5
5–2 Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Write Format 5-6
5–3 Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Read Format 5-6
5–4 Instruction Translation Buffer Address Space Number (ITB_ASN) Register . . . . 5-7
5–5 Instruction Translation Buffer IS (ITB_IS) Register. . . . . . . . . . . . . . . . . . . . . . . . 5-8
5–6 Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=0) 5-9
5–7 Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=1) 5-9
5–8 Virtual Page Table Base (IVPTBR) Register (NT_Mode=0). . . . . . . . . . . . . . . . . 5-10

xii 29 September 1997 – Subject to Change
5–9 Virtual Page Table Base (IVPTBR) Register (NT_Mode=1). . . . . . . . . . . . . . . . . 5-10
5–10 Icache Parity Error Status (ICPERR_STAT) Register. . . . . . . . . . . . . . . . . . . . . . 5-11
5–11 Exception Address (EXC_ADDR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5–12 Exception Summary (EXC_SUM) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5–13 Exception Mask (EXC_MASK) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5–14 PAL Base Address (PAL_BASE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5–15 IDU Current Mode (ICM) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5–16 IDU Control and Status (ICSR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5–17 Interrupt Priority Level (IPLR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5–18 Interrupt ID (INTID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5–19 Asynchronous System Trap Request (ASTRR) Register . . . . . . . . . . . . . . . . . . . 5-20
5–20 Asynchronous System Trap Enable (ASTER) Register . . . . . . . . . . . . . . . . . . . . 5-20
5–21 Software Interrupt Request (SIRR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5–22 Hardware Interrupt Clear (HWINT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5–23 Interrupt Summary (ISR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5–24 Serial Line Transmit (SL_XMIT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5–25 Serial Line Receive (SL_RCV) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5–26 Performance Counter (PMCTR) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5–27 Dstream Translation Buffer Address Space Number (DTB_ASN) Register . . . . . 5-31
5–28 Dstream Translation Buffer Current Mode (DTB_CM) Register . . . . . . . . . . . . . . 5-31
5–29 Dstream Translation Buffer Tag (DTB_TAG) Register . . . . . . . . . . . . . . . . . . . . . 5-32
5–30 Dstream Translation Buffer Page Table Entry (DTB_PTE) Register—Write Format 5-33
5–31 Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5–32 Dstream Memory Management Fault Status (MM_STAT) Register . . . . . . . . . . . 5-35
5–33 Faulting Virtual Address (VA) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5–34 Formatted Virtual Address (VA_FORM) Register (NT_Mode=1) . . . . . . . . . . . . . 5-37
5–35 Formatted Virtual Address (VA_FORM) Register (NT_Mode=0) . . . . . . . . . . . . . 5-37
5–36 MTU Virtual Page Table Base (MVPTBR) Register . . . . . . . . . . . . . . . . . . . . . . . 5-38
5–37 Dcache Parity Error Status (DC_PERR_STAT) Register . . . . . . . . . . . . . . . . . . . 5-39
5–38 Dstream Translation Buffer Invalidate Single (DTB_IS) Register . . . . . . . . . . . . . 5-41
5–39 MTU Control (MCSR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
5–40 Dcache Mode (DC_MODE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5–41 Miss Address File Mode (MAF_MODE) Register . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5–42 Alternate Mode (ALT_MODE) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5–43 Cycle Counter (CC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
5–44 Cycle Counter Control (CC_CTL) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
5–45 Dcache Test Tag Control (DC_TEST_CTL) Register. . . . . . . . . . . . . . . . . . . . . . 5-52
5–46 Dcache Test Tag (DC_TEST_TAG) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5–47 Dcache Test Tag Temporary (DC_TEST_TAG_TEMP) Register. . . . . . . . . . . . . 5-56
5–48 CBU Configuration (CBOX_CONFIG) Register . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5–49 CBU Address (CBOX_ADDR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
5–50 CBU Status (CBOX_STATUS) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
5–51 CBU Configuration #2 (CBOX_CONFIG2) Register. . . . . . . . . . . . . . . . . . . . . . . 5-65
6–1 HW_LD Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6–2 HW_ST Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6–3 HW_REI Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

29 September 1997 – Subject to Change xiii
6–4 HW_MFPR and HW_MTPR Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
9–1 osc_clk_in_h,l Input Network and Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9–2 Impedance vs Clock Input Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9–3 Input/Output Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9–4 Bcache Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9–5 sys_clk System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9–6 BiSt Timing Event —Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9–7 SROM Load Timing Event—Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9–8 Serial ROM Load Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
10–1 Heat Sink 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
11–1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11–2 21164PC Top View (Pin Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11–3 21164PC Bottom View (Pin Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
12–1 IEEE 1149.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12–2 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

xiv 29 September 1997 – Subject to Change
Tables
2–1 Effect of Branching Instructions on the Branch—Prediction Stack . . . . . . . . . . . . 2-6
2–2 Pipeline Examples—All Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2–3 Pipeline Examples—Integer Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2–4 Pipeline Examples—Floating Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2–5 Pipeline Examples—Load (Dcache Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2–6 Pipeline Examples—Load (Dcache Miss). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2–7 Pipeline Examples—Store (Dcache Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2–8 Instruction Classes and Slotting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2–9 Instruction Latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2–10 Floating-Point Control Register Bit Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
3–1 21164PC Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3–2 21164PC Signal Descriptions by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
4–1 CPU Clock Generation Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4–2 System Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4–3 System Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4–4 Physical Memory Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4–5 Bcache States for Cache Coherency Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4–6 Bcache Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4–7 Bcache Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
4–8 21164PC-Initiated Interface Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4–9 System-Initiated Interface Commands (Write Invalidate Protocol) . . . . . . . . . . . . 4-40
4–10 21164PC Responses to Flush-Based Protocol Commands. . . . . . . . . . . . . . . . . 4-41
4–11 Interrupt Priority Level Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
5–1 IDU, MTU, Dcache, and PALtemp IPR Encodings . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5–2 Granularity Hint Bits in ITB_PTE_TEMP Read Format. . . . . . . . . . . . . . . . . . . . . 5-7
5–3 Icache Parity Error Status Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5–4 Exception Summary Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5–5 IDU Control and Status Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5–6 Software Interrupt Request Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5–7 Hardware Interrupt Clear Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5–8 Interrupt Summary Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5–9 Serial Line Transmit Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5–10 Serial Line Receive Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5–11 Performance Counter Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5–12 PMCTR Counter Select Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5–13 Measurement Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5–14 Dstream Memory Management Fault Status Register Fields . . . . . . . . . . . . . . . . 5-35
5–15 Formatted Virtual Address Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5–16 Dcache Parity Error Status Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5–17 MTU Control Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5–18 Dcache Mode Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5–19 Miss Address File Mode Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
5–20 Alternate Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5–21 Cycle Counter Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

29 September 1997 – Subject to Change xv
5–22 Dcache Test Tag Control Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5–23 Dcache Test Tag Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
5–24 Dcache Test Tag Temporary Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
5–25 CBU Internal Processor Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58
5–26 CBU Configuration Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5–27 CBU Address Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
5–28 CBU Status Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
5–29 CBU Configuration #2 Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
5–30 CBU IPR PALcode Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
5–31 PALcode Restrictions Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69
6–1 PALcode Trap Entry Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6–2 Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6–3 Opcodes Reserved for PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6–4 HW_LD Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6–5 HW_ST Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6–6 HW_REI Format Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6–7 HW_MFPR and HW_MTPR Format Description . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
7–1 21164PC Signal Pin Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7–2 Internal Processor Register Reset State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
9–1 21164PC Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9–2 Operating Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9–3 CMOS DC Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9–4 Input Clock Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9–5 Bcache Loop Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9–6 Normal Output Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9–7 Big Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9–8 21164PC System Clock Output Timing (sysclk=T
ø
) . . . . . . . . . . . . . . . . . . . . . . . 9-13
9–9 Input Timing for sys_clk_out-Based Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9–10 Output Timing for sys_clk_out-Based Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9–11 Bcache Control Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9–12 BiSt Timing for Some System Clock Ratios, Port Mode=Normal (System Cycles) 9-18
9–13 BiSt Timing for Some System Clock Ratios, Port Mode=Normal (CPU Cycles). . 9-18
9–14 SROM Load Timing for Some System Clock Ratios (System Cycles) . . . . . . . . . 9-19
9–15 SROM Load Timing for Some System Clock Ratios (CPU Cycles) . . . . . . . . . . . 9-19
9–16 Clock Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9–17 IEEE 1149.1 Circuit Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
10–1 Θ
c
a at Various Airflows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10–2 Maximum T
a
at Various Airflows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
11–1 Alphabetic Signal Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11–2 Voltage Reference, Power, and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
12–1 21164PC Test Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12–2 Compliance Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12–3 Instruction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12–4 Boundary-Scan Register Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
A–1 Instruction Format and Opcode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A–2 Architecture Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A–3 Opcodes Reserved for DIGITAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

xvi 29 September 1997 – Subject to Change
A–4 Opcodes Reserved for PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A–5 IEEE Floating-Point Instruction Function Codes. . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A–6 VAX Floating-Point Instruction Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A–7 Opcode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A–8 Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
B–1 21164PC Microprocessor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
D–1 Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

29 September 1997 – Subject To Change xvii
Preface
This manual provides information about the architecture, internal design, external
interface, and specifications of the Digital Semiconductor Alpha 21164PC micropro-
cessor (referred to as the 21164PC) and its associated software.
Audience
This reference manual is for system designers and programmers who use the
21164PC.
Manual Organization
This manual includes the following chapters and appendixes, and an index.
•Chapter 1, Introduction, introduces the 21164PC and provides an overview of
the Alpha architecture.
•Chapter 2, Internal Architecture, describes the major hardware functions and the
internal chip architecture. It describes performance measurement facilities, cod-
ing rules, and design examples.
•Chapter 3, Hardware Interface, lists and describes the external hardware inter-
face signals.
•Chapter 4, Clocks, Cache, and External Interface, describes the external bus
functions and transactions, lists bus commands, and describes the clock func-
tions.
•Chapter 5, Internal Processor Registers, lists and describes the 21164PC internal
processor register set.
•Chapter 6, Privileged Architecture Library Code, describes the privileged archi-
tecture library code (PALcode).

xviii 29 September 1997 – Subject To Change
•Chapter 7, Initialization and Configuration, describes the initialization and con-
figuration sequence.
•Chapter 8, Error Detection and Error Handling, describes error detection and
error handling.
•Chapter 9, Electrical Data, provides electrical data and describes signal integrity
issues.
•Chapter 10, Thermal Management, provides information about thermal manage-
ment.
•Chapter 11, Mechanical Packaging Information, provides mechanical data and
packaging information, including signal pin lists.
•Chapter 12, Testability and Diagnostics, describes chip and system testability
features.
•Appendix A, Alpha Instruction Set, summarizes the Alpha instruction set.
•Appendix B, 21164PC Microprocessor Specifications, summarizes the
21164PC specifications.
•Appendix C, Serial Icache Load Predecode Values, provides a C code example
that calculates the predecode values of a serial Icache load.
•Appendix D, Errata Sheet, lists changes and revisions to this manual.
•Appendix E, Support, Products, and Documentation, provides phone numbers
for support and lists related DIGITAL and third-party publications with order
information.
•The Glossary lists and defines terms associated with the 21164PC.
The companion volume to this manual, the Alpha AXP Architecture Reference Man-
ual, contains the Alpha architecture information.

29 September 1997 – Subject To Change xix
Conventions
This section defines product-specific terminology, abbreviations, and other conven-
tions used throughout this manual.
Abbreviations
•Binary Multiples
The abbreviations K, M, and G (kilo, mega, and giga) represent binary multiples
and have the following values.
For example:
•Register Access
The abbreviations used to indicate the type of access to register fields and bits
have the following definitions:
IGN — Ignore
Register bits specified as IGN are ignored when written and are UNPRE-
DICTABLE when read if not otherwise specified.
MBZ — Must Be Zero
Software must never place a nonzero value in bits and fields specified as
MBZ. Reads return unpredictable values. Such fields are reserved for future
use.
RAO — Read As One
Register bits specified as RAO return a 1 when read.
RAZ — Read As Zero
Register bits specified as RAZ return a 0 when read.
K=2
10 (1024)
M=2
20 (1,048,576)
G=2
30 (1,073,741,824)
2KB = 2 kilobytes =2×210 bytes
4MB = 4 megabytes =4×220 bytes
8GB = 8 gigabytes =8×230 bytes

xx 29 September 1997 – Subject To Change
RC — Read To Clear
A register field specified as RC is written by hardware and remains
unchanged until read. The value may be read by software, at which point,
hardware may write a new value into the field.
RES — Reserved
Bits and fields specified as RES are reserved by Digital Semiconductor and
should not be used; however, zeros can be written to reserved fields that can-
not be masked.
RO — Read Only
Bits and fields specified as RO can be read and are ignored (not written) on
writes.
RW — Read/Write
Bits and fields specified as RW can be read and written.
W0C — Write Zero to Clear
Bits and fields specified as W0C can be read. Writing a zero clears these bits
for the duration of the write; writing a one has no effect.
W1C — Write One to Clear
Bits and fields specified as W1C can be read. Writing a one clears these bits
for the duration of the write; writing a zero has no effect.
WO — Write Only
Bits and fields specified as WO can be written but not read.
Addresses
Unless otherwise noted, all addresses and offsets are hexadecimal.
Aligned and Unaligned
The terms aligned and naturally aligned are interchangeable and refer to data objects
that are powers of two in size. An aligned datum of size 2nis stored in memory at a
byte address that is a multiple of 2n; that is, one that has nlow-order zeros. For ex-
ample, an aligned 64-byte stack frame has a memory address that is a multiple of 64.
A datum of size 2nis unaligned if it is stored in a byte address that is not a multiple
of 2n.