Digital Equipment PDP-9 Guide

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,.
Digital Equipment Corporation
Maynard, Massachusetts
PDP-9
momODma

DEC-9A-HOAA-D
PDP-9
SYSTEM ADJUSTMENT MANUAL
DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Printing November 1968
2nd Printing November 1969
Copyright © 1968, 1969 by Digital Equipment Corporation
The following are trademarks of Digital Equip-
ment Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
ii
PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
1. Introduction
2.
Main Memory (MM)
2.1
MC70B Voltage Checks and Adjustments
2.1.1
Main Voltage Check
2.1.2
Second Stage Clamp Voltage Check
2.1.3
Slice Voltage Check
2.2
MC70B Timing Adjustments 2
2.2.1
Check 2
2.2.2
Set Up
2
2.2.3
Procedures 3
3.
Control Memory (CM) 9
3.1
Check 10
3.2 Set Up
10
3.3
Procedures
11
3.3.1
Current Start Delay
11
3.3.2
Start Delay
13
"3.3.3
Width Delay
13
3.3.4
Loop Delay 14
3.3.5
Strobe Start Delay
15
3.3.6
CLR Position Delay
15
3.3.7
Current Delay 17
3.3.8
System Timing
17
4.
I/o Adjustments
18
4.1
I/O Restart H22 KD09
18
4.1.1 Set Up
18
4.1.2
Procedure
19
4.2
EAE Restart E40 KD09
19
4.2.1
Set Up
19
4.2.2
Procedure
19
4.3
Power Fail 20
4.4
Power Clear
21
4.5
PC09 Reader Ti mi ng
21
4.5.1
Set Up
21
iii

CONTENTS (Cont)
Page
4.5.2
Procedure 22
ILLUSTRATIONS
Ground Reference 2
2
MA Set Up 100 ns/cm @ 1 V/cm 3
3 Stagger Time 100 ns/cm @ 1 V/cm 4
4 Strobe 100 ns/cm @ 1 V/cm 5
5 Pause Time 100 ns/cm @ 1 V/cm 6
6 Write Time 100 ns/cm @ 1 V/cm 6
7 Core Output and
SAR 50 ns/cm (Sweep 0.5 \-Is/lO) @ 1 V/cm 7
8 Core Output With Excessive Dispersion 8
9 Core Output With Minimum Dispersion 9
10 B31 0I Simpl ified Schematic
10
11 MB 14(1} With Correct Timing Adjustment
11
12
MB 14(1} With Incorrect Timing Adjustment
12
13 Current Start 20 ns/cm (0.2 \-IS X 1O) @ 1 V/cm 12
14
Start Delay 20 ns/cm @ 1 V/cm
13
15
CM Current 20 nsf cm @ 1 V/ cm
14
16
Loop Delay 100 ns/cm @ 1 V/cm 15
17
Strobe Start Delay 100 ns/cm @ 1 V/cm
16
18
CLR Position 100 ns/cm @ 1 V/cm
16
19
Current Delay 100 ns/cm @ 1 V/cm 17
20
I/O RestartI Incorrect Set Up 100 ns/cm @ 1 V/cm
18
21
I/O RestartI Correct Set Up 100 ns/cm @ 1 V/cm
19
22 Set Up for EAE Restart 100 ns/cm @ 1 V/cm 20
23 EAE Restart 100 ns/cm @ 1 V/cm 21
24 Reader Strobe Timing Adjustment 22
25 Reader Strobe Timing AdjustmentI 50% Duty Cycle 23
iv

1. INTRODUCTION
This document is prepared to assist field service personnel in performing a system adjustment
of the PDP-9. Procedures are given for various adjustments of the Main Memory (MM), the Control
Memory (CM), and some Input/Output (I/O) conditions.
The material
is organized in a test procedure format and presumes a prior knowledge of the
computer hardware and standard test equipment. It
is further assumed that the user of this document is
able to prepare and load certain diagnostic programs required in the performance of these procedures.
Where necessary, line tracings
of osci Iloscope waveforms are given to aid the technician in
evaluating the system under test. These are not idealized waveforms but actual tracings made by the
manufacturer under factory conditions. Any deviation in these patterns from those observed at the cus-
tomer1s site should be indicative only of differences in ambient conditions.
2. MAIN MEMORY (MM)
2.1 MC70B Voltage Checks and Adjustments
2.1.1 Main Voltage Check -The MM voltage is measured between J01M and HOlM (negative
probe of meter on HOlM). Adjust the potentiometer on the G804 module, Location (LOC) HJ08 on the
MC70S, for 23.5 Vdc. (See tech tip 108, PDP-9 tech tip 3 concerning G622s.)
2.1.2 Second Stage Clamp Voltage Check -The second stage clamp voltage is measured between
E25B and E25N (negative probe of meter on E25B). Adjust the potentiometer on the G008 module,
LOC E25 of the MC70B, for 6 Vdc. (This is the right-hand potentiometer on the G008 as you face the
module
handle.)
2.1.3 Slice Voltage Check - The slice voltage is measured between E25H and E25A (negative probe
of meter on E25H). Adjust the potentiometer on the G008 module, LOC E25 of the MC70B for approxi-
mately 4.2 Vdc. (This is the left-hand potentiometer on the G008 as you face the module handle.)
NOTE
This is a ball park figure which will be refined,
after the memory timing adjustments have been
made, to
balance the +lOV margins on the sense
amplifiers.

I
L
2.2 MC70B Timing Adjustments
2.2.1 Check - Check the MM timing adjustments by doing a JMP 0 in LaC 0, (LaC 00000 =
600000). If the computer will not run this instruction, turn the DATA switches to UP (all ls) and the
ADDRESS switches to DOWN (all Os). With the REPT (REPEAT) switch turned UP, turn the MAINTEN-
ANCE switch to DEPOSIT. Use the highest REPT SPEED (position 5).
2.2.2
Set Up - Set the oscilloscope to ALT MODE and set the GAIN of both traces to 1 V/cm.
With the input signals grounded, position the traces 1.5 cm above the center line of the grid. (The
negative input signals should cross the center line of the Scope Grid (SG) when they are -1.5V.) All
times are measured along the center line of the SG (see Figure 1).
Figure 1 Ground Reference
2

2.2.3
Procedures -Unless otherwise noted, SYNC on probe 1 of the scope. If the scope is not
equipped for
this, use an external sync, and then SYNC on the same signal as is being observed on
probe
1. Un less otherwise noted, a II measurements are taken from the negative leading edge of the
signal on channell to the negative leading edge of the signal on channel 2. See specific figures for
the time/cm settings. All locations, unless otherwise noted, refer to the MC70B section.
IWARNING I
Be sure to GROUND (GND) all probes.
2.2.3.1 MA Set Up
Probe 1: F36M = CLOCK (ClK)
Probe 2: C16D = DIGIT READ SYNC (RS)
Delay time: 180 ns
Adjust: D35
See Figure 2.
Figure 2 MA Set Up 100 ns/cm @ 1 V/cm
3

2.2.3.2 Stagger Delay
2.2.3.3
Probe 1: C16D = DIGIT RS
Probe 2: H33D =WORD READ (WR)
Delay time: Approximately 80 ns
1
Adjust: D33
See Fi gure 3.
2
Strobe De lay
Figure 3 Stagger Time 100 ns/cm @ 1 V/cm
Probe 1: C16D =DIGIT RS
Probe 2: E32 L = MEM Strobe
Delay time: 320 ns
Adjust: E30
See Figure 4
~ThiS is an approximate setting and may be refined later to optimize memory margins and operation.
Any time that strobe (E30) is adjusted stagger (D33) must a Iso be adjusted by the same amount to
maintain the correct relationship between core memory output and strobe (see Figure 7).
4

Figure 4 Strobe 100 ns/ cm @ 1 V /cm
2.2.3.4 Pause Delay
Probe 1: E32l = MEM Strobe
Probe 2: H32N WORD WRITE ryvW)
Delay time: 260 ns
1
Adjust: F33
See Figure 5
2.2.3.5 Write Delay
Probe 1: F36M = elK
Probe 2: H32N = WW
Delay time: Adjust for overlap of 20-30 ns
Adjust: F34
See Figure 6
1 For a
machine with parity option and a 1.2 !-IS cycle time, adjust pause (F33) for 400 ns instead
of 260. All other memory timing adjustments will remain the same.
5

Figure 5 Pause Time 100 ns/cm @ 1 V/cm
Figure 6 Write Time 100 ns/cm @ 1 V/cm
6

NOTE
If the computer wi II not run instuctions as yet,
perform the CM adjustments in the KC09A cen-
tra I processor before proceed i ng.
2.2.3.6 StaggerTime Set Up -Load all ls through memory, i.e., with all the DATA switches in the
"1" position UP, ADDRESS switches DOWN (Os), and the REPT switch UP; press DEPOSIT (DEP) and
then DEP NEXT. Hold the switch in the DEP NEXT position for a few seconds (until all locations are
loaded); release, put the REPT switch DOWN, press I/O RESET and then START. The computer should
loop through memory. Look
at pin C23U -strobe SENSE AMPS RIGHT (SAR), with probe 1 and SYNC
on this signal. Look at pins P or R of any sense amplifier, such as C23R, with probe 2. Adjust the
scope so that the strobe pulse crosses the center I ine of the SG when it is -1. 5V. Adjust stagger (D33)
so
that the peak output of the core signal (probe 2) intersects the negative leading edge of the strobe
signal (probe
1) where it passes through the center line. See Figure 7. When making this adjustment
be sure that the core output varies in time and not the strobe pulse.
Figure 7 Core Output and SAR 50 ns/cm
(Sweep 0.5 I-Is/l0) @ 1 V/cm
7

2.2.3.7 Slice Level Set Up -Using the same scope set up as in 2.2.3.6, look at channel 2 only.
Set up scope timing as in Figure 8. With the all 1s program running through memory, adjust the poten-
tiometer on the W016 module (LOC HJ21) until the deflection of the leading edge of the core signal is
minimum. This adjustment balances the WS signals to each 4K portion of the 8K stack so that the sense
amp outputs will occur at about the same time regardless of the bits address. The Null Point signals
should be similar to those in Figure 9. After performing this adjustment recheck stagger time (Figure 7)
and reset if necessary. Also see tech tip 18 for PDP-9s.
Figure 8 Core Output With Excessive Dispersion
To finalize the slice voltage setting, load the extended memory checkerboard program DEC-
9A-D1BA-PH into memory as per those instructions. Stop program and turn off power. Turn on SENSE
AMP MARGINS switch in MC70B (switch 7) and put the MARGINAL VOLTAGE switch to +10V. Turn
on computer and run program. Vary margins in positive direction until a failure occurs. Record the
setting on the meter. Do the same in the negative direction. Adjust the slice voltage level on the
G008, as in Section 2.1.3, until equal positive and negative variations from 10V result. These
8

margins must be equal and should exceed the margin specifications for switch 7@ -+ 7.0V. This should
require less than 1 complete turn in either direction to balance margins.
Figure 9
Core Output With Minimum Dispersion
3. CONTROL MEMORY (CM)
The
CM delays are B310s whose delay times are adjusted by jumper wires on the wiring side
of the PDP-9. These jumper wires are installed at the plant; however, if module replacement in the
CM timing area is necessary and/or if margins fall below specifications, then adjustments must be made
in
the field. For adjustment procedures, refer to Figure 10. The B310 is adjustable in increments of
12.5 ns starting with a minimum delay through the circuit of about 27.5 ns when pins E and K or Nand
Tare jumpered together. A maximum of 65 ns delay is available when E and For Nand Pare jumpered
together. When an adjustment is necessary "Adjust E33 E to K, J, H, F" might be called out. The
user
then need only remove the existing jumper wire, E to J and install a new wire, to make delay
longer E to H.
9

L
OUTPUT
K
INPUT
o 0 la N. 0 E
H
U
OR
OUTPUT
T
5
INPUT
MO 1<1
R
Figure 10 8310, Simplified Schematic
3.1 Check
To see if the delays are set properly, load the following program and look at 8320 (M8 14 1)
in the KC09.
LOC 00000 = 777777
Lam
00001 =700010 lOT CLA
00002 = 600000 JMP 0
The correct signal is shown in Figure 11. If the signal appears as shown in Figure 12, the CLR pulse
timing is off and the CM timing adjustments should be checked.
3.2 Set Up
All times are measured from the 50% point of the signal on probe 1 to the 50% point of the
signal on probe 2 unless otherwise noted. Set up the oscilloscope in ALT MODE with gain on both
10
"'---------------- - ---------------- -------------- ----

channels set to 1 V/cm and SYNC on probe 1. If the scope is not equipped for this SYNC externally
with the same signal as on probe 1. See specific figures for the time/cm setting.
3.3
3.3.1
Program JMPO lOC 00000 =600000
Figure 11 MB 14(1) With Correct Timing Adjustment
Procedures
Current Start Delay
Probe 1:
COl H - ClK
Probe 2: F26U -CM current
Delay time: 26 ± 10 ns
Adjust: (see footnote 1)
See Figure 13
------------------------
lThis is only a check. There is no adjustment other then a module change and checking to see
that all pertinent clamp loads are wired in and working.
11

Figure 12 MB 14(1) With Incorrect Timing Adjustment
Figure 13
Current Start 20 ns/cm (0.2 f.lS X10)@ 1 V/cm
12

3.3.2
3.3.3
Start Delay
Probe 1:
COl H - ClK
Probe 2: E27N -CM strobe D
Delay time: 100 ± 10 ns
Adjust: E29 E to F, H, J, K and N to P, R, S, T 1
See Figure 14.
Figure 14 Start Delay 20 ns/cm @ 1 V/cm
Width Delay
Probe 1: COl H ClK
Probe 2: F26U CM current
Delay time: 80 + 25 - 0 ns
Normally these delays are set to their maximum i.e., E to F and N to P. Module checking and
clamp load testing may be necessary to get the specified time.
13

3.3.4
Adjust: (see footnote 1)
See Figure 15.
Figure
15 CM Current 20 ns/cm @ 1 V/cm
loop Delay (see Section 3.3.8 for Final Check)
Probe 1: COl H ClK
Probe 2: E33M - CM strobe D.
Delay time: 212 + 0 -12 n/
Adjust: E33 E to K, J, H, F
See Figure 16.
1 Again, this
is a check only and the actual time is dependent upon circuit delays and proper
2 module operation and clamp loads functioning.
look at probe 2 only.
This is the time from the first CM strobe Dafter ClK to the 2nd CM strobe D.
14