Digital Equipment PDP-11 Series User manual

. ~nmnomn
0
000
processor
handbook
digtalequipmentcorporation

Copyright© 1975 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital
Equipment Corporation assumes no re-
sponsibility for any errors which may appear in
this handbook.
The
following are trademarks of
Digital Equipment Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
LSl-11
ii
PDP
FOCAL
DEC US

CHAPTER
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CONTENTS
1 INTRODUCTION
The LSl-11 Concept .
PDP-11/03
Features .
System
Architecture
Microcomputer
1.5.1 General Registers
1.5.2 The Processor Status Word .....
·
i.5.3 Instruction Set .
LSl-11
Memory Organization
LSl-11 BUS
1.7.1
Bidirectional Lines
1.7
.2 Master Slave Relation
1.7.3
Interlocked Communication
CHAPTER 2 SPECIFICATIONS .......... .
2.1 LSl-11
Operating Specifications ................. .
2.2 PDP-11/03 Operating Specifications ... .
2.3 H9270 Backplane Packaging and Mounting ..
2.4 PDP-11/03 Packaging and Mounting .....
CHAPTER 3 ADDRESSING MODES ....
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Single Operand Addressing ....
Double Operand
Addressing .
Direct Addressing
3.3.1 Register Mode ....
3.3.2 Autoincrement Mode .
3.3.3 Autodecrement (Mode 4)
3.3.4 Index Mode (Mode 6) .
Deferred
(Indirect) Addressing ............... .
Use
of the PC as a General Register .
3.5.1 Immediate Mode .....
3.5.2 Absolute Addressing ......
3.5.3 Relative Addressing .
3.5.4 Relative Deferred Addressing
Use
of Stack Pointer as General Register .
Summary of Addressing Modes
3.7.1 General Register
Addressing ..................
3.7.2 Program Counter Addressing
CHAPTER 4 INSTRUCTION SET
4.1 Introduction
4.2 Instruction Formats .........
4.3 List of Instructions .. .
4.4 Single Operand Instructions ............ .
4.5 Double Operand Instructions
4.6 Program Control Instructions
iii
1-1
1-1
1-1
1-1
1-3
1-4
1-5
1-7
1-8
1-9
1-10
1-12
1-12
1-12
2-1
2-1
2-2
2-2
2-2
3-1
3-3
3-3
3-5
3-5
3-7
3-8
3-9
3-11
3-13
3-14
3-15
3-16
3-16
3-17
3-17
3-17
3-19
4-1
4-1
4-2
4-4
4-6
4-24
4-34

CHAPTER 5 PROGRAMMING TECHNIQUES ..
5.1 The Stack ·
5.2 Subroutine Linkage ....
5.2.1 Subroutine Calls
5.2.2 Argument Transmission
5.2.3
Subroutine Return .......................
5.2.4 LSl-11 Set Subroutine Calls
5.3
Interrupts ..... .. .... .. ... ................
5.3.1· General Principles .
5.3.2
Nesting
5.4 Programming Peripherals
5.5 Device Registers
CHAPTER 6 EXTENDED ARITHMETIC OPTION
..
6.1 General ..........
6.2 Fixed Point Arithmetic (EIS) ................. .
6.3 Floating Point Arithmetic (FIS) .
CHAPTER 7 CONSOLE OPERATION
7-1 General
............ .
7.2 Interfacing
7.3 CDT/Console Microcode
APPENDIX A
Memory Map ....
APPENDIX B
Instruction Timing
APPENDIX C LSl·ll PDP-11 Family of Computers ........
APPENDIX D
Instruction Index
APPENDIX E Summary of LSl-11 Instructions .....
iv
5·1
5-1
5.5
5.5
5-6
5.9
5.9
5·10
5-10
5-11
5·13
5-14
6·1
6·1
6-1
6-6
7·1
7-1
7-1
7-2
A·l
B·l
C·l
D·l
E·l

The LSl-11 (PDPll/03) is the smallest member of the PDP-11 family
of computer systems. It offers the user minicomputer performance in a
microcomputer package that crosses traditional industry barriers. There-
fore,
the us,er can truly add computer power in systems previously too
small for computer application. Yet for our traditional user, the boxed ver-
sion of the LSl-11, the PDPll/03, offers a completely integrated smaller
systems tool at lower cost without sacrificing performance. The LSl-11
(PDPll/03) maintains traditional PDP-11 architectural compatibility.
This includes programs up to 64K bytes and the use of the (optional)
floating instruction set (FIS) and extended instruction set (EIS).
Since
the main design objective of the PDP-11 family has always been
to optimize total system performance, the interaction of software and
hardware have been carefully considered at every step in the design
process. The initial PDP-11 was specified in the ISP language and ex-
tensively simulated and benchmarked.
The effort of bringing the LSl-11 to the marketplace has required exten-
sive design engineering ranging over many disciplines. The basic N-chan-
nel MOS
semiconductor densities are state-of-the-art, since the PDP-11
requires many circuits. In fact, the 4-chips that comprise the processor
have approximately 50,000 active elements in an area of about 4 x 200
mils x 200 mils (0.16 square inches). Extensive circuit simulation was
carried out for the basic circuits that comprise those elements-using a
DECsystem-10.
The basic logic masks were laid out using an Applicon
system for computer-aided-design, which is based on a PDP-11. Two
levels of simulation were carried out on a DECsystem-10 to check the
logic (Gate Level), and the behavior of the microprograms (Register-
Transfer Level). Finally, complete systems were simulated (including
1/0 equipment).
All the preparation in the design and production of computers, we be-
lieve,
is necessary to support our main goal: providing high performance
quality computers at the lowest cost by which you, our users, can apply
them.
v
fL~
C. Gordon Bell
Vice President,
Engineering
Digital Equipment Corporation

vi

CHAPTER 1
INTRODUCTION
1.1 THE LSl·ll CONCEPT
DIGITAL introduced the first PDP-11 Processor in 1970. Since then, a fam·
ily of PDP-11 Computer products has been constantly evolving-not just
a family of processors, but a family of peripherals, software, and ser-
vices. Today,
the PDP-11 family is the broadest family of compatible
computer products on the market, with one of the latest additions being
the LSl-11.
The LSl-11 is a
16-bit microcomputer with the speed and instruction set
of a minicomputer. Due to its size and unique capabilities, it can fit into
almost any instrumentation, data processing, or controller configuration.
1.2 PDP-11/03
The PDP-11/03, a 3lh "H x 19"W x 13% "D boxed version of the LSl-11,
is designed as an
off-the-shelf microcomputer system. It consists of an
LSl-11
microcomputer, a modular power supply, and a mounting box. The
mounting box is designed to mount in a standard 19" cabinet. For a
description of PDP-11/03 specifications, refer to Chapter 2.
1.3 FEATURES
The LSl-11 has the following features:
•
400 Plus Instruction Set
More
than 400 instructions make up the LSl-11 's extensive instruction
set. This instruction set (also used by the PDP-11/ 35,40) permits the
user to take advantage of standard PDP-11 software. The only depar-
ture from the standard software is the addition of two new instruc-
tions, used to explicitly access the processor status word (PSW), De-
velopment programs as in the PDP-11 family include assemblers,
linkers, editors, loaders,
utility packages, operating systems, and
higher level languages.
• Extensive
Compute Power and Small Processor Size
The processor
module is built around a set of four N-channel metal
oxide semiconductor (MOS) chips, which include control and data
elements as well as two microcoded read-only memories (microms).
The latter are programmed to emulate the powerful PDP-11/35,40 in-
struction set, along with routines for on-line debugging techniques
(ODT), operator interfacing, and boot-strap loader capability. The
processor also
contains a 16-bit buffered parallel input/ output (I/ 0)
bus, a 4096-word MOS random-access memory (RAM), a real-time
clock input, priority interrupt control logic, power-fail/ auto restart, and
other features to provide stand-alone operation. The entire processor,
plus all
of the above-mentioned features, are contained on one 8.5-by-
10-inch
printed circuit board.
1-1

• Modularity
The processor, memory, device interfaces, backplane, and intercon-
necting hardware are all modular in design. Module selection, such as
the type and size of memory, and device interfaces, enable custom
tailoring to meet specific application requirements.
• Serial and Parallel 1/0 Modules
Serial and parallel
1/0 modules are available for interfacing the pro-
cessor bus
with external devices. These modules simplify connection
to peripherals when and if required, and also facilitate assembly of
prototype systems without penalizing later development of customized
interfaces.
• Choice
of Memory
Memory modules are offered for applications requinng more storage
than is available with the 4096-word MOS random-access memory on
the processor board. Included are a non-volatile 4096-word core mem-
ory, a 1024-word
static RAM, a 4096-word dynamic RAM which can be
automatically refreshed by central processor microcode, and read·only
memory (PROM/ROM) with capacity to a maximum of 4096 words in
512-word
increments (2048 words in 256-word increments).
• 16-Bit Word (Two 8-Bit Bytes)
Direct addressing of 32K 16-bit words.
• Word
or Byte Processing
Very
efficient handling of 8-bit characters without the need to rotate,
swap,
or mask.
• Asynchronous Operation
System
components run at their highest possible speed; replacement
with faster devices means faster operation without other hardware or
software changes.
• Stack Processing
Hardware sequential
memory manipulation makes it easy to handle
structured data, subroutines, and interrupts.
• Direct Memory Access (OMA)
Inherent in the architecture is direct memory access for multiple de-
vices.
• 8 General-Purpose Registers
For
accumulators or address generation.
• Priority-Structured
I/ 0 System
Daisy-chained
grant signals provide a priority-structured 1/0 system.
• Vectored
Interrupts
Fast interrupt response without device polling.
• Single and Double Operand
Instructions
Powerful and convenient set of programming instructions.
• Power-Fail/Auto Restart
Whenever
DC power sequencing signals indicate an impending AC
power loss, a microcoded power-fail sequence is initiated. When power
is restored,
the processor can automatically return to the run state.
Four
options are available for power up sequencing.
J-2

1.4 SYSTEM ARCHITECTURE
A complete and powerful microcomputer system can be configured by
utilizing the KDll-F microcomputer, appropriate memory, 1/0 devices,
and
interconnection hardware. The LSl-11 bus (implemented on the
H9270 card guide backplane assembly) is the interface which enables a
complete system to be configured.
H9270 BACKPLANE
SERIAL PARALLEL
DEVICES
DEVICES
MSVll·A
11( • 16
SIT RAM
LSI ·11 BUS
MSV11·8
41(•16
BIT RAM
MMVll·AA
41( •16
BIT CORE
Figure 1-1 LSl-11 System Configuration
SPECIAL
HIGH·SPfEO
UO USER
INTERFACES
All LSl-11 modules connected to this common bus structure receive the
same interface signals. LSl-11 bus control and data lines are bidirec·
tional, open-collector lines which are asserted when low. All transactions
on the bus are asynchronous. The bus is composed of 16 multiplexed
data/ address lines, six data transfer control lines, six system control
lines, and five interrupt and direct memory access (DMA) control lines.
Interrupt and DMA are implemented with two daisy-chained grant sig-
nals which
provide a priority-structured 1/0 system. The highest priority
device is the module electrically located closest to the microcomputer
module. Only when a device is not asserting a request does it pass grant
signals to lower priority devices.
The LSl-11
bus provides a vectored interrupt interface for any device.
Device
polling is not required in processing interrupt requests. When an
interrupting device receives a grant, the device passes to the processor
an interrupt vector which points to a new processor status word and the
starting address of an interrupt service routine for the device.
The
H9270 backplane assembly contains all of the wiring for the LSl-11
bus, plus
standard power and system control wires.
1-3

1.5 MICROCOMPUTER
The microcomputer connected to the LSl-11 bus controls the time al-
location
of the LSl-11 bus for peripherals and performs arithmetic and
logic
operations and instruction decoding. It contains multiple high-
speed, general-purpose registers which can be used as
accumulators,
address pointers, index registers, and other specialized functions. The
processor does both single and
double operand addressing and handles
both 16-bit word and 8-bit byte data. The bus permits data transfers
directly between 1/0 devices and memory without disturbing the pro-
cessor registers.
The
microcomputer processor is implemented with four LSI 40-pin chips.
The
four chips are the control chip, the data chip, and two microm
(microcode read-only memory) chips.
Control Chip
This chip provides the microinstruction address sequence, for the microm
and control for the data access port. It contains the following features:
•
Programmable Translation Array (PTA)-Provides a decoding mech-
anism for generating microinstruction addresses from macroinstruc-
tions.
• Location Counter (LC)-Stores the address in the microm from which
accesses are being made.
• Return Register
(RR)-Used to hold a microsubroutine return address.
• Data
Transfer Control Logic-Provides control and timing signals for
data/ address port.
•
Interrupt Logic-Provides control over three internal flags for the pro-
cessor and four external flags for the system.
Data Chip
The data chip incorporates the paths, registers, and logic to execute
microinstructions. It offers the following features:
• Register
File-Provides multiple registers for storage of frequently re-
quired data.
•
Arithmetic and Logic Unit (ALU)-Performs the arithmetic and logic
operations necessary for instruction execution.
•
Condition Flags Logic-Monitors the status of the result from the ALU
section.
•
Data/ Address Port-Provides access to the data address lines.
Microm Chips
The microm chips provide storage of the microcode for emulation of the
basic PDP-11/35,40 instruction set, resident ODT (octal debugging tech-
nique) firmware, resident ASCII/console routine, and bootstrap.
An optional fifth chip (third microm) can be added to the LSl-11 pro-
cessor, via a
socket available on the microcomputer module, to extend the
instruction set to include fixed and floating point arithmetic instructions.
1-4

1.5.1 General Registers
The LSl-11 central processor
module contains eight 16-bit general-pur-
pose registers
that can perform a variety of functions. These registers
can serve as accumulators, index registers,
autoincrement registers, auto-
decrement registers, or as stack pointers for temporary storage of data.
Arithmetic operations can be from one general register to another, from
one memory location or device register to another, or between memory
locations or a device register and a general register. The following illus-
tration identifies the eight 16-bit general registers RO through R7.
GENERAL
REGISTERS
RO
Rl
R2
RJ
R•
RS
R6 It SP)
STACK POINTER
R7 ltPC)
PROGAAM COUNTER
Figure 1-2 General Register Identification
Registers R6 and R7 in the LSl-11 are dedicated. R6 normally serves
as
the Stack Pointer (SP) and contains the location (address) of the last
entry in the stack. Register R7 serves as the processor's Program
Counter (PC) and contains
the address of the next instruction to be exe-
cuted.
It is normally used for addressing purposes only and not as an
accumulator. Register operations are internal to the processor and do
not require bus cycles (except for instruction fetch); all memory and
peripheral device data
transfers do require bus cycles and longer execu-
tion time. Thus, general registers used for processor operations result in
faster execution times. The bus cycles required for memory and device
references are described below.
Bus Cycles
The bus cycles
(with respect to the processor) are:
DATI Data word
transfer in Equivalent to Read opera-
ti on
DATIO Data word
transfer in, fol- Equivalent
to
Read/ Modify
lowed by word transfer out Write
DATIOB Data word
transfer in, fol- Equivalent
to
Read/ Modify
lowed by byte transfer out Write
DATO Data word transfer out Equivalent
to
Write opera-
ti on
DATOB Data byte
transfer out Equivalent
to
Write opera-
ti on
1-5

Every processor instruction requires one or more bus cycles. The first
operation required is a DATI, which fetches an instruction from the loca-
tion addressed by the Program Counter (R7). If no further operands are
referenced in
memory or in an 1/0 device, no additional bus cycles are
required
for instruction execution. If memory or a device is referenced,
however, one
or more additional bus cycles are required.
Note
the distinction between interrupts and DMA operations: Interrupts,
which may change the state of the processor, can occur only between
processor
instructions; DMA operations can occur between individual bus
cycles since
these operations do not change the state of the processor.
Addressing Memory and Peripherals
The maximum direct address space of the LSl-11 is 32K 16-bit words of
memory. LSl-ll's memory locations and peripheral device registers are
addressed in precisely
the same manner. The upper 4096 addresses
(28K-32K) are usually reserved by convention for peripheral device ad-
dressing. However,
the user does not need to dedicate the entire 4K
space to 1/0; he can implement only what he needs.
An
LSl-ll word is divided into a high byte and a low byte as shown
below.
15
7 0
: HIGH: BYTE :
1 LOW0
PifTE:
I I
Figure 1-3 High and Low Byte
Word addresses are always even-numbered. Byte addresses can be
either
even- or odd-numbered. Low bytes are stored at even-numbered memory
locations and high bytes at odd-numbered memory locations. Thus, it is
convenient
to view the memory as:
16-BIT WORD
BYTE BYTE 8-BIT BYTE
HIGH LOW 000000
LOW
000000
HIGH LOW 000002
HIGH
000001
HIGH LOW
000004
LOW
000002
HIGH
000003
LOW
000004
___.-"'.'.
OR
t
01 7772
HIGH 01 7775
01 7774
LOW 017776
017776 HIGH
017777
HIGH
LOW
HIGH LOW
HIGH LOW
WORD ORGANIZATION
BYTE ORGANIZATION
Figure 1-4 Word and Byte Addresses for First 4K Bank
1-6

Certain memory locations have been reserved by convention for interrupt
and trap handling and peripheral device registers. Addresses from O to
376
8 are
usually reserved for trap and device interrupt vector locations.
Several
of these are reserved in particular for system (processor in·
itiated) traps.
1.5.2 The Processor Status Word (PSW)
lS 0
[~=~=~~~~---~~=~=-~---~~~Rl-ORTY~: ~r~l_N_l_z~l _v ~I ~c I
) 1
UJ:~'°"
~- -----NEGATIVE
'---------TRACE TRAP
Figure 1-5 Processor Status Word (PSW)
The Processor Status Word (PSW)
contains information on the current
processor status. This information includes the current processor priority,
the condition codes describing the arithmetic or logical results of the
last instruction, and an indicator for detecting the execution of an in·
struction to be trapped during program debugging. The PS word format
is shown above. Certain instructions allow programmed manipulation of
condition code bits and loading or storing (moving) the PSW. The two
instructions for explicitly accessing the PSW are described in Chapter 4.
Priority Interrupt Bit
The processor operates with interrupt priority PSW bit 7 asserted (1) or
cleared (0). When PSW bit 7 =1, an external device cannot interrupt the
processor with a request for service. The processor must be operating at
PSW bit 7 =0 for the device's request to take effect. As compared to
other PDP-ll's, the LSl-11 operates at 1 line multi level priority.
Condition Codes
The
condition codes contain information on the result of the last CPU
operation. The bits are set as follows: (The bits are set after execution
of all arithmetic or logical single operand or double operand instructions.)
Z =1, if the result were zero
N =1,
if the result were negative
C =
l, if the operation resulted in a carry from the MSB (most
significant bit) or a 1 were shifted from MSB or LSB (least
significant bit)
V =1, if the operation resulted in an arithmetic overflow
Trap (T Bit)
The program can only set or clear the trap bit (T) by popping a new PSW
off the stack. When set, a processor trap will occur through location 14 at
completion of the current instruction execution, and a new processor
status word will be loaded from location 16. This T b"1t is especia\ly use-
ful in debugging programs as an efficient method of installing break-
points.
1-7

1.5.3 Instruction Set
Implementing the PDP-11 instruction repertoire in the LSI chip set per-
mits the user to take advantage of Digital Equipment Corporation's years
of experience with the PDP-11 family-more than 17,000 units installed,
with all associated application notes, software,
documentation, training,
reliability, customer references, and the DECUS library of application
programs.
The
instruction complement uses the flexibility of the general-purpose
registers
to provide more than 400 powerful hard-wired instructions-
the most comprehensive and powerful instruction repertoire of any com-
puter in the 16-bit class. Unlike conventional 16-bit computers, which
usually have
three classes of instructions (memory reference instruc-
tions, operate
or accumulator control instructions, and 1/0 instructions),
all data manipulation operations in the LSl-11 are accomplished with
one set of instructions. Since peripheral device registers can be manip-
ulated as
flexibly as memory by the central processor, instructions that
are used to manipulate data in memory can be used equally well for data
in peripheral device registers. For example, data in an external device
register can be tested
or modified directly by the CPU without bringing it
into memory or disturbing the general registers. One can add or com-
pare data logically
or·arithmetically in a device register.
The basic
order code of the LSl-11 uses both single and double operand
address
instructions for words or bytes. The LSl-11 therefore performs
very efficiently in one step such operations as adding or subtracting two
operands or moving an operand from one location to another.
LSl-11 Approach
ADD
A, B
Conventional Approach
LOA A
ADD B
STA B
Addressing
Add
contents of location A to location B;
store results at location B
Load contents of memory location A into
accumulator
Add contents of memory location B to ac-
cumulator
Store result at location B
Much of the power of the LSl-11 is derived from its wide range of ad-
dressing capabilities. LSl-11 addressing modes
include sequential for-
ward
or backward addressing, address indexing, indirect addressing, 16-
bit word addressing, 8-bit byte addressing, and stack addressing. Vari-
able-length instruction formatting allows a minimum number of words
to be used for each addressing mode. The result is efficient use of pro-
gram storage space.
1-8

1.6 LSl·ll MEMORY ORGANIZATION
The LSl-11 processor organization and addressing, register, memory, and
device addresses are shown.
~MORY
ADORE SS
PROCESSOR
MODULE
RESICfNT
READ/WRITE
MEMORY(4K)
RESERVED VECTOR LOCATIONS
4 BUS ERROR, TIME OUT
O ~--------. 10 RESERVED
}
14 BPT TRAP INSTRUCTION, T BIT
DEVICE INTERRURT
AND SYSTEM
TRAP VECTORS
~ !OT EXECUTED
24 PONER FAIL/RESTART
30 EMT EXECUTED
34 TRAP EXECUTED
!6~ ~============: ~ ~~ ~~~D~
1
~1~
17776 USER AND SYSTEM
PROGRAMS AND
STACK(S)
100 EXTERNAL EVENT
LINE NTERRUPT
244 FIS TRAP
(28K LOCATIOllS)
NOTE:
DEVICE VECTORS AND
32K MAXIMUM
WORD LOCATIONS
OPTIONAL
MEMORY
DEVICE ADDRESSES
ARE SELECTED BY
JUMPERS LOCATED ON
THE DEVICE NTER-
l'ACE MODULES
DEVICE & REGISTER =~=~OFOR
_......_ ___ .....__ __ :~~~~~::=========:}
DEVICE ADDR., ETC:
----''--------- LOC 177776 ....__ _____ __,
MEMORY ORGANIZATION
NOTE
There is 32K of users memory space available;
however
0-28K is recommended for memory ad-
dress locations, and 28K-32K
for peripherals
1/0 device addresses, etc.
Figure 1-6 Memory Organization
1-9

1.7 LSl·ll BUS
The LSl·ll bus is a simple, fast, easy-to-use interface between LSl-11
modules. All LSl-11
modules connected to this common bidirectional bus
structure receive the same interface signal lines. A typical system ap-
plication in which the processor module, memory modules, and periph·
eral device interface modules are connected to the bus is shown in Figure
1·7.
PROCESSOR
MODULE
AND 41(
~ITE
MEMORY
4K
PROM
OoUAJCONTROI.
TO/FROM
USER'S DEVICE -~--~
Figure 1·7 Typical Bus Application
KEYBOARD ANO
CRT DtSPl.AY l/O
TO/FROM VT50
DECSCOPE OR
LA36 TELEPRNTER
Bus data and control lines are bidirectional open-collector lines that are
asserted low. The bus is comprised of 16 data/address lines (BOAL
0-15), and 17 control/synchronization signal lines, and system function
lines.
Control signal lines include two daisy-chained grant signals (four signal
pins), which provide a priority-structured 1/0 system. The highest priority
device is the module located electrically closest to the microcomputer
module. Higher priority devices pass a grant signal to lower priority de·
vices only when not requesting service. For example, "Module A," shown
in figure 1·8, is the highest priority device, and is capable of interrupting
processor operation and/or executing OMA transfers. Modules B and C
have
lower priorities, respectively. Module B can receive a grant signal
when
Module A is not asserting a request. Similarly, Module C can re·
ceive a
grant signal when both Modules A and B are not asserting a re·
quest.
Both 16-bit address and 16·bit data words (or data bytes) are multi·
plexed over the 16 BOAL lines of the LSl·ll bus. For example, during a
programmed data transfer, the processor will assert an address on ttre
bus for a fixed time.
1·10

~-----. BIAK
KDIH
MICRO·
COMPUTER
MODULE
(CO'HAINS4K
READIWRITE
RAM)
HIGHEST
PRIORTY
DEVICE
DECREASING FRIORITY -
~E
A
MOOULE
8 .
MOOUlE
c
Figure 1-8 Bus Priority Structure
BIAIC J PRIORITY
STRUCTURED
DAISY-CHAINED
e WAtiJij8"~
SYSTEM MODULES
}
REQUEST
SIGNALS
FROM
ADDITIONAL
SYSTEM
MOOULES
After the address time has been completed, the processor initiates the
programmed input or output data transfer. The actual data transfer is
asynchronous and requires a reply
from the addressed device; bus syn-
chronization and control signals provide this function.
The processor module is capable of driving six device slots (double-
height) along the bus without additional termination, as provided with the
H9270 backplane. Devices or memory can be installed in any location
along this bus, as long as the desired priority order of the devices is
maintained. Position 1 (figure 1-9) has the highest priority, position 6
the lowest.
COMPONENT SIDE UP
PROCESSOI!
POSITION 2 POSITION 1
POSITION 3 POSITION 4
POSITION 6 POSITION S 4
_A 8 C D
(MODULE INSERTION SIDE)
Figure 1-9 Devices Priority Guide
The bus protocal allows
for a vectored interrupt by the device. Hence,
device
polling is not required in interrupt processing routines. This re-
sults in a considerable savings in processing time when many devices
requiring interrupt service are interfaced along the bus. When an inter-
rupting device receives an interrupt grant signal, the device passes to the
processor, an interrupt vector. The vector points to two addresses which
contain a new processor status word and the starting address of the in·
terrupt service routine for the particular device.
One bus signal
line (BEVNT) functions as an external event interrupt line
via the processor module. This signal line can be connected to a 60 Hz
line frequency source, and can be used
as a real-time interrupt. A wire
wrap connection on the processor module enables or inhibits this func-
tion. When enabled, the device connected to this line has the highest in·
terrupt priority external to the processor. Interrupt vector 100
8 is re-
served
for this function, and an interrupt request via the external event
line causes new
PC and PS words to be loaded from locations 100
8 and
1028.
1-11

1.7.1 Bidirectional Lines
With bidirectional and asynchronous
communications on the LSl-11 bus,
devices can send, receive, and exchange data
at their own rates. The
bidirectional nature of the bus allows utilization of common bus inter-
faces for different devices, and simplifies the interface design.
1.7
.2 Master Slave Relation
Communication between two devices on the bus is in the form of a
master-slave relationship. At any point in time, there is one device that
has control of the bus. This controlling device is termed the "bus mas-
ter." The master device controls the bus when communicating with
another device on the bus, termed the "slave." A typical example of this
relationship is the processor, as master, fetching an instruction from
memory (which is always a slave). Another example is a DMA device in-
terface, as master, transferring data to memory, as slave. Bus master
control is dynamic. The bus arbitrator on the processor module, for ex-
ample, may pass bus control to a DMA device. The DMA device, as mas-
ter, could
then communicate with a slave memory bank.
Since
the LSl-11 bus is used by the processor and all 1/0 devices, there
is a priority structure to determine which device gets control of the bus.
Every device on the LSl-11 bus which is capable of becoming bus master
is assigned a priority according to its position along the bus. When two
devices which are capable of becoming a bus master request use of the
bus simultaneously, the device with the higher priority position will re-
ceive control.
1.7.3 lnlerlocked Communication
Data transfer on the LSl-11 bus is interlocked so that communication is
independent
of the physica(bus length and the response time of the
slave device. The asynchronous operation precludes the need for syn-
chronizing with, and waiting for, clock impulses. Thus, each device is-
allowed to operate at the maximum possible speed.
Full
16-bit words or 8-bit bytes of information can be transferred on the
bus between a master and a slave. The information can be instructions',
addresses, or data. This type of information transfer occurs when the
processor, as master, is fetching instructions, operands, and data from
memory, and storing the results into memory after execution of the in-
struction.
1-12

CHAPTER 2
SPECI FICA TIO NS
2.1 LSl-11 OPERATING SPECIFICATIONS
Tables 2-1 and 2-2
list the electrical and mechanical specifications of the
LSl-11 options. All LSl-11 modules will operate at temperatures of 41 °F
to 122°F (5°C to 50°C) with a relative humidity of 10% to 95% (no
condensation), with adequate airflow across the modules.
TABLE 2-1 LSl-11 ELECTRICAL SPECIFICATIONS
LSl-11 Module
Nomenclature
Description
KDII-F Microcomputer with
4K X 16 RAM
MSVII-A
lK X 16 RAM
MSVll-B 4K X 16 RAM
MRVll-AA
4K X 16 PROM/ ROM
(OK implemented)
(4K implemented)
MMVll·A
4K x 16 Core
DLVll
Serial Line Unit
DRVII
Parallel Line Unit
*Preliminary
**At the module connector
For all Modules:
Electrical
Input Logic Levels:
Bus Low: 1.3 Vdc Max
Bus High: 1.7 Vdc Min
Power Requirements*
+5 v ±5%**
+12V±3%**
I.SA (Typ)
O.SA (Typ)
2.4A (Max) I.IA (Max)
O.SA (Typ) 0.IA (Typ)
I.SA (Max)
O.IA (Max)
0.6A (Typ) 0.3A (Typ)
l.lA (Max)
0.6A (Max)
0.2A (Typ)
0.4A (Max)
2.SA (Typ)
4.IA (Max)
3.0A (Stby) (Max) 0.2A (Stby) (Max)
7.0A (Optg) (Max) 0.6A (Optg) (Max)
1.0A (Typ) 0.ISOA (Typ)
I.GA (Max)
0.250A (Max)
O.SA (Typ)
1.3A (Max)
Electrical
Output Logic Levels:
2-1
Bus Low:
O.S Vdc Max
Bus High: 2.7 Vdc Min