Digital Equipment PDP-11 Series User manual

PDP-ll UNIBUS Processor Handbook
PDP-ll/84, PDP-ll/44, and PDP-ll/24

ii
Digital Equipment Corporationmakes no representation that the interconnec-
tion
of its products in the mannerdescribedhereinwill notinfringe on existing
or future patent rights,·nor do the descriptions contained herein imply the
granting
of license to make, use, or sell equipment constructed in accordance
with this description.
Digital believes
the information. in this publication is accurate as of its
publicationdate; such information
is subject to change without notice. Digital
is not responsible for any inadvertent errors.
The following are trademarks
of Digital Equipment Corporation: DEC,
DECnet, DECsystem-10, DECSYSTEM-20, DECtape, DECUS, DECwriter,
DlBOL, the Digital logo, lAS,
MASSBUS, OMNIBUS, PDp, PDT, Q-bus, RSTS,
RSX, RT-ll, ULTRIX, UNIBUS, VAX, VMS, and VT.

iii
Contents
Preface ................................................. VII
Chapter 1 • Introduction
Overview of PDP-ll UNIBUS Family Members ................... 1-2
PDP-ll/84 System ........................................ 1-3
Software ............................................... 1-6
Networks
............................................... 1-8
Peripherals
............................................. , 1-8
Service ................................................ 1-9
Documentation .......................................... 1-9
Chapter 2 • PDP-ll/84
Introduction ............................................ 2-2
Features
................................................ 2-2
System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-3
Central Processor ........................................ , 2-4
General Registers
...................................... 2-6
Processor Status Word .................................. 2-7
Program Interrupt Request Register ....................... 2-10
Pipeline Processing
.................................... 2-11
CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12
Stack Limit Protection ................................. 2-13
Kernel Protection
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-14
Trap and Interrupt Priorities
............................. 2-15
Hardware Detected Errors
.............................. 2-16
Private Memory Interconnect .............................. 2-17
Memory System
......................................... 2-18
Memory Management
................................. 2-18
Error Correction Code
................................. 2-19
Battery Backup Unit
................................... 2-19
UNIBUS Adapter (UBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-20
DMA Cache ......................................... 2-20
UNIBUS Mapping ..................................... 2-21
Boot
ROM Facility .................................... 2-21
Cache Memory
....................................... 2-22
Cache Registers
...................................... 2-24

iv
Backplane Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-28
Console Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-29
Console Serial Line Unit Registers ........................ 2-29
Line-time Clock
......................................... 2-33
Clock status Register ................................... 2-33
Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-34
Setup Mode ......................................... 2-34
Program Mode ....................................... 2-36
Console ODT Mode ................................... 2-37
Specifications
.......................................... 2-38
Chapter 3' PDP-ll/44
System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Central Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
General Registers
...................................... 3-4
Processor Status Word .................................. 3-5
CPU Registers ........................................... 3-7
CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-7
Processor
Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9
Program Interrupt Request Register ....................... 3-11
CPU and I/O Device Registers and Addresses ................ 3-12
Memory Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 3-13
Error Correction Code and Battery Backup
................. 3-13
Memory Management
................................. 3-13
UNIBUS Map ........................................ 3-13
Cache Memory ......................................... 3-13
General System Architecture ............................ 3-13
CPU Bypass of the Cache ............................... 3-14
Cache Memory Organization ............................ 3-15
Cache-Control Registers ................................ 3-15
Floating-Point Processor
.................................. 3-21
Backplane Configuration
.................................. 3-21
Serial Line Unit Registers
.................................. 3-21
Serial Line Unit Timing Considerations .................... 3-22
Terminal Serial Line Unit Control Registers
................. 3-22
Second Serial Line
Unit Registers (SLU 2) . . . . . . . . . . . . . . . . . .. 3-26
Line
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-29
Line Clock Status Register
.............................. 3-29
Address andVector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 3- 30
Specifications .......................................... 3-31

Chapter 4 • PDP.ll/24
System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4·2
Central Processor
......................................... 4·2
Registers ............................................... 4·4
Processor Status Word .................................. 4-5
CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4- 7
Processor Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-8
CPU and I/O Device Registers and Addresses ................. 4-9
Memory System
......................................... 4-10
Memory Management ................................. 4·10
Error Correcting Code and Battery Backup ................. 4-10
UNIBUS Map ........................................ 4-10
Backplane Configuration .................................. 4-10
Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4·11
Program Mode
....................................... 4-12
Console ODT Mode ................................... 4-13
Address Specification
.................................... 4-14
Processor I/O Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-14
Stack Pointer Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-14
Entering Octal Digits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-15
Serial Line Units
........................................ 4-16
Terminal Serial Line Unit Control Registers
................. 4-16
Second Serial Line Unit Registers . . . . . . . . . . . . . . . . . . . . . . .
.. 4-19
Line Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-22
Clock Status Register .................................. 4-22
Address and Vector Assignments
............................ 4-23
Specifications
.......................................... 4-23
Chapter 5 • UNIBUS Technical Description
Characteristics of the UNIBUS ............................... 5-2
Nonmultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 5-2
Strict Master/Slave Relationship . . . . . . . . . . . . . . . . . . . . . . . . . .. 5·3
Partially Distributed Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
Overlapped Arbitration and Data Transfer ... . . . . . . . . . . . . . . .. 5-5
Asynchronous Operation ................................ 5-5
18 Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
Word or Byte Operations
................................ 5-7
Parity Error Information from Slaves ....................... 5-7
UNIBUS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
UNIBUS Data and Address Organization . . . . . . . . . . . . . . . . . . . . . . . 5·9
v

vi
Types of UNIBUS Data Transfers ............................ 5~ 10
Read Word .......................................... 5-11
Write Word
.......................................... 5-12
Write Byte
.......................................... 5-12
Read Word with Write
Intent ............................ 5-13
Write Vector
......................................... 5-14
UNIBUS Signal Details .................................... 5-14
Initialization and Shutdown Signals
....................... 5-17
Powerup Timing
...................................... 5-18
Powerdown Timing
.................................... 5-19
Initialization
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-20
Arbitration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 5-21
UNIBUS Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-22
Abnormal Cycles
..................................... 5-23
Data Transfer Signals
.................................. 5-25
DATI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
DATIP ................................ , ............. 5-29
DAIDjDAIDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-29
Write Vector Timing
................................... 5-30
Abnormal Bus Cycles
.................................. 5-32
Multiple Bus Cycles .................................... 5-32
Miscellaneous Signals
................................. , 5-33
UNIBUS Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-34
Electrically Bidirectional High-speed Lines
.................. 5-35
Electrically Unidirectional High-speed Lines
................. 5-35
BUS AC LO L and BUS DC LO L ........................... 5-36
Design Suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-37
Watch
the dc Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-37
Maintain 120-ohm Impedance and Watch
ac Signals ........... 5-38
Minimize Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 5-39
ConsiderAll Timing Cases
.............................. 5-39
Be A
Good Bus Citizen ................................. 5-40
Appendix A • PDP-ll Family Differences
Table . . . . . . . . . . . . . . . .. Al
Appendix B· Console Commands. . . . . . . . . . . . . . . . . . . . . . . . . .. B-1
Appendix C • Instruction Times .............. ;............. C-l
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Index-l

vii
. Preface
This handbook is a reference guide that focuses on Digital's PDP-ll UNIBUS
processors and details the UNIBUS specifications. Written with both evalua-
tors and users in mind, this handbook will help you choose the processor
that
best meets the needs of your application.
Chapters 1through 4 supply a discussion
of the key functions of the following
PDP-ll UNIBUS processors.
• PDP-ll/84
• PDP-ll/44
• PDP-ll/24
Chapter5 describes thetechnical specifications of the PDP-ll UNIBUS to assist
in configuring large, complex PDP-ll systems and to aid in the design of
interfaces for PDP-lls.
After reading this handbook, you may wish to learn more about PDP-ll
architecture. The PDP-ll Architecture Handbook is a companion to this
handbook and describes the
key elements of thePDP-ll architecture, including
addressing modes, the PDP-ll instruction set, memory management, PDP-ll
floating point, commercial instruction set, and the assignment of addresses
and vectors. This and other handbooks
that you can order are listed in the
documentation section
of Chapter 1.
A postage-paid Reader's Comments card is located at the back of this
handbook.
We hope you will take the time to fill it out. Your suggestions will
help us to continue to present literature
that meets your needs.

Chapter 1 •Introduction

1-2 • Introduction
The UNIBUS, a single, bidirectional, asynchronous bus, is the connecting
device that makes possible the strengths and flexibilities of the PDP-ll family
members discussedin this book. TheUNIBUS
is a high-speed communications
path that links system components and peripheral devices and provides
system-to-system connectability. This unique data bus provides the hardware
and software backbone of
the PDP-ll/84, PDP-ll/44, al1d PDP.ll/24
processors.
TheUNIBUS was the first databus in the history ofthe minicomputer industry
to enable devices to send, receive, or exchange data without processor
interventionand without intermediate buffering in memory. PDP-ll architec-
ture takes advantage of the UNIBUS in its method of addressing peripheral
devices. Memory elements, such
as main memory or any read-only or solid-
state memories, have ascending addresses starting at zero, while registers that
store input/output (I/O) data or the status ofindividual peripheral devices have
addresses in the highest 8 Kbytes of addressing space. Communications
between any twodevices on the bus use a master/slave relationship and priority
arbitration. Details of this unique UNIBUS design are highlighted in chapter 5
of this handbook.
Each member
oUhe PDP-ll family of computers shares a common architec-
ture. Each is based on a 16-bitwordlength, a common instruction set, and the
same addressing techniques. Each also shares the same data management
utilities, the same I/O systems, and the same programming languages.
The
software written for one member of the PDP-ll family runs on other PDP-ll
family members. The peripherals and I/O systems for the UNIBUS PDP-ll
. family are also compatible. In other words, the success of this Jamily of
computers
is afunction of their common architecture that provides compatibil- .
ity across all models.
Digital has provided customers with a clear growth path to expand their
computer systems
as their requirements demand. You can upgrade or extend
any UNIBUS system by adding memory and peripherals without worrying
about major incompatibilities in your computing system.
Beyond the architecture and software commonalities, the processors described
in
this handbook are bound together by the UNIBUS. Yet each PDP-ll
processorhas features andcapabilities uniquely suited for various applications.
Some functionally similar features have been accomplished with different
implementations. Therefore, there
is some repetition of information in the
chapters describing the individual processor members.
It is often necessary to
discuss each separately because what
may appear to be very subtle differences
in operations
lIlay actmilly becrucial to a certain processor's uniqueness.

1-3
Thble 1-1 lists many of the basic UNIBUS system functions and five of the
UNIBUS PDP-11 processors for comparison. This chart allows you to compare
the processors quickly, especially in relation to the latest member, the PDP-l1/
84. The X denotes the processor is equipped with that particular function.
. High-performance PDP-ll/84 System
The year 1985 marks the 15th anniversary of the PDP-11 UNIBUS computer,
and also the advent of Digital's
new, high-speed minicomputer-the PDP-11/
84. It is the most powerful, yet most cost-effective, UNIBUS PDP-11 computer
ever designed. Based
on the]-l1 chipset with cache memory, the PDP-11/84
processor surpasses PDP-11/70 performance, yet fits into the price range of the
current PDP-11 processors. The introduction of the PDP-ll/84 establishes the
fifth generation of UNIBUS PDP-11 computers. Figure 1-1 represents the
enhancement
of performance/functionalityversus price with thedevelopment
of each succeeding PDP-ll generation.
The PDP-11/84 clearly provides the
price/performance advantage over previous PDP-ll designs.
2nd generation
Performance/Functionality
3rd
generation
Figure 1-1 • UNIBUS PDP-ll Peiformance/Functionality versus Price

1-4 • Introduction
Table 1-1" Functionality Matrix
Function
Basic PDP:ll
Instruction Set with Extended
Instruction Set (multiply, divide,
longshift)
Floating-point
" Processor '
Commercial '
Instruction Set (CIS)
Memory-management
Unit '
22-bit Physical
Addressing
Maximum Memory
Console
Battery Backup
Relative Processing
Power
Expansion Slots
Open System Units
Onboard Serial-line
Units
Line-time Clock
Kernel and User
Modes
Supervisor Mode
Separation
of
Instructions ahd Data
Dual-register Set
Packaging
Box
Cabinet
PDP-ll/84
x
Microcode'stahdard
Hardware standard'
X
X
3,840 Kbytes
ASCII
.optional
1.1
7 hex:fquad and
1
quad
oin 10.5-inch box
2 in cabiriet
X
X
X
X
X
1O.5-inch
42.0-inch
PDP-ll/44
x
Hardware optional
Optional
X
X
3,840 Kbytes
ASCII
Optional
.75
1 hex/quad
and
1 quad
3 in 10.5-inch box
2
X
X
X
X
10.5-inch
10.5-inch box
within 42.0-inch
cabinet

1-5
PDP-ll/24 PDP-ll/34A PDP-llj70
x x x
Microcode optional Hardware optional Hardware optional
Hardware optional
Optional
X X X
Optional X
248 Kbytes 248 Kbytes 3,840 Kbytes
3,840 Kbytes
optional
ASCII
ASCII standard Hardware standard
Hardware optional
ASCII optional"
Optional Optional Optional
.30 .50 1.0
5 hex/quad and 3 hex/quad and 3 hex/quad and
1 quad 1 quad 1 quad
oin 5.25-inch box oin 5.25-inch box oin cabinet
4 in 10.5-inch box 3 in 1O.5-inch box
2
X X X
X X X
X
X
X
5.25-inch 5.25-inch
1O.5-inch 10.5-inch
1O.5-inch box lO.5-inch box 60.0-inch
or
within 42.0-inch within 42.0-inch 72.0 inch
cabinet cabinet
* Provided by Digital's Field Service.

1-6 • Introduction
The powerful]-ll chipset is an example of Digital's sophisticated technology,
providing increased performance in a smaller package. The chipset itself
performs functions
that once required many separate boards. Based on CMOS
technology, the]-ll microprocessor has 16-bit I/O and a 32-bit internal data
path.
It can address up to 4 Mbytes of memory. This 60-pin package
implements the full PDP-ll instruction set including hardware multiply/divide,
floating point instructions, and online debugging technique
(ODT). In addi-
tion, the chipset contains memory management logic and cache-control
registers.
It also handles all data and address transfers.
. Software
The large installed base of PDP-ll computers with their associated software
means
that software for your application will be easy to find. You can choose
from proven software developed and supported by Digital and you can choose
from software supported by third parties. An important source of software
is
DECUS, the Digital Equipment ComputerUsers Society. DECUS is one of the
largest and most active user groups in the computer industry and membership
is available to owners of Digital's computers.
The PDP-ll UNIBUS systems detailed in this handbook offer simple, easy
programming with a rich array of languages and software tools. Thousands of
application software packages already exist to serve virtually every area of
business and industry. The same software
that runs on Digital's smaller, low-
priced PDP-ll systems will run on our larger models. A directory of over 2000
available software offerings for PDP-lis is listed in Digital's two-volume PDP-ll
Software Source Book.
The Digital PDP-ll 16-bit operating systems meet realtime, timesharing, and
batch proccessing demands efficiently and effectively in a host of environ-
ments-from small, dedicated laboratory and industrial control systems to
large, multiuser information management systems. For more information
about PDP-ll operating systems and layered products,
see the PDP-ll Software
Handbook. It includes a general description of each operating system, the file
structure and data-handling facilities,
the user interfaces, the system utilities,
and the languages supported by each processor.
PDP-ll UNIBUS processors supportmultiple operating systems so that theright
hardware, operatingsystem, and application software canbecombined to meet
your exact requirements. Table
1-2 gives a short description of the PDP-ll
operating systems and the availability of each operating system on the PDP-ll
processors.

1-7
Table 1-2' PDP-ll Operating Systems
Name Description Processor
RT-11 A single-user, multi-job PDP-11/84, 11/44, 11/34A,
system, ideal for dedicated 11/24, 11/70
realtime or small business
applications
CTS-300 A multiuser, commercial PDP-11/84, 11/44, 11/34A,
timesharing system
that
11/24, 11/70
combines DIBOL
with RT-11
DSM-ll A timesharing system PDP-11/84, 11/44, 11/24,
oriented toward large 11/70
database applications
RSTS/E
A general-purpose, time- PDP-11/84, 11/44, 11/34A,
sharing system
that pro- 11/24, 11/70
vides a fast response time
in multiuser applications
and program development
RSX-11M-PLUS Multiuser, multiprogram- PDP-11/84, 11/44, 11/24,
ming realtime systems
that
11/70
support multiple languages,
program development
tools,
and a variety of
utilities
RSX-11M Subset of RSX-llM-PLUS PDP-11/84, 11/44, 11/34A,
RSX-11S
appropriate for small- 11/24, 11/70
memory PDP-11s. RSX-11S
is a memory-only system
lAS Interactive Application PDP-11/84, 11/44, 11/24,
System allows realtime 11/70
application execution
concurrent
with timeshared
processing
ULTRIX-11
Digital's enhanced native- PDP-11/84, 11/44, 11/24,
mode UNIX software that
11/70
is upward compatible with
Digital's ULTRIX-32
operating system

1-8 • Introduction
. Networks
Digital offers extensive capabilities that permit the linking of computers and
terminals into flexible configurations called networks. Networking lets com-
puter systems amd terminals, whether located within a facility or around the
world, share resources and exchange information, files, and programs.
The
smaller computers in a network have access to the powerful capabilities of
larger systems, while the larger computers can take advantage of smaller
dedicated systems chosen for specific application environments.
The PDP-ll UNIBUS processors support a wide range of users while simultane-
ously connecting them all to a network of systems. Digital's powerful commu-
nications software, DECnet, enables two or more Digital computer systems
-16-bit PDP-lls, 32-bit VAXes, and 36-bit DEC system-lOs and DECSYSTEM-
20s -to form a network. DECnet offers task-to-task communications, remote
file access, utilities for network file transfer, heterogeneous network command
terminal support, and network resource sharing.
The Ethernet-to-UNIBUS high-performance synchronous communications
controller
(DEUNA) connects VAX and PDP-ll UNIBUS systems to Ethernet
local area networks
(LANS). This allows large amounts ofdata to be exchanged
at high rates between systems located within limited distances.
The key to this networking feature is Digital's Network Architecture (DNA), a
set of hardware and software networking capabilities that supports communi-
cations between Digital's systems, and between Digital's systems and other
manufacturers' systems. Digital-to-Digital communications are permitted
through protocols, or rules,
that are defined by the DNA. Internet products
provide a means for Digital's systems to communicate with systems built by
other manufacturers. These products use common communications protocols
and are data transfer facilitators rather
than hardware emulators. Digital's
packetnet system interface
(PSI) products allow Digital's systems to connect to
public packet-switching networks.
Digital Networks: An Architecture with a Future and the Communications
Handbook describe in detail computer networking and the data communica-
tions devices available for use with the PDP-ll family members.
. Peripherals
The UNIBUS links the PDP-ll processors with one of the industry's most
comprehensive set of mass-storage systems. And it provides the configuration
flexibility and growth capacity
that make thePDP-ll processors ideal solutions
for a broad spectrum of applications.
Digital sets the standard for the design and manufacture of storage systems
with its Digital Storage Architecture
(DSA). DSA is a carefully planned
framework of standardizedinterfaces
that permit the addition of new products

1-9
and new technologies to host systems without the need to develop additional
specialized controllers or software drivers. The PDP-ll/84, PDP-ll/44, and
PDP-ll/24 all support the Digital Storage Architecture.
Digital manufactures a full range of peripheral equipment designed to meet
specific needs
as well as to maintain PDP-ll family compatibility. I/O and
storage devices range from low-cost cassette-tape devices through high-capac-
ityWinchesterdisks, and from intelligent, rugged DECwriters for hard copy, to
ergonomically designed video-display terminals.
You can also choose from a
varietyofperipheral products developed and supportedby third parties.
Either
way, there is a complete spectrum of peripherals available to complement the
software and provide the complete answer to application needs in all mar-
ket areas-business, education, industry, laboratory, and engineering envi-
ronments.
The Terminals and Printers Handbook and the PDP-ll Systems and Options
Catalog describe the optional equipment available for use with the PDP-ll
UNIBUS family members.
. Service
Digital's style of computing stresses quality and consistency in every phase of
development, manufacturing, service, and support. Comprehensive services
are offered to help customers before, during, and after system installation.
Our
sales representatives work closely with customers, studying each application
and determining specific computing needs. Trained software and hardware
specialists, well-versed in designing systems using Digital's products, are
available to supplement the sales representative's product knowledge.
Comprehensive customer services continue to complete our commitment to
meeting users' needs. Digital's customerservice organizations include software
services, educational services,
and field service.
Digital
is a complete service vendor and has the products and tools to back its
commitment to customer satisfaction. For an indepth description
of Digital's
PDP-ll UNIBUS systems and PDP-ll software, talk to your Digital sales
representative or to one of Digital's commercial or technical OEMs.
Or visit
one
of Digital's Training Centers located throughout the United States. For
informationoncourses, training materials,
or training centerlocations, call the
customer support number in Massachusetts:
[phone].
. Documentation
Digital offers several levels of documentation describing PDP-ll UNIBUS
software and hardware. These manuals are updated periodically to include new
developments and equipment and can be ordered through Digital's Peripherals
and Supplies Group, Continental Boulevard, Merrimack, NH, 03054. The
following lists contain the titles and associated Digital order numbers of
documents
that apply to the PDP-ll UNIBUS family.

1-10 • Introduction
Hardware Handbooks and System Manuals
PDP-ll Architecture Handbook
Communications Handbook
Terminals and Printers Handbook
PDP-ll/44 System Technical Manual
PDP-ll/24 System Technical Manual
PDP-ll/84 System Installation and Technical
Reference Manual
Other Technical Manuals and User's Guides
PDP-ll/84 Maintenance Guide
PDP-ll/84 Site Preparation, Unpacking and
Installation Guide
DCJll Microprocessor User's Guide
KDJ11-B User's Guide
MSVll-J MOS Memory User's Guide
MSVll-J Configuration Summary
PDP-ll/44 System User's Guide
Software Handbooks
PDP-ll Software Handbook
RSX-ll Handbook
RSTSjE Handbook
ULTRIX Software Guidebook
PDP-ll Software Sourcebook-Fourth Edition
(Volumes 1 and 2)
Other Important Reference Materials
PDP-ll Systems and Options Catalog
Networks and Communications Buyer's Guide
Digital's Networks: An Architecture With A Future
EB-23657-18
EB-
30066-42
EB-23909-54
EK-KDllZ-TM
EK-ll024-TM
EK-1l84A-TM
EK-PDP84-SV
EK-PDP84-IN
EK-DCJ-ll-UG
EK-PDP84-UG
EK-MSVIJ-UG-OOl
EK-MSVIJ-HR-OOl
EK-ll044-UG
EB-25398-41
EB-25742-41
EJ-23534-18
EJ-26153-20
EB-27333-41
ED-27252-41
EB-26067-42
EB-260l3-42
The hardware user documentation, software tutorial documentation, and
reference manuals
that accompany the delivery of a PDP-ll computer system
offer the most detailed levels
of information. There are also several books
published commercially
that discuss the PDP-ll family. If you have a specific
documentation need, discuss the issue with a Digital sales representative who
will guide you to the appropriate literature.

Chapter 2 •PDP-ll/84