Digital Equipment PDP16-M User manual

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USER’S
GUIDE.

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DEC—16-IMUGA-A-D
PDP16-M
USER’S
GUIDE
digital equipment
corporation
-
maynard,
massachusetts
1'

lst
Edition
March 1973
Copyright
© 1973
by
Digital
Equipment Corporation
The material in this manual is for informational
purposes
and is
subject
to
change
without notice.
The
following
are trademarks of
Digital
Equipment
Corporation,
Maynard,
Massachusetts:
FLIP CHIP FOCAL
DIGITAL COMPUTER
LAB
‘itsefiséil‘iiflifiilmmlmmlm.
‘

CHAPTER
1
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
CHAPTER 2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
CHAPTER 3
3.1
3.1.1
3.1.2
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
CHAPTER
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
CONT
ENTS
Page
OVERVIEW
INTRODUCTION
................................
1-1
Functional
Programming
..........................
1-1
Multiple Memory
Features
..........................
1-1
MACHINE
DESCRIPTION
AND
FEATURES
....................
1-2
Programmable
Read-Only Memory
(PROM)
..................
1-2
Program
Control
Sequencer
(PCS)
......................
1-3
Register
Transfer Module
(RTM)
.......................
1-3
Modularity
................................
1-3
SOFTWARE
..................................
1-3
A
VIEW OF THE HARDWARE
FUNCTIONAL
DESCRIPTION
..........................
2-1
PHYSICAL
DESCRIPTION
...........................
2-2
SPECIFICATIONS
...............................
2-7
Processor
.................................
2-7
Mechanical
................................
2-9
Electrical
................................
210
Environmental
..............................
2
10
CONFIGURATION DATA
...........................
2
10
INTERFACING
PARALLEL
l/O
DATA
TRANSFERS
.......................
3-1
GPI
Interfacing
..............................
3-2
External
Data
Bus
Interfacing
........................
3-2
SERIAL
l/O
TRANSFERS
............................
32
MUX AND FF
l/C)
INTERFACE
.........................
3-3
MUX
AND
FF
I/O
SLOT
C19
..........................
3-3
GPII
I/O
SLOT 019
..............................
3-4
GP|2
I/O
SLOT 020
...............................
3—4
GP|3 l/O
SLOT D20
..............................
3-6
RTM
DATA
BUS SLOTS ABOI
—
A317
......................
3-6
PDP-11
PERIPHERAL
INTERFACE
CONNECTIONS ................
3-7
SI1 AND SI2 INTERFACE
CONNECTIONS
...................
3—10
INTERFACE CABLING
............................
3-12
MANUAL/AUTO
RUN
OPTION
........................
3-12
CONTINUE
OPTION
.............................
3‘12
WRITING
THE PROGRAM
REGISTER TRANSFER
INSTRUCTION
......................
4-1
Arithmetic
Group
.............................
4-2
Logical
Group
...............................
4-3
Register Group
..............................
4-4
Constant Generator
Group
.........................
4-4
I/O
Group
................................
4-4
Command
Group
.............................
4-5
Test
Group
................................
4-6

CONTENTS
(Cont)
Page
4.2
GOTO
INSTRUCTION
.............................
4-6
4
3
IF
INSTRUCTION ...............
.
.
..............
4-7
4.4
CALL
AND EXIT
INSTRUCTIONS
........................
4-8
4.5
ASSEMBLER DIRECTIVES
...........................
4-8
4.5.1
Comments
.
...............................
4-9
4.5.2
Page Linkage
Code
.............................
4-9
‘
4.5.3
Source
Program Segmentation
................
. . . . . . . 4-10
4.5.4
Assembler
Initialization
Code
....................
4-10
4.6
INSTRUCTION IMPLEMENTED THRU
OPTIONS
............
.. .
.
4-12
’
4.6.1
Scratch
Pad
(SP)
Option
MS16-C ...................
. . . 4-13
4.6.2
.
Constant
Generator
(K)
Option
MR16—D ...................
4-13
M
4.6.3
Data
PROM
Option
MR16-E
........................
4-13
4.6.4
Data
Read/Write
Memory Option
M8160
and
E
...............
4-14
4.6.5
Parallel
l/O
Option
DB16-A ......
. .
..........
. . .
.
.
.
4-16
4.6.6
PDP-11
Peripheral
Interface
Option
DA16-F .............
. . . . 4-16
4.6.7
Serial
I/O
Option
DC16-A . . .
.
.....................
4-17
4.6.8
Boolean
Output
Option
KF
L16
........
. .
............
4-18
4.6.9
Boolean
Input
Option
PCSIB-D
. .
. ................
4-19
4.6.10
IF Instruction
Option
PCS16-D
......................
4—19
4.7
SAMPLE PROGRAMS
.............................
4-19
4.7.1
Read
Paper Tape
............. .
. .
.............
4-20
4.7.2
Print
Message
on ASR
33 .....................
. .
.
. 4-20
4.7.3
Multiply
. . .
.
............................
4-21
1
CHAPTER
5
PROGRAM
PREPARATION AND
ASSEMBLY
'
5.1 BINARY
LOADER ..............................
.
5-1
5.2
SYMBOLIC EDITOR ..............................
5-3
5.2.1
Writing
a
Program
................
. . . . . .........
5-7
5.2.2
Search
Feature
..............................
5-8
5.2.3
Input/Output
Control
.......................
. . . .
5-9
5.2.4
Generating
a
Program Tape
.........................
5-9
5.2.5
Loading
a
Program Tape
.................
5-1 1
5.2.6
Restart
Procedure ............................
5-11
5.2.7
Error
Detection
.............................
5-11
5.2.8
Summary
of
Special
Keys
and Commands
................
5-12
5.3
PAL16 ASSEMBLER
..........................
.
.
.
5-14
5.3.1
Pass
1
........................
. . .......
5-14
a
5.3.2
Pass 2
................................
5-14
5.3.3
Assembling
a
Program
..........................
5-14
5.3.4
Error
Messages
..............................
5-17
,
CHAPTER 6
UTILITY OPTION
(TENTATIVE)
6.1
INSTALLATION
..........................
.
6-1
6.2
OPTION DESCRIPTION
..........................
. 6-2
6.3
OPERATIONAL
DETAILS ............................
6-3
6.3.1
Zero, Fetch,
Load and
Modify
................ .
.......
6-5
6.3.1.1
Load
................................
6-5
6.3.1.2
Modify
...............................
6-5

6.3.1.3
6.3.2
6.3.3
6.3.4
6.3.5
APPENDIX
A
A.1
A.2
A.3
A.4
A5
A6
A.7
A.8
A.9
A.10
A.11
APPENDIX
B
APPENDIX
C
APPENDIX D
APPENDIX
E
APPENDIX
F
APPENDIX G
APPENDIX H
Figure
No.
1-1
2-1
2-2
2-3
3-1
3-2
3-3
3-4
35
3-6
CONTENTS
(Cont)
Page
Fetch
................................
6-6
Simulate
........................
6-6
Program
...............
6-6
Check
.........................
.
6-7
Type
...........
.
6-7
PDP-1‘I PERIPHERAL SUMMARY
CONTROL AND STATUS REGISTERS
..................
A-1
DATA REGISTERS
...................
A-1
ASR
33
TELETYPE
...........................
A-I
PC11
HIGH
SPEED
READER
PUNCH
............
A-3
LP11 LINE
PRINTER
...........................
A-4
CR11 AND CM11
CARD
READER
...........
A-4
LA3O DECWRITER
......................
A-5
AFC11
FLYING
CAPACITOR
.........................
A-6
UDC11
DIGITAL
l/O
.............................
A-7
AA11-D
D/A CONVERTER ...................
A-8
ADOl-D
A/D CONVERTER
.........................
A-9
ASCII AND EBCDIC Cll-IARACTER SET
ENCODINGS
CONVERSION
TABLES
INSTRUCTION SET
PDP16-M MACHINE CODES
DEFINITION TAPE LISTING
SIGNAL LISTINGS
USER OPTIONS
ILLUSTRATIONS
Title
'Page
PDP16-M
Simplified
Block
Diagram
.....
. 1-2
PDP16—M
Configuration
.............................
2-3
CPU
Block
Diagram
...............................
2-4
Logic
Assembly Configuration
Diagram
....................
.
2-5
Logic
Assembly
l/O
Slot
Location ......................
3-2
GPI
Interfacing
..............................
. . 3-3
External Data
Bus
Interfacing
........................
.
3-4
PDP-‘Il
Peripheral
Interfacing
...........................
3-5
H803
Connector
Block Pin
Assignments
.............
.
3-8
PDP-II
Peripheral
Interface
Cabling Diagram
...................
3-10

Figure
No.
3-7
3-8
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
Table
No.
12-1
2-2
3—1
3-2
23-3
3-4
44
!5-1
95-2
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‘5-5
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ILLUSTRATIONS
(Cont)
Title
'
SI
Adapter
Module
M7333,
TTY
Connectors,
and
Split Lug
Identification
............................
Interface Cables
...............................
Address
and
Data Transfer Scheme
.......................
Loading
the RIM
Loader
.............................
Checking
the
RIM Loader
Loading
the
BIN Loader
.............................
Loading
A
Binary
Tape Using
BIN
Transition Between
Editor Modes
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Generating
a
Symbolic
Tape
Using
Editor
.....................
Assembling
with
PAL16
............................
Utility Computer
Configuration
..........................
MR16-SL
Utility Option
.............................
TABLES
Title
Module Slot
Assignment
and
Description
......................
Configuration
Data
..............................
MUX
and FF I/O
Slot C19
............................
GPln"
l/O
Slot
.................................
RTM Data Bus
Slots ABOI
—
AB17
........................
H803 Connector
Block
Wirewrap
Connections
Arithmetic Instruction
Set
RIM
Loader
Programs
..............................
Input/Output
Control
..............................
Summary
of
Special
Keys
...........................
Summary
of Commands
............................
PAL16 Assembler Switch
Register Option
PDP16-M
I/O
Slot
Pin
Assignments
.......................
PDP16-M RTM
Data Bus Pin
Assignments
PDP-11 UNIBUS
Pin
Assignments
vi
Page
3-11
3-12
4-15
5-2
5-3
5-4
5-5
5-6
5-10
5-18
6-2
6-4
4-3
5-1

FOREWORD
All information
necessary
for
interfacing, programming,
and
debugging
a PDP16-M
is contained
in this manual.
The
manual contains
six
chapters
and
eight
appendices.
Chapter
1
provides
an overview of the
PDP16-M.
Applications,
hardware
features,
and software are
summarized.
Chapter
2
contains
a brief
description
of
the
hardware. Functional and
physical
descriptions,
specifications,
and
configuration
data
are included.
Chapter
3 contains
details for
interfacing
the
PDP16-M
with the outside world.
All
input
and
output signals,
with
respective
loading
information,
are identified.
Specific
details
are included
for
interfacing
with serial
data
communication
devices and
low-speed
POP-11
peripheral
devices.
Chapter
4
covers
the basic instruction
set,
assembler
directives,
and
the instructions
implemented
through options.
The
chapter
details
program
formats
and
conventions,
using many examples.
Chapter
5
describes
how
to
prepare
and assemble a
PDP16-M control
program.
The RIM
and
BIN
Loaders,
the
Symbolic
Editor,
and the
PAL16 Assembler are described
in
detail.
All
features of
the
utility option
for the
PDP16-M
are discussed
in
Chapter
6.
Detailed
interface
information
is
included
in this
chapter
to allow the user to
interconnect his
utility system.
Appendix
A contains
a
summary
of low
speed
PUP-11
peripheral
devices.
Their status
control
and
data word
formats
and addresses
are
specified. Option
DA16-F
permits
the
user to utilize
low
speed
PDP-11
peripheral
devices
in
a
PDP16—M
system.
Appendix
B lists the octal codes
for
the ASCII and EBCDIC
character
sets.
Appendix
C contains various code conversion
tables.
Appendix
0 lists
the
complete
instruction
set
of
the
PDP16M.
The
list is ordered
by
classification.
Appendix
E lists the
complete
instruction set of the
PDP16-M.
The
list is
ordered
by
octal
machine
code.
Appendix
F
is a
listing
of the definition
tape
used to initialize
the
PDP-16
Assembler.
Appendix
G
lists all
PDP16-M
and
PDP-ll
l/O
signals.
The
lists are
in
alphabetic
order.
Appendix
H
is a
summary
describing options
available
to
the
small and
large
users.
vii

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CHAPTER
1
OVERVIEW
1.1 INTRODUCTION
The
PDP16-M
resembles both a
hard-wired controller
and a
general
purpose
minicomputer.
It
is similar
to
a
hard-wired
controller
because the
program:
is
stored
in
a
memory
that is
impervious
to
noise
interference
and
process
sensors/controls
can
be
easily
interfaced.
The
PDP16-M
also resembles a
general
purpose minicomputer
because it
features
arithmetic
and data
memory capability
in
addition
to the
logic
and
l/O
capability
typical
of a hard-wired
controller.
In
general, applications
tend
to be
where
a
conventional
minicomputer
may
be
too
costly
and
a
hard-wired
design
too time
consuming.
Some
typical
application
areas for
the PDP16-M
are:
0
Machinery control,
alarm
scanning,
data
collection,
monitoring,
and remote
telemetry
in
the
industrial
field.
0
Fourier
Analysis,
auto and cross
correlation,
and
waveform
synthesis
in the
laboratory.
0
Input
terminals
for
automated stock
control,
warehousing,
and
inventory
control
in
the commercial
market.
0
Data format
conversion,
code
conversion,
complex
arithmetic,
and
intelligent
front-end
processor
to
larger computers
in
the data
processing
field.
1.1.1
Functional
Programming
The
PDPIG-M
is
a function-oriented
minicomputer,
with a
simple
design
that novice
computer
users
will
quickly
grasp
and
experienced
computer
users
will
fully
appreciate.
It
is
termed a “function-oriented"
computer
because it
responds
to
a
simple
set
of
function reference
instructions.
The functions
are
specified by
plain
language
statements
that
are
similar to
those used
in
BASIC
and
FORTRAN
programming
languages.
This makes
the task
of
programming
the
PDP16-M
much
easier than
programming
a
conventional
minicomputer.
The functions
implemented
in
the
PDP16—M include
arithmetic,
Boolean
logic,
data
memory
transfers,
and l/O
operations.
1.1.2
Multiple Memory
Features
The PDP16-M
features two
segregated
memories: one for
control
instruction
storage
and another
for
data
storage.
This
feature
eliminates the
need
for
direct
memory
reference instructions
and the
programming
complexities
associated
with
memory
reference instructions
that
are
inherent with conventional
minicomputers.
The
PDP16-M
also uses an
inexpensive,
state-of~the-art,
programmable
read-only memory
(PROM)
for
program
and
permanent
data
storage.
PROMs
are
not
susceptible
to environmental
noise,
and their
contents
cannot
be
changed
inadvertently.
Thus,
they
provide
an ideal
program
and
data
storage
medium
for dedicated
control
applications
in a
noisy
environment.
The
use of
PROMs
in
the
PDP16-M
also eliminates the
need for
expensive paper
tape
l/O
equipment
or
a
computer
console,
required
by
computers
that
employ
read/write
program
storage.
1-1

1.2
MACHINE
DESCRIPTION
AND FEATURES
Figure
1-1,
a
simplified
block
diagram
of
the
PDP16-M,
illustrates
some of
the main features
of
the
PDP‘lG—M:
segregated
memory
for
instructions
and
data,
arithmetic
and
logical
capabilities
offered
by
the ALU
(arithmetic
and
logic
unit),
and
[/0
capabilities.
The
ALU,
Data
Memory,
and
HG channels are
all interconnected via
a common
data
highway
called the
Register
Transfer
Module
(RTM)
data
bus.
Notice that
the instruction
memory
is
not
connected
to the bus. Function
reference
instructions are
assigned
192
instruction
codes for
operating
on
data in
M
the
ALU
and
for
transferring
data between the
ALU,
Data
Memory,
and
WC channels.
In
addition,
64 instruction
codes
are
assigned
to
unconditional
and
conditional branch
instructions
and
subroutine CALL and EXlT
instructions.
These
instructions
operate only
on
the
program
control
sequencer
-—
not the RTM
bus.
The
application
‘
program
is stored
in
a
PROM
designated
the
instruction
(control)
memory.
The
program
is written for a
specific
application
by
the
user,
using
the
simple
PDPlG—M
instruction
set.
All
Boolean,
arithmetic,
and data transfer
functions
found
in other
computers
are available in
the
PDP16-M.
Functions
like
AND, OR,
exclusive-OR,
'
complement,
shift,
add, subtract,
binary multiply,
binary
divide,
move
data,
load data
memory,
read
from data
memory, interrogate
I/O
devices,
etc.,
can all
be
handled
with
ease in the
PDP16—M.
After the
application
program
is
'4"
*
assembled and
debugged,
it
is
loaded
into the
PROM. The
PROM
can
then be
installed in its
preassigned
slot on
the
PDPlB-M'
logic
assembly.
After
starting
the
program,
the
instructions
are
fetched and executed
by
the
program
control
sequencer
one
at a
time
without
operator
intervention. The
instruction
memory
can
be
expanded
from
its
basic 256
words to
1024 words
in
256-word
increments,
permitting
the user to
implement only
the
program
memory
he
needs.
<
ADDRESS
INSTRUCTION
MEMORY _?7::’:“°5“E§°%r
(PROM) 3
INSTRUCTION
>’“ £3?
”'3
CENTRAL
PROCESSING
UNIT
(CPU)
CONTROL
-
DATA
I/O
____>
($23125
(BOOLEAN EXTERNAL
ROM'S
FROM-é
PARALLEL
EQUiPMENT
ANc
READ-WRlTE)
AND
SERIAL)
.__.._.__
Q
RTM
Bus
>
l6-OO7Z
Figure
14
PDPlSM
Simplified
Block
Diagram
1.2.1
Programmable
Read-Only
Memory
(PROM)
The PROM
is
an
electrically
programmable
read-only memory.
It contains 256
addressable
8-bit
storage
locations.
The PROM
is
housed
in a
24-pin
dual-in-line
ceramic
package
with a
quartz
window that
exposes
the
MOS
chip.
The
M
chip
is a silocon
gate
matrix
with
switchable links.
These links can be reset
by
exposing
the
chip
to ultraviolet
light.
After the
links are
reset,
the
PROM
can
be
reprogrammed.
The PROM
may
be
reprogrammed
a
minimum of
100
times
without
affecting
reliability.
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1.2.2
Program
Control
Sequencer
(PCS)
The
PCS fetches and
executes the
instructions
one
at a
time. It
generates
control
signals
in
response
to
the
instruction
code
to
Operate
on
data in
the
ALU
and to
transfer
data between
the
ALU,
Data
Memory,
and
I/O
channels.
The
branch
and
subroutine
instructions
are
executed
by
internal
logic
of
the
PCS.
1.2.3
Register
Transfer
Module
(RTM)
The
functional
elements that are connected
to
the RTM
bus
are
called
Register
Transfer
Modules
because data can
be transferred
between
the
modules via the
RTM
bus
simply by
asserting
the
appropriate
control
inputs.
Since a
functional
element,
when not
accessing
the
bus,
presents
essentially
no load to
the RTM
bus,
the
system
can be
expanded
to
accommodate
virtually
an
unlimited
number of
elements. The standard and
optional
functional
elements
that are
available
for the
PDP16-M include:
a.
Arithmetic
and
Logic
Unit
b.
Data
Memory
Scratchpad Registers
Constant
ROMS
Data
PROMs
Data Read-Write
Memory
0.
I/O
Channels
Boolean l/O
(TTL)
Serial
l/O
(TTY
or
TTL)
Parallel
l/O
(16-bit)
PDP-ll
Peripheral
l/O
1.2.4
Modularity
All
components
(modules
and functional
elements)
of
the
PDP16—M
are
housed
on
a
single
prewired logic
assembly.
The
standard
and
optional
components
can be
implemented
simply
by
inserting
the
components
in their
preassigned
slot.
Except
for
l/O
interfacing,
no other
wiring
is
required.
1.3 SOFTWARE
An extensive
software
package
is
available
for
the
PDP16-M.
Software is
available
for:
a.
Program
development, including
preparation
and
assembly.
b.
Program
debugging
and
loading.
c.
Diagnostics
for basic machine
and
all
available
options.
Program
development, debugging,
and
loading
must be
done with the
aid of a
PDP-8/
E.
For those customers
who
do
not have
a
PDP-8/E
or
do
not wish to
purchase
one,
Digital
Equipment
Corporation
offers to load
the
Instruction
and
Data
Memory
PROMs
at
a
minimal
cost.
in
this
case,
the user
need
only
provide
DEC
with the source
tape
in
ASCII
format. Refer
to
Appendix
H.
The
diagnostic
programs
are
preloaded
on
PROMs.
To
run the
diagnostics,
the
apprOpriate
PROMs
are inserted
in the
instruction
memory
slots
and the
program
is started
by depressing
the START
switch
on the console.
If a failure
occurs,
the
diagnostic program
will
halt.
Then,
the
diagnostic
listing
and
optional
maintenance
modules
may
be used
to
quickly
isolate the malfunction. The maintenance
modules feature
instruction
and
data readout
displays,
and
single
step
and
breakpoint
functions
to
aid
in
isolating
the
malfunction.
1-3

CHAPTER
2
A
VIEW
OF
THE HARDWARE
The PDP16-M
Maintenance Manual
should
be
consulted
by
readers who are interested
in
specific
hardware
details.
2.1
FUNCTIONAL
DESCRIPTION
The
PDP16—M has
an
asychronous
control
(instruction)
memory
bus
and
an
asychronous register
transfer
bus
(Figure
2-1).
Control PROMs
connect
to
the
control
memory
bus and
all
register
transfer modules connect
to
the
register
transfer bus.
All
data transfers on the control
memory
bus and
register
transfer bus
are controlled
by
the CPU. The
CPU contains
the instruction
decoder,
state
generator,
program counter,
subroutine
stack,
arithmetic
and
logic
unit,
LINK,
A
register,
B
register,
and
TR
register
(Figure
2-2).
The basic PDP16-M
is
equipped
with one
control
PROM;
three
additional PROMs
may
be
added
to the
memory
bus.
The PROM
has 256
8-bit
storage
locations.
When
the PROM
is
addressed
by
the
program
counter
(PC)
of the
CPU,
the word in that PROM
location
is
transferred
to
the
CPU.
Both the
address and
data are
transferred
via
the
memory
bus.
In the
CPU,
the control
word
is decoded
and executed.
Only
the LET
instruction
(register
transfer)
operates
on
the
register
transfer bus. The
bus
consists of
16 data
lines
and
5 control
lines.
All
arithmetic,
logical, memory,
and
I/O
register
transfer
operations
transpire
over the bus.
The
GOTO
and
IF
instructions
simply
cause the
PC to be incremented to
fetch the
jump
address. The CALL/EXIT
instructions
operate
on
the hardware
stack to store
and retrieve
the
return
address.
All
arithmetic
and
logical
operations
are
implemented by
instructions that
operate
on the
ALU
via the
A,
B,
and
LINK
registers.
The
A
register
can
be
used
as
an
accumulator,
the
B
register
serves as
an
argument
register,
and the
LlNK
register
facilitates
carry manipulation.
The TR
register,
which
is
byte
and word
addressable,
can
be used
for
temporary
storage
or for data
manipulation.
The
register
transfer
bus
provides
the data
path
for
transferring
the
data
between
these
registers
and
any
other
register
transfer
modules that are connected
to the bus.
(Refer
to
Appendix
D
for
a
list
of all
legal register
transfer
instructions.)
The
basic
PDP16-M
is
equipped
With one
Ill-word
constant ROM and one
parallel
I/O,
both of
which
are connected
to
the bus.
in
addition,
the basic PDP16-lVl contains
three
flags/Boolean
output
channels and
six Boolean
input
channels.
A wide
variety
of
memory
and
l/O
options
can
be added to the
register
transfer bus
(Figure
2-1).
These
options
may
be added to
expand
data/constant
memory
and
l/O
capabilities.
ROMs
are available
for
storing program
constants, data,
or text information. Read/write MOS
memories
may
be used for
accumulating
data for
HO,
and
I/O
modules
may
be added to
expand
the
interfacing capabilities.
The standard
data
options
that
are
available
from
DEC
are:
DATA
MEMORY
0
Two
16
X
16
(16
words)
Scratchpad
Registers,
MS16-C
0
Two Data R/W
MOS
Memories.
Any
of
the
following
combinations
can be
implemented:
2-1

MS1'6-D
M31 6-E
Memory
(16
x
256) (16
x
1024)
Size
(words)
A
1
0256
2
0
512
0 1
1024
.M
I 1
1280
0
2
2048
0
One
16
X
24
Constant
ROM,
MR16-D
0
One
8
X
256
Data
PROM
(high
or low
order
8
bits),
MR‘lS-E
or 16
X
256
Data
PROM,
MR16-F
INPUT/OUTPUT
0
Two 16-bit
Parallel
l/O
Channels,
DBIG-A
0
Two Serial
l/O
Channels
(TTY
or
TTL),
DC16-A
0
One PDP-11
Peripheral
Interface,
DAIG-F
O
Boolean
Input
Channels
I16),
PCSIB—D
O
Flags/Boolean
Output
Channels
(3).
KFL16
The
main
frame
of the
PDP16—M
is
prewired
to
accept
any
of
the
above
options
simply
by inserting
the
Option
M
modules
in the
preassigned
slot.
2.2 PHYSICAL
DESCRIPTION
The
PDPIG-M
is
packaged
in
a small
table
top
or
rack-mountable
cabinet
with a self-contained
power supply,
cooling
fans,
an
air
filter,
and
a
simple
front
panel.
Each slot
of the
logic
assembly
has been wired
to
accept only
a
specific
module
type.
CAUTION
Damage may
result
to the
machine if an
option
is
inserted into
the
wrong
slot.
Figure
2-3 and Table
2-1
illustrate the
prewired
configuration
and describe each
module of the
PDPIG—M.
The
~
corresponding
model
number
for
each
module
and
Option
is
given
in
Table
2-1. Four additional
optional
modules
are
available from
DEC.
These modules are
designed
to
facilitate
maintenance
and
program
debugging.
(Refer
to
Chapter
5
of the PDP16-M Maintenance
Manual.)
'
2-2
"5}???
I

.IIIII
CONTROL
MEMORY
L
OPTIONS
CONTROL
MEMORY
BUS
INSTRUCTION
DECODER
8x256
3x256
8X256
8x256
STATE
GENERATOR
CONTROL
CONTROL
CONTROL
CONTROL
PROGRAM
COUNTER
PROM
PROM
PROM
PROM
STACK
PCSIG-B
PCSIG—B
PCSIe-e
PCSIG-B
ARITH
AND
LOGIC
UNIT
LINK
A
REGISTER
a
REGISTER
TR
REGISTER
CPU
DATA
MEMORY
OPTIONS
(/1
REGISTER
TRANSFER
BUS
\I
16X4
6
CONSTANT
3
FLAGS/
BOOLEAN
16x16
16x16
3
FLAGS/
R/w
MOS
R/w
MOS
CONSSfi’EITQT
PROM
ROM
BOOL
OUT
,NPUTS
SCRATCRPAD
SCRATCHPAD
BOOL
OUT
DATA
DATA
ROM
CONTROL
MR16_A
KFL16
”516-0
MSIe-C
MSIG-C
KFL16
stzss
stzse
”mew
MSIG—D
MSIG-D
l
I
OR
OR
DATA
PROM
16X1024
16X1024
MSIS—E
MSIG-E
”Rag‘E
MR16-F
2-3
l/O
OPTIONS
REGISTER
TRANSFER
BUS
DATA
l
PARALLEL
PARALLEL
PARALLEL
SE35“
SEIR/OAL
BOOLGEAN
UMBUS
DB‘G‘A
DB‘ST“
DB‘s—A
ITTY-TTL)
ITTY-TTL)
PCSIG-D
“‘6":
P0P“‘
PERIPHERAL
BASIC
INTERFACE
ADAPTER
PDP16-M
00‘6-5
NOTE
-
I
On
thIs
drawnng
model
numbers
I
L_________
K
are
glvenIothe
memoryond
regIsIer
I
_
—_—_-—'_-_-"'-_-"'_"_‘-"\
I—
transfer
modules.
For
the
correspondmg
>
ADDR
Figure
2-1
PDP16-M
Configuration
Is-oosa

mummmmmmmm
« I
I
I
CONTROL MEMORY
BUS
INSTRUCTION
DECODER
DEC EN
STATE
GENERATOR
(DUHTIJJUOD
PROGRAM
COUNTER
umu’lbuN—O
CONTROL
TEST
CONDITION
FLAGS
IF
INSTRUCTION
TEST
A
<8lT>
MULTIPLEXER
02 DN DP OVF
OVF
BUS SENSE
AND
TERM
REGISTER
TRANSFER
EN
REGISTER
TRANSFER
DECODER
TR
RL'TRU
(EVOKE)
OPERATION
ARITHMETIC
AND
LOGIC UNIT
A
B
REGISTER REGISTER
TRANSFER
REGISTER
LOWER
I
UPPER
REGISTER
TRANSFER
BUS
Figure
2-2 CPU Block
Diagram
2—4
B
(0.15)
16-0060

HO
-3
SLOT
1/0-
2
SLOT
PCS
M7336
1/0
-1
SLOT MUX l/O
SLOT
MUX.1
117.329
,,
‘
31
ADAPT
M7333’3‘AND
M1307
MUXO
M7329
CONT
PROM3
M7327
CONT
PROMZ
M7327 312
M7313
CONT
PRDMi M7327
CONT
PROMO M7327 3:1 M7313
DAT PROMi M7327
DAT
PROM2
M7327 DAT PROM
1N7
M7311
_
'_
'
15
PDP-11
INT
M623:AND
M1307
GP13
M7311
'
-
'
14
AND M1307
AND
M1307
GP12
M7311
\_
_
_,
id
13
AND M1307
AND
M1307
GPll M7311
12
AND M1307
AND
M1307
GPA com M7300
11
AND
M1307
AND
M1307 GPA REG
M7301
(A818)
H851
10
AND M1103
L,PAGE,MUX
M7306
TR M7305
9
EVOKE
DEC
5
M7328
K
M7325
W
8
EVOKE DEC
4
M73213
(51717-32) MEM2
M7319/M7324
-'
7
EVOKE
DEC)
3 M73213
(SP1-1st Mew
M7319/M7324
'_
6
EVOKE
DEC
2
M7328
'c
M7307
V
5
EVOKE
01-:01
M7328
SP1-131147313
'
"
W
'
4
EVOKE
DEC 0 M7328
31717-32
M72313.
1..
3
FFA-sM73‘Ds
FF1-3
M7306 BUS
SENSE
AND TERM M7332
2
SWCAB
M908 EVOKE
M7310
_-
l
D
c e
A
16—0027
E]
OPTIONS
Figure
22-3
Logic
Assembly Configuration
Diagram
Table 2-1
Module
Slot
Assignment
and
Description
Slot
Module No.
Model No.
Configuration
Description
How
A
1 Test Slot
2
M7332
KBSiG-A
Basic
Timing
Control,
Data
Testing,
Bus
Terminator
3
M7318 M3160
Option
16-Bit
Registers
SP17
through
SP32
4
M7318
MS16-C
Option
16-Bit
Registers
SP1
through
SP16
5 M7307
MR16-A
Basic 4-W0rd Constant Generator
6
M7319
M8160
Option
MEM1
—
256
X 16
R/W
MOS
Memory
7
M7319 M8160
Option
MEM2
—
256
X
16
R/W
MOS
Memory
8
M7325
MR16-D
Option
24-Word
Constant Generator
9
M7305
MS16-A
Basic
16-Bit
Register
with
Byte
Control
10
M7301
KAR16 Basic ALU
and
Registers
A and B
11
M7300 KAC16
Basic
ALU
Control
Unit
12
M7311 DBilS—A
Basic GP11
—
16-Bit
1/0
TTL
Interface
13
M7311
DB16-A
Option
GP12
—
16-Bit l/O
TTL Interface
14
M7311
DB16-A
Option
GP13
—
16-Bit
1/0
TTL Interface
15
M7311
DB1l3-A
Option
lnterface
for
8
or 16
X 246
Data
PROM
16
M7313
DC16—A
Option
S|1
-
Asynchronous
Serial l/O
interface

Table 21
(Cent)
Module Slot
Assignment
and
Description
Slot
Module No.
Model
No.
Configuration
Description
17
M7313
DC16—A
Option
Sl2
—
Asynchronous
Serial ”0
Interface
4%
18
M7329
PCSlG-D
Basic
MUXO
—
ln'put
Multiplexer
19
M7329
PCS16—D
Option
MUX1
—
Input
Multiplexer
20
M7336
PCS16-A
Basic
Processor Control
.
NOTE
The
following
variation
is
permitted
for sockets
A6
and A7.
6
M7324
MS16—E
Option
MEM1
—
1K
X
16 R/W
MOS
Memory
7
M7324
MS16—E
Option
MEM2
-
1K
X
16
R/W MOS
Memory
Row B
1
Test
Slot
Row C
1 M7310
KEV16
Basic
PAGEO
and
PAGEl
Control
2
M7306
KFL16
Basic
FF1,
FF2 and FF3
3
M7328
PCS16-C
Basic
Evoke Decoder
000—037
1
4
M7328
PCS16-C
Basic
Evoke
Decoder
040—077
Ale
5
M7328
PCS16-C
Basic
Evoke Decoder
100—137
6
M7328
PCS16-C
Option
SP1—SP16
Evoke Decoder
140—177
7 M7328
PCSlG-C
Option
SP17—SP32 Evoke
Decoder
200—237
8 M7328
PCS16—C
Basic
Evoke
Decoder
240—277
9
M7306
KFL16
Basic
Link,
MUX
Select, Page
Select
10 M1307 KOR16—B Basic
Control
Logic
11
M1307 KOR16—B
Basic
Control
Logic
12 M1307
KOR1SB
Basic
Control
Logic
13 M1307
KOFl16-B Basic Control
Logic
14
M1307 KOR16-B
Basic
Control
Logic
15 M7327
MR16—FE
Option
8 X
246
Data
PROM
(lower
8
bits)
16
M7327
PCS16—B
Basic
Control
PROM
Loc 0000—0377
17
M7327
PCSlB-B
Option
Control PROM Loc 1000—1377
M
18
M1307
KOR16-A
Basic
Control
Logic
-
19
VD
Socket
Basic
EXT1—EXT23,
FF1—FF6, SI1, Sl2,
MSYNC
and SSYNC
20 VD Socket
Basic GPI2
HO
and
FF2
-
Row D
1
M908 Panel Socket
Basic Front Panel and Autostart
(SWCAB) 49o
2
M706 KFL16
Option
FF4,
FF5 and
FF6
9
M1103 KOR16-A
Basic
Control
Logic
1'0
M1307
KOR16—B Basic Control
Logic
11
M1307
KORlG—B
Basic
Control
Logic
2-6