Digital Equipment DF32 User manual

INSTRUCTION MANUAL
DISK FILE
AND
CONTROL
DIGITAL EQUIPMENT CORPORATION •MAYNARD, MASSACHUSETTS

DEC-D8-IDFA-D
DISK FILE AND CONTROL
INSTRUCTION MANUAL
DIGITAL EQUIPMENT CORPORATION •MAYNARD. MASSACHUSETTS

1st Printing March 1968
2nd Printing October 1968
3rd Printing November 1968
Copyright (C) 1968 by Digital Equipment Corporation
Inslruction times, operating speeds and the like are in-
cluded in this manual for reference only; they are not to
be taken as specifications.
The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC PDP
FLIP CHIP FOCAL
DIGITAL COMPUTER LAB

CONTENTS
CHAPTER 1
INTRODUCTION
Page
1.1 Purpose and Scope 1-1
1.2 Reference Documents and Programs 1-2
1.2.1 Manuals 1-2
1.2.2 Operation and Maintenance Programs 1-2
1.3 System Specifications 1-3
1.4 Physical Description 1-4
1.4.1 Disk File Assembly 1-5
CHAPTER 2
OPERATION AND PROGRAMMING
2-2
2-2
2-7
2-7
2-7
2-8
2-8
2-8
2-8
2-8
2-8
2-8
CHAPTER 3
PRINCIPLES OF OPERATION
3.1 Disk Format 3-1
3.2 NRZI Recording 3-2
3.3 General Operation of Search, Read, and Write 3-2
3.4 Timing Pulses 3-5
3.5 Detailed Logic Discussion 3-5
3.5.1 Address Searching 3-8
2.1 Operating Controls
2.2 IOT Instructions
2.3 Interrupt Flags
2.4 Error Flags
2.4.1 DRL Flag
2.4.2 PER Flag
2.4.3 WIA Flag
2.4.4 WIB Flag
2.4.5 EWL Flag
2.5 ADC Flag
2.6 Status Evaluation
2.7 Programming Example

CONTENTS (Cont)
Page
3.5.2 Read 3-10
3.5.3 Write 3-11
3.5.4 Track Head Selection 3-12
3.5.5 Continuous Data Transfers 3-12
3.5.6 Disk Expander Operation 3-12
3.5.7 Errors 3-13
3.5.8 Timing Track Writer 3-13
3.6 Special Circuits 3-16
3.6.1 G083 Differential Preamplifier 3-16
3.6.2 G284 Disk Writer 3-17
3.6.3 G285 Series Selector Switch 3-17
3.6.4 G286 Center Tap Selector 3-18
3.6.5 G702 Disk Simulator 3-19
3.6.6 54-4073 Photocell Amplifier 3-20
3.6.7 G680 Disk Head and Matrix 3-20
CHAPTER 4
INSTALLATION
4.1 Power and Cable Requirements 4-1
4.2 Mounting Suggestions 4-2
CHAPTER 5
MAINTENANCE
5.1 Disk/Head Cleaning Procedure 5-1
5.1 .1 Disk Removal 5-1
5.2 Troubleshooting 5-3
5.3 Disk Operating Procedure for Timing Track Writer DF32 5-7
ILLUSTRATIONS
1-1 DF32 System Block Diagram 1-1
1-2 DF32 Unit, Rack Mounted on Slide 1-4
1-3 Disk File Assembly 1-5
1-4 Disk File Assembly, Read/Write Head Locations 1-6
IV

ILLUSTRATIONS (Cont)
Page
2-1 DF32 Operating Control Panels 2-3
2-2 DS32 Operating Control Panel 2-3
3-1 Simplified Diagram of NRZI Recording 3-3
3-2 Simplified Diagram of Read and Write 3-4
3-3 Timing Diagram 3-10
3-4 Block Diagram, G083 Differential Preamplifier Module 3-16
3-5 Block Diagram, G284 Disk Writer Module 3-17
3-6 Block Diagram, G285 Series Selector Switch Module 3-18
3-7 Block Diagram, G286 Center Tap Selector Module 3-19
3-8 Block Diagram, G702 Disk Simulator Module 3-20
3-9 Block Diagram, G680 Disk Head and Matrix Module 3-21
4-1 Mounting Dimensions 4-2
4-2 PDP-8, PDP-8/S, PDP-8/I Cabling 4-3
5-1 Disk Removal 5-2
5-2 Head Cleaning 5-2
5-3 Timing Diagram for DF32 Disk Timing Track Writer 5-9
TABLES
1-1 Reference Documents 1-2
1-2 Operation and Maintenance Programs 1-3
1-3 Disk File System Specifications 1-3
2-1 DF32 Logic Rack Controls 2-2
2-2 DS32 Logic Rack Controls 2-2
2-3 IOT Instructions 2-4
2-4 IOT Instruction Analysis 2-5
3-1 Mnemonic Codes for DF32 Disk System 3-5
3-2 Mnemonic Codes for DF32 DECdisk Timing Track Writer 3-14

Typical PDP-8/S and Disk File Installation

CHAPTER 1
INTRODUCTION
The Type DF32 Disk File and Control, manufactured by Digital Equipment Corporation,
Maynard, Massachusetts Is afast, random or sequential access, bulk storage device used with the
PDP-8, PDP-8/S, or PDP-8/I computers for memory expansion. The DF32 provides acapacity of 32,768
13-bit words which are stored on arotating disk.
Up to three type DS32 Extender. Disks can be attached to the DF32, each of which extends
the bit capacity by 32K for atotal of 131 ,072 13-bit words as shown in Figure 1-1 .
The disk file is aprogram controlled device used in conjunction with the PDP-8, PDP-8/S,
or PDP-8/1, and operates through the 3-cycle data break facility of the computers.
1.1 PURPOSE AND SCOPE
This manual and the referenced documents herein provides operation, programming, and
maintenance information on both the Type DF32 Disk File and Control and DS32 Extender Disk. The
programming information, which includes sample programs for storage access, is presented in sufficient
detail to allow operating programs to be written. Although references throughout this manual are
primarily made to the PDP-8 computer, the information may be assumed to apply equally to the PDP-8/t
and PDP-8/S except where specifically noted otherwise.
PDP-8, 8/1 DF32 DISC
OR PDP-8/S CONTROL 32K
1r''''
DS32 DS32 DS32
1<1111
OISC
32K DISC
32K DISC
32K
Figure 1-1 DF32 System Block Diagram
1-1

The information in this manual is intended for use by persons familiar with DEC digital logic
and the operation of the PDP-8, PDP-8/S, and PDP-8/1 computers. The maintenance information and
routines require knowledge of the operation of bulk storage devices.
1.2 REFERENCE DOCUMENTS AND PROGRAMS
1.2.1 Manuals
Table 1-1 is alisting of the available publications which augment the information contained
in this manual. These publications may be obtained upon request from the nearest DEC office or from
the following address:
Digital Equipment Corporation
Main Street
Maynard, Massachusetts
Table 1-1
Reference Documents
Document Description
Digital Logic Handbook (CI 05)
PDP-8 Maintenance Manual (F87)
PDP-8/S Maintenance Manual
(F87S)
PDP-8/1 Maintenance Manual
Small Computer Handbook (C500)
Function and specifications of FLIP-CHIP
modules, cabinets, power supplies and
accessories.
Theory, operation, and maintenance
information on the PDP-8 Processor.
Theory, operation, and maintenance
information on the PDP-8/S Processor.
Theory, operation, and malntenace
information on PDP-8/1 Processor.
Describes operation and programming of
PDP-8 and PDP-8/S computers.
1.2.2 Operation and Maintenance Programs
Table 1-2 lists the operating and maintenance programs available for the DF32 and DS32
systems
.
1-2

Table 1-2
Operation and Maintenance Programs
Program Description •
DF32 Software Package
DF32 Diskless Logic Tests
(Maintenance)
DF32 Disk Data, Mini Disk
(Maintenance)
Perforated program tapes and description of
symbolic assembly, assembly language, and
utility subroutines.
Tests master and extender logic without the
disk in operation.
Tests the entire disk logic and disk including
the interface, addressing and data.
1.3 SYSTEM SPECIFICATIONS
The general specifications for the disk file systems are listed in Table 1-3.
Table 1-3
Disk File System Specifications
Storage capacity DF32 32,768 13-bit words
DS32 32,768 13-bit words per DS32
for atotal of 131,072, words per system
60-Hz power 50- Hz power
Data transfer rate 66 us per word 80 us per word
Average access time 16.67 ms 20.0 ms
Write lock switches Inhibitwritingon lower and/or upper 16Kof any 32K disk sur-
face, and can inhibit one or more, or all disks in an expanded
memory system
.
Addressing scheme Random or sequential addressing from to 32, 768 words, with
variable block size from one word to 4,096 words.
Data assembly Read/write to and from disk is in serial, with external
transfer in parallel, by word.
Timing track One, with one spare.
Address track One, with one spare.
Data tracks 16
Words per track 2,048
Recording method NRZI
Density 1100 bpi
Operating environment Ambient temperature: Maximum: 32 to 130°F
Recommended: 70 to 85°F
Relative humidity: 20 to 80%
Heat dissipation 500W
Power requirements 117V, 60 Hz, single phase, ac, for DF32 or DS32
117V, 50 Hz, single phase, ac, for DF32A or DS32A
1-3

1.4 PHYSICAL DESCRIPTION
The DF32 interface, control logic, and mechanical components are mounted as an integral
unit on aseparate frame as shown on Figure 1-2. This unit can be installed within aDEC standard
cabinet or any 19-in. relay rack. Track slides, attached on the side, allow the unit to be extended
for servicing. The basic DF32 unit consists of two mounting panels for the DEC modules, with the wiring
side facing the front of the unit. The disk file, consisting of a disk, drive motor, read/write heads, and
photo cell amplifier are mounted separately at the rear of the unit. The overall dimensions of the DF32
are as follows: 10-1/2 in. high, 19 in. wide, 23-1/4 in. deep (21-1/4 in. deep from mounting surface,
and 2-3/8 in .in front of mounting surface)
.
Each DS32 Extender is mounted on asimilar frame with track slides and has the same dimen-
sions as listed for the DF32. The DS32 unit, however, containing the disk file and analog-to-digital
conversion logic, is controlled by signals and data supplied from the DF32. Acomplete extended mem-
ory system consisting of one DF32, three DS32 units, aType 728 Power Supply and power control panel
can be housed in asingle bay of astandard rack or cabinet. When installed, sufficient cooling is pro-
vided by afan mounted on the bottom of each unit. Additional system arrangements are also available
to suit customer requirements.
Figure 1-2 DF32 Unit, Rack Mounted on Slide
1-4

1.4.1 Disk File Assembly
The disk file assembly is shown on Figure 1-3. The 16 read/write heads, four timing and
address heads, photocell amplifier circuit, and drive motor are attached to the base plate which is
suspended on four shock-absorbing mounts. The storage device is anickel-cobalt plated disk that
rotates with the motor shaft. The base plate and mounted components are completely enclosed by
removable dust covers on the top and bottom as shown. Two connector cards provide timing, address
signals, and data to the read/write heads cable. The physical position of the read/write heads on the
base plate is shown on Figure 1-4.
I
Figure 1-3 Disk File Assembly (Cover Removed)
1-5

Mm
Figure T-4 Disk File Assembly, Read/Write Head Locations
1-6

CHAPTER2
OPERATION AND PROGRAMMING
The programming of the DF32 is typical of an I/O device attached to the PDP-8. It uses the
IOT instructions to control operation and the 3-cycle data break facility of the PDP-8 to transfer data
between core memory and the DF32. The WC register (memory address 7750) of the data break facility
specifies the number of word transfers, and the CA register (memory address 7751) of the data break
facility specifies the current address of core memory that is to receive or send aword. The DF32 con-
tains amemory buffer (DMB) to buffer the data between core memory and the disk; and aDMA (disk
memory address) to specify the track address; the EMA (extended memory address) to specify the track
and unit number. The formats of these registers are shown below.
SPECIFIES THE TRACK ADDRESS
UNIT NUMBER TRACK NUMBER
t\t \
EMAS EMA4 EMA3 !EMA2 JEMA 1DMAO
There can be as many as four disk files within asystem: one DF32 and up to three DS32 disk
extenders. The disk extenders operate under the control of the DF32; therefore, only one disk file can
be selected at any one time for data transfers (i ,e., the control circuits handle only one block transfer
at any one time).
The programming of each disk is functionally identical. Unit number assignment for each
disk within the system is accomplished by the setting of aselection switch, provided on the front panel
of each disk file unit. The program selects the desired unit by appropriately programming the EMA re-
gister. To ensure proper operation, each disk file within aparticular system must be assigned its own
unique unit number.
The storage capacity of each disk is 32,768 13-bit words, or 16itracks of 2,048 13-bit words.
If the specified data transfer encompasses more than one track, the data transfer operation continues
automatically to the next track following one revolution of latency (33 ms). Similarly, operation con-
tinues to the next unit when the last track and track address have been accessed, provided that anext
unit exists.
2-1

2.1 OPERATING CONTROLS
Tables 2-1 and 2-2 show the operating controls for the DF32 and DS32, respectively.
Figures 2-1 and 2-2 show the control panels for the DF32 and the DS32, respectively.
2.2 IOT INSTRUCTIONS
Table 2-3 shows the IOT instructions for the DF32 system, and Table 2-4 shows acomplete
analysis of the IOT instructions.
Table 2-1
DF32 Control Panel Functions
Number Controls Function
1
2
3
4
5
6
7
8
Upper write lockout
Unit select
Lower write lockout
Disk lockout
Disk lockout 1
Disk lockout 2
Disk lockout 3
PDP-8, PDP-8/1
or PDP-8/S
Inhibits writing on the upper 16K word position of the DF32.
Assigns disk address 0, 1,2, or 3.
Inhibits writing on the lower 16K word position of the DF32.
Enables write lockout selection on unit 0.
Enables write lockout selection on unit 1.
Enables write lockout selection on unit 2.
Enables write lockout selection on unit 3.
Processor selection enables the system, through interface, to
be employed with both processors
.
Table 2-2
DS32 Control Panel Functions
Number Controls Function
1
2
3
Upper write lockout
Unit select
Lower write lockout
Inhibits writing on the upper 16K word positions on the
extension unit.
Assigns disk address, permitting the extender unit to be
operated with the master unit or as an additional extender
unit.
Inhibits writing on the lower 16K word position on the extend-
er unit.
2-2

4567
Figure 2-1 DF32 Operating Control Panels
132
Figure 2-2 DS32 Operating Control Panel
2-3

Table 2-3
IOT Instructions
Mnemonic Octal
Code Operation
DCMA
DMAR
DMAW
6601
6603
6605
DCEA
DSAC
DEAL
6611
6612
6615
DEAC 6616
Clear the disk memory address register, parity error, and completion flags.
This instruction clears the disk memory request flag and interrupt flags.
Load the disk memory address with information (initial address) in the ac-
cumulator. Then clear the AC. Begin to read information from the disk
into the specified core location. Clear parity error and completion flags.
Clear interrupt flags AC-,. DMA- ..
.
Load the disk memory address register with information (initial address) in
the accumulator (AC); then clear the AC. Begin to write information onto
the disk from the specified core location. Clear parity error and completion
flags. Clear interrupt flags. ACq,, DMAQ,..
Clear the disk extended address and memory address extension register.
Skip next instruction if the address confirmed flag is a1.Flag is set for
16 |js (AC is cleared).
Clear the disk extended address and memory address extension register.
Then load the disk extended address and memory address extension registers
with the track address data held in the accumulator.
IOT 6615 (TRANSMIT TO DF32)
I2
// // // V/A
I28K 96 K 6 4K 32K 16K %F2F,'/,
'// '// '// ////
IOT 6616 (RECEIVE STATUS FROM DF32)
PHOTO
CELL
SYNC 126K 96K 64K 32K 16K %F2F,
1*
DATA WRITE
REO. LOCK OR
LATE WONEXIST
DISK
PARITY
ERRORS
*WRITE LOCK SWITCH STATUS IS TRUE ONLY WHEN
DISK MODULE CONTAINS WRITE COMMAND.
Clear the accumulator. Then load the contents of the disk extended address
register into the accumulator to allow program evaluation. Skip next in-
struction if address confirmed flag is a1
.
2-4

Table 2-3 (Cont)
IOT Instructions
Mnemonic Octal
Code Operation
DFSE
DFSC
DMAC
6621
6622
6626
Skip next instruction if the parity error, data request late, or write lock
switch flag is a(no error).
Skip next instruction if the completion flag is a1(data transfer is
complete).
Clear the accumulator. Then load the contents of the disk memory address
register into the accumulator to allow program evaluation.
UMA0-11 >AL0-U
During read the final address will be the last address transferred +1
.
During write the final address will be the last address transferred.
Table 2-4
IOT Instruction Analysis
IOT INSTRUCTIONS
6601: DCMA
(1) Generates SCL (start clear) which clears:
(a) TRC flip-flop
(b) NED flip-flop
(c) MRS flip-flop
(d) ADC flip-flop
(e) ACH flip-flop
(f) DRL flip-flop
(g) PER flip-flop
Transfer Complete
Nonexistent Disk
Memory Request Sync
Address Confirmed
Address Compare Hold
Data Request Late
Parity Error
(2) Generates DTC (Disk Time Clear) which clears:
(a) MWR flip-flop
(b) TCA flip-flop
(c) TCB flip-flop
(3) Clears the disk memory address register
Memory Word Request
Time Counter "A"
Time Counter "B"
6602:
(1) Clears the accumulator
(2) Clears the R/W (read/write) flip-flop setting transfer direction to. read.
(3) Generates LAD (load address) which:
(a) Does ones transfer from the accumulator to the disk memory address register.
(b) Clears WCO flip-flop (word count overflow)
(c) Sets MRS flip-flop
2-5

Table 2-4 (Cont)
IOT Instruction Analysis
c.6604:
(1) Clears the accumulator
(2) Sets the R/V/ flip-flop, setting transfer direction to write.
(3) Generates LAD (see Section b, Paragraph 3).
(4) Sets DBR flip-flop (data break request).
NOTE
Combinations of the 660X IOT's are
6603 DMAR (Read)
6605 DMAW (Write)
d. 6611: DCEA
(1) Clears disk extended memory address register.
(2) Clears extended address register (for extended memory in computer).
e. 6612: DSAC
(1) Enables skip bus if ADC flip-flop is set (used primarily in diagnostic programming),
(2) Clears the accumulator
f. 6614:
(1) Does ones transfer from accumulator bits 1through 5to the disk extended
address register.
(2) Does ones transfer from disk "status register" to accumulator bits through 11 .
NOTE
Combinations of 661 XIOT's are
6615 DEAL (Clear and Load disk EMA register)
6616 DEAC (0--AC, load AC with disk EMA)
g. 6621: DFSE
(1) Enables skip bus if no error flags are up (skip on no error)
h. 6622: DFSC
(1) Enables skip bus if the TRC flip-flop is set and computer MB bif 9is a zero
(IOT 6622 used alone).
(2) Enables clear bus if computer MB bit 9is aone. (IOT 6622 used with IOT 6624.)
2-6