Epson S5U13A05B00C User manual

Rev. 1.1
S1D13A05 LCD/USB Companion Chip
S5U13A05B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X40A-G-004-02.1

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission
of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does
not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application
or use in any product or circuit and, further, there is no representation that this material is applicable to products
requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights
is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance
with this material will be free from any patent or copyright infringement of a third party. When exporting the
products or technology described in this material, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell,
to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the devel-
opment and/or manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2002-2018. All rights reserved.
Evaluation Board/Kit and Development Tool Important Notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-
ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished
products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any
kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even
during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
2Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1

S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 3
Rev. 1.1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 14
5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 18
6.3 S1D13A05 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . 18
6.5 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . 19
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 19
6.7 LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.1 LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7.3 TFT Type 3 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8 USB Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8.1 USB IRQ Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.9 External oscillator support for CLKI and CLKI2 . . . . . . . . . . . . . . . . . 20
6.10 External oscillator support for USBCLK . . . . . . . . . . . . . . . . . . . . 20
7 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
THIS PAGE LEFT BLANK

Introduction
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 5
Rev. 1.1
1 Introduction
This manual describes the setup and operation of the S5U13A05B00C Rev. 1.0 Evaluation
Board. The board is designed as an evaluation platform for the S1D13A05 LCD/USB
Companion Chip.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
vdc.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
vdc-document[email protected].com.

Features
6Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
2 Features
Following are some features of the S5U13A05B00C Rev. 1.0 Evaluation Board:
• 121-pin PFBGA S1D13A05 Embedded Memory LCD Controller with 256K bytes of
embedded SRAM.
• PCI bus operation through onboard PCI bridge.
• CPU/Bus interface header strips for non-PCI bus operation.
• Configuration options.
• On-board adjustable positive LCD bias power supply from +23V to +40V.
• On-board adjustable negative LCD bias power supply from -14V to -24V.
• Software adjustable backlight intensity support using PWMOUT.
• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.
• Direct interface for 18-bit Sharp HR-TFT LCD panel support.
• Direct interface for 18-bit Casio TFT LCD panel support.
• Direct interface for 18-bit TFT Type 2 LCD panel support
• Direct interface for 18-bit TFT Type 3 LCD panel support
• Direct interface for 18-bit TFT Type 4 (Epson ND-TFD) LCD panel support.
• Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.
• Connector for USB client support.
• Selectable clock source for CLKI and CLKI2.
• External oscillator support for CLKI and CLKI2.

Installation and Configuration
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 7
Rev. 1.1
3 Installation and Configuration
The S5U13A05B00C is designed to support as many platforms as possible. The
S5U13A05B00C incorporates a DIP switch and five jumpers which allow both the evalu-
ation board and the S1D13A05 LCD controller to be configured for a specified evaluation
platform.
3.1 Configuration DIP Switches
The S1D13A05 has seven configuration inputs (CNF[6:0]) which are read on the rising
edge of RESET#. In order to configure the S1D13A05 for multiple Host Bus Interfaces an
eight-position DIP switch (SW1) is required. The following figure shows the location of
DIP switch SW1 on the S5U13A05B00C.
Figure 3-1: Configuration DIP Switch (SW1) Location
DIP Switch - SW1

Installation and Configuration
8Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
All S1D13A05 configuration inputs are fully configurable using the eight position DIP
switch as described below.
Table 3-1: Configuration DIP Switch Settings
Switch
(SW1)
S1D13A05
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
SW1-5,
SW1-[3:1]
CNF4,
CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0 Host Bus Interface
1 0 0 0 SH-4/SH-3 interface, Big Endian
0 0 0 0 SH-4/SH-3 interface, Little Endian
1 0 0 1 MC68K #1, Big Endian
0 001 Reserved
1 0 1 0 MC68K #2, Big Endian
0 010 Reserved
1 0 1 1 Generic #1, Big Endian
0 0 1 1 Generic #1, Little Endian
1 100 Reserved
0 1 0 0 Generic #2, Little Endian
1 1 0 1 RedCap 2, Big Endian
0 101 Reserved
1 1 1 0 DragonBall, Big Endian
0 110 Reserved
X 111 Reserved
SW1-4 CNF3 Reserved. Must be set to 1.
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-7 CNF6 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1
SW1-8 - Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host
= Required settings when using the PCI Bridge FPGA

Installation and Configuration
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 9
Rev. 1.1
3.2 Configuration Jumpers
The S5U13A05B00C has five jumper blocks which configure various setting on the board.
The jumper positions for each function are shown below.
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 CLKI Source VCLKOUT from clock
synthesizer External oscillator (U6) BUSCLK from Header H5
JP2 CLKI2 Source MCLKOUT from clock
synthesizer External oscillator (U7) —
JP3 LCD Panel Voltage +3.3V LCDVCC +5V LCDVCC —
JP4 PCI_IRQ Disable Enable USB IRQ on PCI — Disable USB IRQ on PCI
JP5 GP00 Polarity on H3 Normal (Active High) Inverted (Active Low) GPO0 not sent to H3
= recommended settings

Installation and Configuration
10 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
JP1 - CLKI Source
JP1 selects the source for the CLKI input pin.
When the jumper is at position 1-2, the CLKI source is VCLKOUT from the Cypress clock
synthesizer (default setting).
When the jumper is at position 2-3, the CLKI source is the external oscillator at U6.
When no jumper is installed, the CLKI source is the BUSCLK signal from Header H5.
Figure 3-2: Configuration Jumper (JP1) Location
JP2 - CLKI2 Source
JP2 selects the source for the CLKI2 input pin.
When the jumper is at position 1-2, the CLKI2 source is MCLKOUT from the Cypress
clock synthesizer (default setting).
When the jumper is at position 2-3, the CLKI2 source is the external oscillator at U7.
Figure 3-3: Configuration Jumper (JP2) Location
JP1
VCLKOUT from
clock synthesizer
External
oscillator (U6)
BUSCLK from
Header H5
JP2
MCLKOUT from
clock synthesizer
External
oscillator (U7)

Installation and Configuration
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 11
Rev. 1.1
JP3 - LCD Panel Voltage
JP3 selects the voltage level to the LCD panel.
When the jumper is at position 1-2, the voltage level is +3.3V (default setting).
When the jumper is at position 2-3, the voltage level is +5.0V.
Note
When configured for Sharp HR-TFT, JP3 and JP5 must be set to position 1-2.
Figure 3-4: Configuration Jumper (JP3) Location
JP4 - PCI_IRQ Enable
JP4 selects whether the USB IRQ on PCI is enabled or disabled.
When the jumper is at position 1-2, the USB IRQ on PCI is enabled (default setting).
When no jumper is installed, the USB IRQ on PCI is disabled.
Figure 3-5: Configuration Jumper (JP4) Location
+5 LCDVCC
+3.3 LCDVCC
JP3
USB IRQ USB IRQ
JP4
on PCI enabled on PCI disabled

Installation and Configuration
12 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
JP5 - GPO0 Polarity on H3
JP5 selects the polarity of the GPO0 signal available on the TFT Type 3 Extended LCD
Connector H3.
When the jumper is at position 1-2, the GPO0 signal is sent directly (active high) to H3
(default setting).
When the jumper is at position 2-3, the GPO0 signal is inverted and then sent (active low)
to H3.
When no jumper is installed, GPO0 is not sent to H3.
Figure 3-6: Configuration Jumper (JP5) Location
Normal Inverted GPIO0 not
JP5
(Active High) (Active Low) sent to H1

CPU Interface
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 13
Rev. 1.1
4 CPU Interface
4.1 CPU Interface Pin Mapping
Note
1A0 for these bus interfaces is not used internally by the S1D13A05 and should be
connected to VSS.
2If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3These pins are not used in their corresponding host interface mode. Systems are
responsible for externally connecting them to IO VDD.
Table 4-1: Host Bus Interface Pin Mapping
S1D13A05
Pin Name Generic #1 Generic #2 Hitachi
SH-3/SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
AB[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1]
AB0 A01A0 A01LDS# A0 A01A01
DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]2D[15:0] D[15:0]
CS# External Decode CSn# External Decode CSn CSX
M/R# External Decode
CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLKO
BS# Connected to IOVDD3BS# AS# AS# Connected to IOVDD3
RD/WR# RD1# Connected to
IOVDD3RD/WR# R/W# R/W# R/W Connected to
IOVDD3
RD# RD0# RD# RD# Connected to
IOVDD3SIZ1 OE OE
WE0# WE0# WE# WE0# Connected to
IOVDD3SIZ0 EB1 LWE
WE1# WE1# BHE# WE1# UDS# DS# EB0 UWE
WAIT# WAIT# WAIT# WAIT#/
RDY# DTACK# DSACK1# N/A DTACK
RESET# RESET# RESET# RESET# RESET# RESET# RESET_OUT RESET

CPU Interface
14 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
4.2 CPU Bus Connector Pin Mapping
Table 4-2: CPU Bus Connector (H4) Pinout
Connector
Pin No. Comments
1Connected to DB0 of the S1D13A05
2Connected to DB1 of the S1D13A05
3Connected to DB2 of the S1D13A05
4Connected to DB3 of the S1D13A05
5Ground
6Ground
7Connected to DB4 of the S1D13A05
8Connected to DB5 of the S1D13A05
9Connected to DB6 of the S1D13A05
10 Connected to DB7 of the S1D13A05
11 Ground
12 Ground
13 Connected to DB8 of the S1D13A05
14 Connected to DB9 of the S1D13A05
15 Connected to DB10 of the S1D13A05
16 Connected to DB11 of the S1D13A05
17 Ground
18 Ground
19 Connected to DB12 of the S1D13A05
20 Connected to DB13 of the S1D13A05
21 Connected to DB14 of the S1D13A05
22 Connected to DB15 of the S1D13A05
23 Connected to RESET# of the S1D13A05
24 Ground
25 Ground
26 Ground
27 +12 volt supply
28 +12 volt supply
29 Connected to WE0# of the S1D13A05
30 Connected to WAIT# of the S1D13A05
31 Connected to CS# of the S1D13A05
32 Connected to MR# of the S1D13A05
33 Connected to WE1# of the S1D13A05
34 Connected to +3.3V

CPU Interface
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 15
Rev. 1.1
Table 4-3: CPU Bus Connector (H5) Pinout
Connector
Pin No. Comments
1Connected to AB0 of the S1D13A05
2Connected to AB1 of the S1D13A05
3Connected to AB2 of the S1D13A05
4Connected to AB3 of the S1D13A05
5Connected to AB4 of the S1D13A05
6Connected to AB5 of the S1D13A05
7Connected to AB6 of the S1D13A05
8Connected to AB7 of the S1D13A05
9Ground
10 Ground
11 Connected to AB8 of the S1D13A05
12 Connected to AB9 of the S1D13A05
13 Connected to AB10 of the S1D13A05
14 Connected to AB11 of the S1D13A05
15 Connected to AB12 of the S1D13A05
16 Connected to AB13 of the S1D13A05
17 Ground
18 Ground
19 Connected to AB14 of the S1D13A05
20 Connected to AB15 of the S1D13A05
21 Connected to AB16 of the S1D13A05
22 Connected to AB17 of the S1D13A05
23 Not connected
24 Not connected
25 Ground
26 Ground
27 +5 volt supply
28 +5 volt supply
29 Connected to RD/WR# of the S1D13A05
30 Connected to BS# of the S1D13A05
31 Connected to BUSCLK of the S1D13A05
32 Connected to RD# of the S1D13A05
33 Not connected
34 Not connected

LCD Interface Pin Mapping
16 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
5 LCD Interface Pin Mapping
Note
1 These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
S1D13A05 Hardware Functional Specification, document number X40A-A-001-xx.
2 GPO0 can be inverted on H1 by setting JP5 to 2-3.
Table 5-1: LCD Connector (H1)
Pin
Name
H1
Pin
No.
Monochrome
Passive Panel Color Passive Panel Color TFT Panel
Single
Single
Others Sharp
HR-TFT
Casio
TFT
TFT
Type 2
TFT
Type 3
TFT
Type 4
Format
1
Format
2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit 18-bit 18-bit 18-bit
FPDAT0 1 driven 0 D0 driven 0 D0 (B5)1D0 (G3)1D0 (R6)1R2 R3 R5 R5 R5 R5 R5 R5
FPDAT1 3 driven 0 D1 driven 0 D1 (R5)1D1 (R3)1D1 (G5)1R1 R2 R4 R4 R4 R4 R4 R4
FPDAT2 5 driven 0 D2 driven 0 D2 (G4)1D2 (B2)1D2 (B4)1R0 R1 R3 R3 R3 R3 R3 R3
FPDAT3 7 driven 0 D3 driven 0 D3 (B3)1D3 (G2)1D3 (R4)1G2 G3 G5 G5 G5 G5 G5 G5
FPDAT4 9 D0 D4 D0 (R2)1D4 (R3)1D4 (R2)1D8 (B5)1G1 G2 G4 G4 G4 G4 G4 G4
FPDAT5 11 D1 D5 D1 (B1)1D5 (G2)1D5 (B1)1D9 (R5)1G0 G1 G3 G3 G3 G3 G3 G3
FPDAT6 13 D2 D6 D2 (G1)1D6 (B1)1D6 (G1)1D10 (G4)1B2 B3 B5 B5 B5 B5 B5 B5
FPDAT7 15 D3 D7 D3 (R1)1D7 (R1)1D7 (R1)1D11 (B3)1B1 B2 B4 B4 B4 B4 B4 B4
FPDAT8 17 driven 0 driven 0 driven 0 driven 0 driven 0 D4 (G3)1B0 B1 B3 B3 B3 B3 B3 B3
FPDAT9 19 driven 0 driven 0 driven 0 driven 0 driven 0 D5 (B2)1driven0R0R2R2R2R2R2R2
FPDAT10 21 driven 0 driven 0 driven 0 driven 0 driven 0 D6 (R2)1driven 0 driven0R1R1R1R1R1R1
FPDAT11 23 driven 0 driven 0 driven 0 driven 0 driven 0 D7 (G1)1driven 0 driven0R0R0R0R0R0R0
FPDAT12 25 driven 0 driven 0 driven 0 driven 0 driven 0 D12 (R3)1driven0G0G2G2G2G2G2G2
FPDAT13 27 driven 0 driven 0 driven 0 driven 0 driven 0 D13 (G2)1driven 0 driven0G1G1G1G1G1G1
FPDAT14 29 driven 0 driven 0 driven 0 driven 0 driven 0 D14 (B1)1driven 0 driven0G0G0G0G0G0G0
FPDAT15 31 driven 0 driven 0 driven 0 driven 0 driven 0 D15 (R1)1driven0B0B2B2B2B2B2B2
FPDAT16 4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven0B1B1B1B1B1B1
FPDAT17 6 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven0B0B0B0B0B0B0
FPSHIFT 33 FPSHIFT DCLK CLK CLK CPH FPSHIFT
DRDY 35 &
38 MOD FPSHIFT2 MOD DRDY driven 0 no
connect INV INV DRDY
FPLINE 37 FPLINE LP GPCK STB LP FPLINE
FPFRAME 39 FPFRAME SPS GSRT STV STV FPFRAME
GND
2, 8,
14, 20,
26
GND
PWMOUT 28 PWMOUT
VLCD 30 Adjustable -24V to -14V negative LCD bias
LCDVCC 32 LCDVCC (3.3V or 5V)
+12V 34 +12V
VDDH 36 Adjustable +23V to +40V positive LCD bias
GPO0240 GPO0 (for controlling on-board LCD bias power supply on/off)

LCD Interface Pin Mapping
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 17
Rev. 1.1
Note
1If a panel type requiring extra control signals is selected (REG[0Ch] or REG[48h]),
GPIO[3:0] are used for the required signals. This leaves GPIO[7:4] available for USB
support or as GPIOs.
2If USB support is enabled (REG[4000h] bit 7 = 1), GPIO[7:4] are used by the USB
interface. GPIO[3:0] remain available for extended panel interface support (HR-TFT,
Casio or Type 2/3/4 TFT) or as GPIOs.
Table 5-2: Extended LCD Connector (H2)
Pin
Name
H2 Pin
No.
Mono
Passive
Panels
Color
Passive
Panels
Color TFT Panel
USB2
Others Sharp
HR-TFT1
Casio
TFT1
TFT
Type 21
TFT
Type 31
TFT
Type 4
9-bit 12-bit 18-bit 18-bit 18-bit 18-bit 18-bit 18-bit
GPIO0 1 GPIO0 PS POL VCLK CPV GPIO0 GPIO0
GPIO1 3 GPIO1 CLS GRES AP OE GPIO1 GPIO1
GPIO2 5 GPIO2 REV FRP POL POL GPIO2 GPIO2
GPIO3 7 GPIO3 SPL STH STH EIO GPIO3 GPIO3
GPIO4 9 GPIO4 USBPUP
GPIO5 11 GPIO5 USBDETECT
GPIO6 13 GPIO6 USBDM
GPIO7 15 GPIO7 USBDP
GND
2, 4, 6, 8,
10, 12, 14,
16
GND
Table 5-3: TFT Type 3 Extended LCD Connector (H3)
Pin Name H3 Pin number TFT Type 3 All Other LCD Display Modes
GPO0 1 GPO0 GPO0
GPO1 3 VCOM GPO1
GPO2 5 XOEV GPO2
GPO3 7 CMD GPO3
GPO4 9 PCLK1 GPO4
GPO5 11 PCLK2 GPO5
GPO6 13 XRESH GPO6
GPO7 15 XRESV GPO7
GPO8 17 XOHV GPO8
GPO9 19 XSTBY GPO9
GPO10 21 PMDE GPO10
NC 23 -
NC 25 -
GND 2-26 Even Numbers GND

Technical Description
18 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
6 Technical Description
6.1 PCI Bus Support
The S1D13A05 does not have on-chip PCI bus interface support. The S1D13A05B00C
uses the on-board PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13A05B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13A05 directly supports many other host
bus interfaces. Connectors H4 and H5 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 13.
Note
If a direct host bus interface is used, the PCI Bridge FPGA must be disabled using SW1-
8.
6.3 S1D13A05 Embedded Memory
The S1D13A05 has 256K bytes of embedded SRAM. The 256K byte display buffer address
space is directly and contiguously available through the 18-bit address bus.
6.4 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide
between -14V and -24V (Iout=45mA). Such a power supply (VLCD) has been provided on
the S5U13A05B00C board. VLCD can be adjusted using potentiometer R21 to provide an
output voltage from -14V to -24V, and is enabled/disabled using the S1D13A05 general
purpose signal, GPO0 (active high).
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements before connecting the panel.

Technical Description
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 19
Rev. 1.1
6.5 Adjustable LCD Panel Positive Power Supply
Most color passive LCD panels and most single monochrome 640x480 passive LCD panels
require a positive power supply to provide between +23V and +40V (Iout=45mA). Such a
power supply (VDDH) has been provided on the S5U13A05B00C board. VDDH can be
adjusted using R14 to provide an output voltage from +23V to +40V, and is
enabled/disabled using the S1D13A05 general purpose signal, GPO0 (active high).
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements before connecting the panel.
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13A05 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on LCD Connector H1.
6.7 LCD Panel Support
The S1D13A05 directly supports:
• Single-panel, single drive passive displays.
• 4/8-bit monochrome interface.
• 4/8/16-bit color interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• Direct support for 18-bit Sharp HR-TFT LCD panel.
• Direct support for 18-bit Casio TFT LCD panel.
• Direct support for 18-bit TFT Type 2 LCD panel.
• Direct support for 18-bit TFT Type 3 LCD panel.
• Direct support for 18-bit TFT Type 4 (Epson ND-TFD) LCD panel.
All the necessary signals are provided on the 40-pin LCD Connector H1, 16-pin Extended
LCD Connector H2, and the 26-pin TFT Type 3 Extended LCD Connector H3. For detailed
connection information, see Section 5, “LCD Interface Pin Mapping” on page 16.
6.7.1 LCD Connector
The LCD Connector H1 provides all LCD panel signals required for Active Matrix TFT
and Passive LCD panels. These signals are buffered to either a 3.3V level or a 5.0V level
depending on the setting of JP3. See Table 3-2: “Jumper Summary” on page 9.

Technical Description
20 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
6.7.2 Extended LCD Connector
The S1D13A05 directly supports several extended panel types such as the Sharp 18-bit HR-
TFT, Casio TFT and compatible panels. The Extended LCD Connector H2 provides the
extra signals required to support these panels. The signals on this connector are provided
directly from the S1D13A05 without any buffering and are 3.3V signals.
6.7.3 TFT Type 3 Extended LCD Connector
The S1D13A05 directly supports 18-bit TFT Type 3 compatible panels. The TFT Type 3
Extended LCD Connector H3 provides the extra signals required to support panels
compatible with the specified timings. The signals on this connector are provided directly
from the S1D13A05 without any buffering and are 3.3V signals.
6.8 USB Support
The S1D13A05 USB controller provides a Revision 1.1 compliant USB client. The
S1D13A05 acts as a USB device and connects to an upstream hub or USB host through
connector J1 on the S5U13A05B00C evaluation board. Clamping diodes have been added
to protect the USB bus from ESD and shorting.
6.8.1 USB IRQ Support
The S1D13A05 supports interrupts using the output pin, IRQ. In order to support interrupts
from the USB client of the S1D13A05, the S5U13A05B00C evaluation board connects
IRQ to PCI interrupt INTA# from the PCI slot. The IRQ pin output to the PCI bus can be
disabled by removing jumper JP4.
6.9 External oscillator support for CLKI and CLKI2
The S1D13A05 can use CLKI and CLKI2 sources other than the Clock Synthesizer. Two
+3.3V supplied 14-pin DIP package sized oscillator slots are present on the board.
6.10 External oscillator support for USBCLK
The S1D13A05 can use a 48MHz oscillator for the USBCLK source, instead of the USB
crystal oscillating circuit. A +3.3V supplied 14-pin DIP package sized oscillator slot is
present on the board.
Note
The board supports either an external crystal or an external oscillator for USB function-
ality. Only one can be enabled at a time. If an external crystal is used for the clock
source for the USB module, the USBCLK input needs to be disabled by using a pull-