Epson S5U13A05B00C User manual

Rev. 1.1
S1D13A05 LCD/USB Companion Chip
S5U13A05B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X40A-G-004-02.1

NOTICE
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©SEIKO EPSON CORPORATION 2002-2018. All rights reserved.
Evaluation Board/Kit and Development Tool Important Notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-
ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished
products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any
kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even
during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
2Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1

S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 3
Rev. 1.1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 14
5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 18
6.3 S1D13A05 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . 18
6.5 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . 19
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 19
6.7 LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.1 LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7.3 TFT Type 3 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8 USB Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8.1 USB IRQ Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.9 External oscillator support for CLKI and CLKI2 . . . . . . . . . . . . . . . . . 20
6.10 External oscillator support for USBCLK . . . . . . . . . . . . . . . . . . . . 20
7 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Introduction
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 5
Rev. 1.1
1 Introduction
This manual describes the setup and operation of the S5U13A05B00C Rev. 1.0 Evaluation
Board. The board is designed as an evaluation platform for the S1D13A05 LCD/USB
Companion Chip.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
vdc.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
vdc-document[email protected].com.

Features
6Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
2 Features
Following are some features of the S5U13A05B00C Rev. 1.0 Evaluation Board:
• 121-pin PFBGA S1D13A05 Embedded Memory LCD Controller with 256K bytes of
embedded SRAM.
• PCI bus operation through onboard PCI bridge.
• CPU/Bus interface header strips for non-PCI bus operation.
• Configuration options.
• On-board adjustable positive LCD bias power supply from +23V to +40V.
• On-board adjustable negative LCD bias power supply from -14V to -24V.
• Software adjustable backlight intensity support using PWMOUT.
• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.
• Direct interface for 18-bit Sharp HR-TFT LCD panel support.
• Direct interface for 18-bit Casio TFT LCD panel support.
• Direct interface for 18-bit TFT Type 2 LCD panel support
• Direct interface for 18-bit TFT Type 3 LCD panel support
• Direct interface for 18-bit TFT Type 4 (Epson ND-TFD) LCD panel support.
• Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.
• Connector for USB client support.
• Selectable clock source for CLKI and CLKI2.
• External oscillator support for CLKI and CLKI2.

Installation and Configuration
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Rev. 1.1
3 Installation and Configuration
The S5U13A05B00C is designed to support as many platforms as possible. The
S5U13A05B00C incorporates a DIP switch and five jumpers which allow both the evalu-
ation board and the S1D13A05 LCD controller to be configured for a specified evaluation
platform.
3.1 Configuration DIP Switches
The S1D13A05 has seven configuration inputs (CNF[6:0]) which are read on the rising
edge of RESET#. In order to configure the S1D13A05 for multiple Host Bus Interfaces an
eight-position DIP switch (SW1) is required. The following figure shows the location of
DIP switch SW1 on the S5U13A05B00C.
Figure 3-1: Configuration DIP Switch (SW1) Location
DIP Switch - SW1

Installation and Configuration
8Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
All S1D13A05 configuration inputs are fully configurable using the eight position DIP
switch as described below.
Table 3-1: Configuration DIP Switch Settings
Switch
(SW1)
S1D13A05
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
SW1-5,
SW1-[3:1]
CNF4,
CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0 Host Bus Interface
1 0 0 0 SH-4/SH-3 interface, Big Endian
0 0 0 0 SH-4/SH-3 interface, Little Endian
1 0 0 1 MC68K #1, Big Endian
0 001 Reserved
1 0 1 0 MC68K #2, Big Endian
0 010 Reserved
1 0 1 1 Generic #1, Big Endian
0 0 1 1 Generic #1, Little Endian
1 100 Reserved
0 1 0 0 Generic #2, Little Endian
1 1 0 1 RedCap 2, Big Endian
0 101 Reserved
1 1 1 0 DragonBall, Big Endian
0 110 Reserved
X 111 Reserved
SW1-4 CNF3 Reserved. Must be set to 1.
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-7 CNF6 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1
SW1-8 - Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host
= Required settings when using the PCI Bridge FPGA

Installation and Configuration
S5U13A05B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 9
Rev. 1.1
3.2 Configuration Jumpers
The S5U13A05B00C has five jumper blocks which configure various setting on the board.
The jumper positions for each function are shown below.
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 CLKI Source VCLKOUT from clock
synthesizer External oscillator (U6) BUSCLK from Header H5
JP2 CLKI2 Source MCLKOUT from clock
synthesizer External oscillator (U7) —
JP3 LCD Panel Voltage +3.3V LCDVCC +5V LCDVCC —
JP4 PCI_IRQ Disable Enable USB IRQ on PCI — Disable USB IRQ on PCI
JP5 GP00 Polarity on H3 Normal (Active High) Inverted (Active Low) GPO0 not sent to H3
= recommended settings

Installation and Configuration
10 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
JP1 - CLKI Source
JP1 selects the source for the CLKI input pin.
When the jumper is at position 1-2, the CLKI source is VCLKOUT from the Cypress clock
synthesizer (default setting).
When the jumper is at position 2-3, the CLKI source is the external oscillator at U6.
When no jumper is installed, the CLKI source is the BUSCLK signal from Header H5.
Figure 3-2: Configuration Jumper (JP1) Location
JP2 - CLKI2 Source
JP2 selects the source for the CLKI2 input pin.
When the jumper is at position 1-2, the CLKI2 source is MCLKOUT from the Cypress
clock synthesizer (default setting).
When the jumper is at position 2-3, the CLKI2 source is the external oscillator at U7.
Figure 3-3: Configuration Jumper (JP2) Location
JP1
VCLKOUT from
clock synthesizer
External
oscillator (U6)
BUSCLK from
Header H5
JP2
MCLKOUT from
clock synthesizer
External
oscillator (U7)