Freescale Semiconductor 56852 User manual

56F850
16-bit Digital Signal Controllers
freescale.com
56852
Evaluation Module User Manual
DSP56852EVMUM
Rev. 3
07/2005

TABLE OF CONTENTS
Table of Contents, Rev. 3
Freescale Semiconductor i
Preface vii
Chapter 1
Introduction
1.1 56852EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 56852EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56852EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1 56852 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI Serial EEPROM/Data FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 RS-232 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7 Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8.1 JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.9 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.12.1 Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.13 Daughter Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.13.1 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-19
2.13.2 Peripheral Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-21
2.14 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

DSP56852EVM User Manual, Rev. 3
ii Freescale Semiconductor
Appendix A
DSP56852EVM Schematics
Appendix B
DSP56852EVM Bill of Material

LIST OF FIGURES
List of Figures, Rev. 3
Freescale Semiconductor iii
1-1 Block Diagram of the 56852EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F801EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the 56852EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External CS0 Memory Interface. . . . . . . . . . . . . . . . . . . 2-3
2-2 Schematic Diagram of the External CS1/CS2 Memory Interface. . . . . . . . . . . . . . . 2-4
2-3 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-7 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-8 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-9 Schematic Diagram of the RESET Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-11 Codec Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-12 CS4218 Stereo Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

DSP56852EVM User Manual, Rev. 3
iv Freescale Semiconductor

LIST OF TABLES
List of Tables, Rev. 3
Freescale Semiconductor v
1-1 56F801EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SPI Port Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-4 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-9 SSI Port Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-10 GPIO Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-11 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-12 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-21

DSP56852EVM User Manual, Rev. 3
vi Freescale Semiconductor

Preface, Rev. 3
Freescale Semiconductor vii
Preface
This reference manual describes in detail the hardware on the 56852 Evaluation Module.
Audience
This document is intended for application developers who are creating software for devices using
the Freescale 56852 part.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1, Introduction - provides an overview of the EVM and its features.
•Chapter 2, Technical Summary - describes in detail the 56852 hardware.
•Appendix A, DSP56852EVM Schematics - contains the schematics of the 56852EVM.
•Appendix B, DSP56852EVM Bill of Material - provides a list of the materials used on the
56852EVM board.
Suggested Reading
More documentation on the 56852 and the 56852EVM kit may be found at URL:
www.freescale.com

DSP56852EVM User Manual, Rev. 3
viii Freescale Semiconductor
Conventions
This manual uses the following notational conventions:
Term or Value Symbol Examples Exceptions
Active High Signals
(Logic One)
No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
Hexadecimal Values Begin with a “$” sym-
bol
$0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positive
unless specifically
noted as a negative
value
5
-10
Voltage is often shown as
positive: +3.3V
Blue Text Linkable on-line ...refer to Chapter 7,
License
Bold Reference sources,
paths, emphasis
...see:
www.freescale.com

Preface, Rev. 3
Freescale Semiconductor ix
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference.
Codec COder/DECoder; a part used to convert analog signals to digital (coder)
and digital signals to analog (decoder)
DSP Digital Signal Processor or Digital Signal Processing
EEPROM Electrically Erasable Programmable Read-Only Memory
EOnCE Enhanced On-Chip Emulation; a debug bus and port created by Freescale
to enable a designer to create a low-cost hardware interface for a
professional-quality debug environment
EVM Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application
GPIO General Purpose Input and Output port on Freescale’s family of
controllers; does not share pin functionality with any other peripheral on
the chip and can only be set as an input, output or level-sensitive
interrupt input
IC Integrated Circuit
ISSI Improved Synchronous Serial Interface port on Freescale’s family of
controllers
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LED Light Emitting Diode
MBGA MAP Ball Grid Array package
MPIO Multi Purpose Input and Output port on Freescale’s family of controllers;
shares package pins with other peripherals on the chip and can function
as a GPIO
PCB Printed Circuit Board
PLL Phase Locked Loop
RAM Random Access Memory
ROM Read Only Memory
SCI Serial Communications Interface port on Freescale’s family of
controllers

DSP56852EVM User Manual, Rev. 3
xFreescale Semiconductor
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, Freescale Semiconductor
[2] DSP56852 Digital Signal Processor User’s Manual, Freescale Semiconductor
[3] DSP56852 Digital Signal Processor Technical Data, Freescale Semiconductor
SPI Serial Peripheral Interface port on Freescale’s family of controllers
SRAM Static Random Access Memory
SSI Synchronous Serial Interface port on Freescale’s family of controllers
WS Wait State

Introduction, Rev. 3
Freescale Semiconductor 1-1
Chapter 1
Introduction
The 56852EVM is used to demonstrate the abilities of the 56852 and to provide a hardware tool
allowing the development of applications that use the 56852.
The 56852EVM is an evaluation module board that includes a 56852 part, 16-bit stereo codec,
external memory and a daughter card expansion interface. The daughter card expansion
connectors are for signal monitoring and user feature expandability.
The 56852EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56852EVM facilitate evaluation of the feature set
and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the controller's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the chip
is available to the user.
1.1 56852EVM Architecture
The 56852EVM facilitates the evaluation of various features present in the 56852 part. The
56852EVM can be used to develop real-time software and hardware products based on the
56852. The 56852EVM provides the features necessary for a user to write and debug software,

DSP56852EVM User Manual, Rev. 3
1-2 Freescale Semiconductor 
demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56852EVM is flexible enough to allow a user to fully exploit
the 56852's features to optimize the performance of their product, as shown in Figure 1-1.
56852
RESET
MODE
Address,
Data &
Control
JTAG/EOnCE
XTAL/EXTAL
SPI
SCI
ISSI
GPIO
+1.8V,
+3.3V
& GND
Peripheral
Daughter
Card
Connector
RESET
LOGIC
MODE
LOGIC
CS0
(Program Memory)
128Kx16-bit SRAM
Memory
Daughter Card
Connector
JTAG
Connector
Parallel
JTAG
Interface
4.00MHz
Crystal
DSub
25-Pin
CS1/CS2
(Data Memory)
128Kx16-bit SRAM
DSub
9-Pin
Debug
LEDs
Stereo 16-bit
Codec
RS-232
Interface
SPI Data
FLASH
1M-bit
IRQ Interface
IRQ
Amp
Stereo Line In
Stereo Line Out
Headphone Jack
Power Supply
+1.8V, +3.3V &
+5.0V
Figure 1-1. Block Diagram of the 56852EVM
1.2 56852EVM Configuration Jumpers
Ten jumper groups, (JG1-JG10), shown in Figure 1-2, are used to configure various features on
the 56852EVM board. Table 1-1 describes the default jumper group settings.

DSP56852EVM
J3
JTAG
U7
S/N
P2
Y1
U1
S1
S2
S3
S4
P1
LEDS
JG3
JG8
U5
RESET
IRQB
IRQA
1
2
7
8
JG2
J2
P5
1
JG3
3JG7
JG2
JG7 TB1
P6
P3 P4
JG4
J1
JG6
HEADPHONE
LINE
LINE
IN OUT
JG8
JG4
3
1
JG6
JG5
U3
U2
JG1
RE10520B REV
JG10
1
2
3
4
JG5
1
2
5
6
JG10
JG1
S5
12
34
12
910
JG9
JG9
S5
56852EVM Configuration Jumpers
Introduction, Rev. 3
Freescale Semiconductor 1-3
Figure 1-2. 56F801EVM Jumper Reference
Table 1-1. 56F801EVM Default Jumper Options
Jumper
Group Comment Jumpers Connections
JG1 Enable on-board Byte selectable SRAM via CS1/CS2 (U3) 1-2, 3-4
JG2 Enable on-board Word selectable SRAM via CS0 (U2) 1–2
JG3 Use on-board XTAL crystal input for oscillator 1–2
JG4 Use on-board EXTAL crystal input for oscillator 2–3
JG5 Enable SCI Port to RS-232 transceiver 1–2, 3-4
JG6 Enable SPI Port to Serial EEPROM/Data FLASH 1–2, 3–4, 5–6 & 7–8
JG7 Enable on-board Parallel JTAG Host/Target Interface NC
JG8 Enable RS-232 output NC
JG9 Enable SSI Port for CODEC data. 1-2, 3-4, 5-6, 7-8,
9-10
JG10 Enable GPIO for CODEC control. 1-2, 3-4, 5-6

DSP56852EVM User Manual, Rev. 3
1-4 Freescale Semiconductor 
1.3 56852EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply or external +5.0V DC lab power supply to the 56852EVM board.
PC-compatible
Cable
Computer
Parallel Extension
56852EVM
External
+12.0V
Power
P1
P2
Connect cable
to Parallel/Printer port
with 2.1mm,
receptacle
connector
+5.0V
Lab
Supply
TB1
Figure 1-3. Connecting the 56852EVM Cables
Perform the following steps to connect the 56852EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56F801EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the external
+5.0V DC 1A lab power supply is not plugged into a +120V AC power source.
4. Connect the 2.1mm output power plug from the external switching power supply into P2,
shown in Figure 1-3, on the 56852EVM board. Optionally, attach an external +5.0V DC
lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.

Technical Summary, Rev. 3
Freescale Semiconductor 2-1
Chapter 2
Technical Summary
The 56852EVM is designed as a versatile controller development card for developing
real-time software and hardware products to support a new generation of applications in
digital and wireless messaging, digital answering machines, feature phones, modems, and
digital cameras. The power of the 16-bit 56852, combined with the on-board
128K u16-bit external program/data static RAM (SRAM), 128K u16-bit external
data/program SRAM, RS-232 interface, stereo 16-bit codec interface, Daughter Card
Expansion interface and parallel JTAG interface, makes the 56852EVM ideal for
developing and implementing many audio and voice algorithms, as well as for learning the
architecture and instruction set of the 56852 processor.
The main features of the 56852EVM, with board and schematic reference designators
include:
• 56852 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]
• External fast static RAM (FSRAM) memory, configured as:
— 128Ku16-bit of memory [U2] with 1 wait state at 120MHz via CS0
— 128Ku16-bit of memory [U3] with 1 wait state at 120MHz via CS1/CS2
• 1M-bit Serial EEPROM/Data FLASH [U4]
• 4.00MHz crystal oscillator for controller frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG3 and JG4]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P1]
• RS-232 interface for easy connection to a host processor [U6 and P6]
• 16-bit stereo codec interface [U5, JG9, JG10, P3 and P4]
• Stereo headphone interface [U12 and P5]

DSP56852EVM User Manual, Rev. 3
2-2 Freescale Semiconductor 
• Codec sample rate selector [S4]
• Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI,
ISSI, SPI or GPIO-compatible peripheral to the controller [J2]
• Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the controller [J1]
• On-board power regulation from an external +12V DC-supplied power input [P2]
• On-board power regulation from an optional +5V DC-supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]
• Boot MODE selector [S5]
• Manual RESET push-button [S3]
• Manual interrupt push-button for IRQA [S1]
• Manual interrupt push-button for IRQB [S2]
2.1 56852
The 56852EVM uses a Freescale DSP56852VF120 part, designated as U1 on the board and in the
schematics. This part will operate at a maximum speed of 120MHz. A full description of the
56852, including functionality and user information, is provided in these documents:
•DSP56852 Technical Data, (DSP56852):Provides features list and specifications,
including signal descriptions, DC power requirements, AC timing requirements and
available packaging
•DSP56852 User’s Manual, (DSP56852UM): Provides an overview description of the
controller and detailed information about the on-chip components, including the memory
and I/O maps, peripheral functionality, and control/status register descriptions for each
subsystem
• DSP56800E Reference Manual, (DSP56800ERM): Provides a detailed description of the
core processor, including internal status and control registers and a detailed description of
the family instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com

Program and Data Memory
Technical Summary, Rev. 3
Freescale Semiconductor 2-3
2.2 Program and Data Memory
The 56852EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is controlled
by CS0 and SRAM bank 1 is controlled by CS1 and CS2.
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128Ku16-bit Fast Static RAM (GSI GS72116,
labeled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
CS0 can be configured to use this memory bank as 16-bit program memory, data memory, or
both. Additionally, CS0 can be configured to assign this memory’s size and starting address to
any modulo address space.
This memory bank will operate with one wait state access while the 56852 is running at 120MHz
and can be disabled by removing the jumper at JG2.
56852 GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
1 2
JG2
+3.3V
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
CS0
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128Ku16-bit Fast Static RAM (GSI
GS72116, labelled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable program memory, data memory, or both. Additionally, CS1 and CS2 can be
configured to assign this memory’s size and starting address to any modulo address space.

DSP56852EVM User Manual, Rev. 3
2-4 Freescale Semiconductor 
This memory bank will operate with one wait state access while the 56852 is running at 120MHz
and can be disabled by removing the jumpers at JG1.
56852 GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
JG1
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
CS1
CS2
1
3
2
4
LB
HB
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface